DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/26/2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 1/26/2026. Claims 1 and 14 have been amended. No claims have been added or canceled. Claims 1-2,4-7,9 and 11-13 were withdrawn. Currently, claims 14-23 are pending.
Response to Arguments
Applicant’s arguments filed 1/26/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14, 16-18, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Banno et al. (US 20210050517) in view of Tada (US 10615339), Fu et al. (US 20210104666), and Chen et al. (US 20200106011).
Regarding claim 14, Banno teaches, in Fig. 26, a resistive memory device (Abstract, [0231]), comprising:
a) a bottom insulator (313, [0234]) on a substrate interlayer dielectric (311/312, [0234]);
c) a bottom electrode (321a/322a, [0236]) covering at least a portion of the bottom insulator (313);
d) a top insulator (315, [0234]) on the bottom electrode (321a/322a);
e) a bottom electrode hard mask (314, [0235]; see Fig. 17 and [0183] how 314, labelled as 214 in Fig. 17, is configured as a hard mask) on the top insulator (315) (e.g., layer 314 is on the bottom surface of the top insulator 315),
f) a cell plate layer (302/303, [0233]) in direct contact with a top surface of the bottom electrode hard mask (314), sidewalls of the top insulator (315), sidewalls of the bottom electrode (221a/222a), and sidewalls of the bottom insulator (313); and
g) an electrical contact (323a/325a, [0236]) connected to the cell plate layer (302/303) (see Fig. 26).
Banno does not teach b) vias in the bottom insulator and the substrate ILD, the vias having a via metal and a flat via surface; c) that the bottom electrode fully covers the vias; e) that the bottom electrode hard mask is wider than the vias; and f) that the cell plate layer is in direct contact with a recessed surface of the substrate ILD.
In a similar field of endeavor, Tada teaches, in Fig. 8, f) that the cell plate layer (105/106/107; col. 6, lines 15-20) is in direct contact with a recessed surface of the substrate ILD (102; col. 6, lines 15-20) (see Fig. 8), in order to “provide a variable resistance element in which a programming operation is stabilized and leakage current is reduced” (col. 1, lines 25-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cell plate layer configuration of Banno with the cell plate layer configuration of Tada, in order to provide a variable resistance element in which a programming operation is stabilized and leakage current is reduced (col. 1, lines 25-35).
Banno in view of Tada does not teach b) vias in the bottom insulator and the substrate ILD, the vias having a via metal and a flat via surface; c) that the bottom electrode fully covers the vias; and e) that the bottom electrode hard mask is wider than the vias.
In a similar field of endeavor, Fu teaches, in Fig. 2B,
b) vias (106, [0019]) in the bottom insulator (104, [0017]), the vias (106) having a via metal ([0017]) and a (top) flat via surface (see Fig. 2B);
c) that the bottom electrode (112, [0019]) fully covers the vias (106); and
e) that the bottom electrode hard mask (116, [0021]; see Fig. 1B and [0024] how 116 is configured as a hard mask) is wider than the vias (106) (see Fig. 2B),
in order to reduce the production cost ([0054]) and use interconnection space more efficiently.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the via configuration of Banno in view of Tada with the via configuration of Fu, in order to reduce the production cost ([0054]) and use interconnection space more efficiently.
Banno in view of Tada and Fu does not explicitly teach b) that the vias are in the substrate ILD.
In a similar field of endeavor, Chen teaches, in Fig. 21, b) that the vias (109 and 306, [0019], [0043]) are in the substrate ILD (302a-302c; labelled in Fig. 14; [0035]), in order to couple the resistive memory device to an access device arranged within the substrate ([0035]) using efficient interconnection space.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the resistive memory device of Banno in view of Tada and Fu with the via configuration of Chen, in order to couple the resistive memory device to an access device arranged within the substrate ([0035]) using efficient interconnection space.
Regarding claim 16, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno further teaches, in Fig. 26, that each of the bottom electrodes (321a/322a) comprises a sidewall (right side, see Fig. 26).
Regarding claim 17, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno further teaches, in Fig. 26, that the cell plate layer (302/303) covers one or more bottom electrodes (321a/322a) (see Fig. 26).
Regarding claim 18, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Tada further teaches, in Fig. 8, that the cell plate layer (105/106/107) is encapsulated by an ILD layer (104; col. 6, lines 15-20), and electrical contact to the cell plate layer is made by top contacts or vias (115a/115b; col. 12, lines 50-60) through the ILD layer (104).
Regarding claim 21, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno further teaches, in Fig. 26, that the bottom insulator (313), the bottom electrode (321a/322b), the top insulator (315) and bottom electrode hard mask (314) comprise a stack of materials, and the cell plate layer (302/303) is a conformal layer that is over the stack of materials. Alternatively, Fu also teaches, in Fig. 2B, that the bottom insulator (104, [0016]), the bottom electrode (112), the top insulator (114, [0020]) and bottom electrode hard mask (116) comprise a stack of materials, and the cell plate layer (132/134/136/142, [0026], [0032]) is a conformal layer that is over the stack of materials.
Tada further teaches, in Fig. 8, that the stack of materials (101, 103) are adjacent to the recessed surface of the substrate ILD (102), and the cell plate layer (105/106/107) is within a recess of the substrate ILD (102).
Regarding claim 22, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 21. Fu further teaches, in Fig. 2B, that the stack of materials (104, 112, 114, and 116) is at a height above the recess of the substrate ILD (because the substrate ILD 102 is below 104).
Regarding claim 23, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 22. Tada further teaches that the cell plate layer (105/106/107) is provided over the stack of materials (as explained in claim 21 above) and within the recess (of 102) (see Fig. 8).
Banno further teaches, in Fig. 26, that a hardmask (304a, [0233]) is provided over the stack of materials (321a/322a, 313, 314, and 315) and within the recess, and the electrical contact (323a/325a) extends through an opening in the hardmask (304a) to contact the cell plate layer (302/303) (see Fig. 26).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Banno et al. (US 20210050517) in view of Tada (US 10615339), Fu et al. (US 20210104666), and Chen et al. (US 20200106011), and further in view of Jameson et al. (US 10497868).
Regarding claim 15, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno further teaches that the cell plate layer (302/303) comprises a switching layer (303b, labelled as 203b in Fig. 25) comprising SiO2 ([0125]) and a cap layer (302b, labelled as 202b in Fig. 25) comprising tantalum nitride ([0116]).
Tada further teaches that the anode layer (106, Fig. 8) comprises HfxTe1-x. (col. 7, line 65 – col. 8, line 10; Hf).
Banno in view of Tada, Fu, and Chen does not teach that the cap layer comprises TaxSi1-x.
In a similar field of endeavor, Jameson teaches, in Fig. 2, that the cap layer (208) comprises TaxSi1-x (col. 4, lines 15-25; Ta), in order to make an RRAM/CBRAM element “compatible with existing CMOS fabrication processes” and “able to withstand anneals of at least 400° C” (col. 1, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the resistive memory device of Banno in view of Tada, Fu, and Chen with the cap layer of Jameson, in order to make an RRAM/CBRAM element compatible with existing CMOS fabrication processes and able to withstand anneals of at least 400° C.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Banno et al. (US 20210050517) in view of Tada (US 10615339), Fu et al. (US 20210104666), and Chen et al. (US 20200106011), and further in view of Sato et al. (US 9444040).
Regarding claim 19, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno in view of Tada, Fu, and Chen does not explicitly teach that a shape of each of the bottom electrodes is rounded.
In a similar field of endeavor, Sato teaches that a shape of each of the bottom electrodes (120, Fig. 6D) is rounded (Sato claim 2), in order to “lead to a more robust conductive path with higher retention” (col. 7, lines 20-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bottom electrode shapes of Banno in view of Tada, Fu, and Chen with the bottom electrode shape of Sato, in order to have a more robust conductive path with higher retention (col. 7, lines 20-25).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Banno et al. (US 20210050517) in view of Tada (US 10615339), Fu et al. (US 20210104666), and Chen et al. (US 20200106011), and further in view of Fest (US 9865813).
Regarding claim 20, Banno in view of Tada, Fu, and Chen teaches the limitations of claim 14. Banno in view of Tada, Fu, and Chen does not explicitly teach that a shape of each of the bottom electrodes is rectangular or dumbbell.
In a similar field of endeavor, Fest teaches that that a shape of each of the bottom electrodes (102A, Fig. 4F) is rectangular or dumbbell (col. 6, lines 40-50; rectangular), in order to have “lower erase current, narrower distribution of low-resistance state (LRS), higher on/off ratio (HRS/LRS), and improved failure rates” (col. 8, lines 55-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the bottom electrodes of Banno in view of Tada, Fu, and Chen with the bottom electrode shape of Fest, in order to have lower erase current, narrower distribution of low-resistance state (LRS), higher on/off ratio (HRS/LRS), and improved failure rates.
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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