DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 21 November 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 5-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (U.S. Pub. 2022/0302039) in view of Matsuura (U.S. Pub. 2003/0089988).
Claim 1: Li et al. discloses a semiconductor device, in Fig. 2E and in paragraphs 31, 33, 39, 41, 51 and 54, comprising:
a substrate (10); and
a wiring structure (126, 142 and 146) comprising:
at least one metal interconnect (126) disposed on the substrate (10);
at least one conductive feature (146) disposed on the metal interconnect (126) and having a head portion (upper portion of 146) and a neck portion (lower portion of 146), wherein the neck portion (lower portion of 146) is between the metal interconnect (126) and the head portion (upper portion of 146),
at least one diffusion barrier liner (142) to surround the conductive feature (146), and
an insulative layer (110) disposed on the substrate (10) to receive the metal interconnect (126) at a position that a top surface (top surface of 126) of the metal interconnect (126) is coplanar with a top surface (top surface of 110) of the insulative layer (110);
a block layer (132) disposed on the insulative layer (110) to cover the top surface (top surface of 126) of the metal interconnect (126) and the top surface (top surface of 110) of the insulative layer (110), wherein the block layer (132) has a hole (via cavity in 132) extended therethrough to expose a portion of the top surface (top surface of 126) of the metal interconnect (126) while the top surface (top surface of 110) of the insulative layer (110) is remained covered;
wherein a portion of the diffusion barrier liner (142) and the neck portion (lower portion of 146) of the conductive feature (146) is disposed within the hole (via cavity in 132) of the block layer (132), such that the portion of the diffusion barrier liner (142) is only in contact with the portion of the top surface (top surface of 126) of the metal interconnect (126) exposed through the hole (via cavity in 132) of the block layer (132)
wherein the neck portion (lower portion of 146) has a first critical dimension (width), which gradually decreases at positions of increasing distance from the head portion (upper portion of 146)
wherein the diffusion barrier liner (142) is formed on sidewalls of the hole (via cavity in 132) of the block layer (132), and the top surface (top surface of 126) of the metal interconnect (126) exposed through the hole of the block layer.
Li et al. appears not to explicitly disclose wherein the diffusion barrier liner is formed on a top surface of the block layer;
wherein the head portion of the conductive feature is positioned above the top surface of the block layer;
wherein the neck portion of the conductive feature is extended into the hole of the block layer at a position that a bottom surface of the neck portion of the conductive feature is positioned below the top surface of the block layer.
Matsuura, however, in Fig. 6 and in paragraphs 19, 45, 50 and 52, discloses the diffusion barrier liner (15) is formed on a top surface of the block layer (8, 9 and 10);
the head portion (upper portion of 16) of the conductive feature (16) is positioned above the top surface of the block layer (8, 9 and 10); and
the neck portion (lower portion of 16) of the conductive feature (16) is extended into the hole (13) of the block layer (8, 9 and 10) at a position that a bottom surface of the neck portion (lower portion of 16) of the conductive feature (16) is positioned below the top surface of the block layer (8, 9 and 10) in order to enhance reliability.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. with the disclosure of Matsuura to have made the diffusion barrier liner is formed on a top surface of the block layer;
the head portion of the conductive feature is positioned above the top surface of the block layer; and
the neck portion of the conductive feature is extended into the hole of the block layer at a position that a bottom surface of the neck portion of the conductive feature is positioned below the top surface of the block layer in order to enhance reliability (paragraph 19 of Matsuura).
Claim 2: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E, further discloses wherein an included angle (angle between upper surface of 126 and outer surface of 146) between the neck portion (lower portion of 146) and the metal interconnect (126) is less than 90 degrees.
Claim 5: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E, further discloses wherein the head portion (upper portion of 146) has a second critical dimension (width of upper portion of 146) greater than the first critical dimension (width of lower portion of 146).
Claim 6: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E and in paragraphs 31 and 39, further discloses comprising:
an isolation layer (134) surrounding the head portion (upper portion of 146) of the conductive feature (146), wherein the isolation layer (134) is disposed on the block layer (132), wherein the isolation layer (134) has a trench (line cavity and via cavity in 134) extended therethrough to communicate with the hole (via hole in 132) of the block layer (132), wherein the diffusion barrier liner (142) is further formed on sidewalls of the trench (line cavity and via cavity in 134) of the isolation layer (134).
Claims 7 and 8: Li et al. in view of Matsuura discloses the semiconductor device of claim 6.
Li et al. in view of Matsuura, as applied to claim 6, appears not to explicitly disclose wherein the block layer includes an underlying layer in contact with the metal interconnect and an overlying layer between the underlying layer and the isolation layer, wherein the diffusion barrier liner is formed on a top surface of the overlying layer, and
wherein the underlying layer has a first permittivity, and the overlying layer has a second permittivity greater than the first permittivity.
Matsuura, however, in Fig. 6 and in paragraphs 19, 44, 45 and 52, further discloses the block layer (8, 9 and 10) includes an underlying layer (8) in contact with the metal interconnect (7) and an overlying layer (10) between the underlying layer (8) and the isolation layer (11), wherein the diffusion barrier liner (15) is formed on a top surface of the overlying layer (10), and
wherein the underlying layer (8, which can be SiC, paragraph 46) has a first permittivity (SiC has a relative permittivity of 4.5 to 5.0, paragraph 12), and the overlying layer (10, which can be SiN , paragraph 48) has a second permittivity (SiN has a relative permittivity of 6.5 to 8.0, paragraph 12) greater than the first permittivity.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. in view of Matsuura, as applied to claim 6, with the further disclosure of Matsuura to have made the block layer includes an underlying layer in contact with the metal interconnect and an overlying layer between the underlying layer and the isolation layer, wherein the diffusion barrier liner is formed on a top surface of the overlying layer, and
wherein the underlying layer has a first permittivity, and the overlying layer has a second permittivity greater than the first permittivity in order to enhance reliability (paragraph 19 of Matsuura).
Claim 9: Li et al. in view of Matsuura discloses the semiconductor device of claim 6, and Li et al., in Fig. 2E, further discloses wherein the diffusion barrier liner (142) sandwiched between the conductive feature (146) and the metal interconnect (126), between the conductive feature (146) and the block layer (132), and between the conductive feature (146) and the isolation layer (134).
Claim 10: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E and in paragraph 33, further discloses comprising:
an adhesion liner (122B) interposed between the metal interconnect (126) and the substrate (10) and between the metal interconnect (126) and the insulative layer (110).
Claim 11: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E, further discloses wherein the head portion (upper portion of 146) and the neck portion (lower portion of 146) of the conductive feature (146) are integrally formed.
Claim 12: Li et al. in view of Matsuura discloses the semiconductor device of claim 1, and Li et al., in paragraphs 33, 52 and 55, further discloses wherein the metal interconnect (126) and the conductive feature (146) have identical conductive materials.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. in view of Matsuura as applied to claim 2 above, and further in view of Lin et al. (U.S. Pub. 2015/0318243).
Claim 3: Li et al. in view of Matsuura discloses the semiconductor device of claim 2.
Li et al. in view of Matsuura appears not to explicitly disclose wherein the diffusion barrier liner has a first thickness, and smaller values of the included angle correspond to greater values of the first thickness of the diffusion barrier liner.
Lin et al., however, in paragraph 16, discloses the thickness of the diffusion barrier and the included angle are result-affecting parameters because the thickness of the diffusion barrier liner (106) and the included angle (sidewall angle of 120) of the conductive feature (120) affects the electrical characteristics of the metal interconnect (104).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the thickness of the diffusion barrier and the included angle of Li et al. in view of Matsuura in order to have the desire electrical characteristics of the metal interconnect according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Li et al. in view of Matsuura in view of Lin et al. appears not to explicitly disclose wherein the first thickness of the diffusion barrier liner is less than a thickness of the block layer.
Matsuura, however, in Fig. 6 and in paragraphs 45 and 52, discloses the first thickness of the diffusion barrier liner (15) is less than a thickness of the block layer (8, 9 and 10).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. in view of Matsuura in view of Lin et al. with the disclosure of Matsuura to have made the first thickness of the diffusion barrier liner is less than a thickness of the block layer in order to adequately protect the surrounding elements.
Claim 4: Li et al. in view of Matsuura in view of Lin et al. discloses the semiconductor device of claim 3, and Li et al., in paragraph 39, further discloses the neck portion (lower portion of 146) can have a second thickness (h_v) of 1 nm to 150 nm and the head portion (upper portion of 146) can have a third thickness (h_i) of 2 nm to 150 nm. Therefore, Li et al. in view of Lin et al. discloses the semiconductor device of claim 3, and Li et al. would further disclose wherein the neck portion (lower portion of 146) has a second thickness (h_v), and the head portion (upper portion of 146) has a third thickness (h_i), greater than the second thickness (h_v) (for example, when the second thickness is 1 nm and the third thickness is 2 nm).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815