DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 24 April 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02 July 2026 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7, in the last two lines, recites “wherein the overlying layer is in contact between the diffusion barrier liner and the underlying layer.” It is indefinite as to what the overlying layer is in contact with or what the overlying layer is between. For compact prosecution, it will be interpreted as “wherein the overlying layer is in contact and between the diffusion barrier liner and the underlying layer.”
Claim 8 depends from claim 7, and is therefore also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7, 9, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. Pub. 2018/0350913) in view of Shih et al. (U.S. Pub. 2021/0125947).
Claim 1: Yang et al. discloses a semiconductor device, in Figs. 2B and 4, comprising:
a substrate (102; paragraph 43); and
a wiring structure (103 and 402; paragraphs 43, 48-51 and 54) comprising:
at least one metal interconnect (103; paragraph 43) disposed on the substrate (102);
at least one conductive feature (402; paragraph 54) disposed on the metal interconnect (103) and having a head portion (upper portion of 402) and a neck portion (lower portion of 402), wherein the neck portion (lower portion of 402) is between the metal interconnect (103) and the head portion (upper portion of 402), wherein the head portion (upper portion of 402) and the neck portion (lower portion of 402) of the conductive feature (402) are integrally formed;
at least one diffusion barrier liner (306; paragraphs 48-51 and 54) to surround the conductive feature (402), and
an insulative layer (105; paragraph 30) disposed on the substrate (102) to receive the metal interconnect (103) at a position that a top surface (top surface of 103) of the metal interconnect (103) is coplanar with a top surface (top surface of 105) of the insulative layer (105);
a block layer (104, 106 and 108; paragraph 43) disposed on the insulative layer (105) to cover the top surface (top surface of 103) of the metal interconnect (103) and the top surface (top surface of 105) of the insulative layer (105), wherein the block layer (104, 106 and 108) has a hole (113) extended therethrough to expose a portion of the top surface (top surface of 103) of the metal interconnect (103) while the top surface (top surface of 105) of the insulative layer (105) is remained covered; and
an isolation layer (110; paragraph 43) disposed on the block layer (104, 106 and 108);
wherein a portion of the diffusion barrier liner (306) and the neck portion (lower portion of 402) of the conductive feature (402) is disposed within the hole (113) of the block layer (104, 106 and 108), such that the portion of the diffusion barrier liner (306) is only in contact with the portion of the top surface (top surface of 126) of the metal interconnect (103) exposed through the hole (113) of the block layer (104, 106 and 108);
wherein the diffusion barrier liner (306) is formed on a top surface (top surface of 106) of the block layer (104, 106 and 108), sidewalls of the hole (113) of the block layer (104, 106 and 108), and the top surface (top surface of 103) of the metal interconnect (103) exposed through the hole of the block layer;
wherein the head portion (upper portion of 402) of the conductive feature (402) is positioned above the top surface (top surface of 106) of the block layer (104, 106 and 108);
wherein the neck portion (lower portion of 402) of the conductive feature (405) is extended into the hole (113) of the block layer (104, 106 and 108) at a position that a bottom surface (bottom surface of 402 in 113) of the neck portion (lower portion of 402) of the conductive feature (402) is positioned below the top surface (top surface of 106) of the block layer (104, 106 and 108);
wherein the head portion (upper portion of 402) of the conductive feature (402) and a top section (top section of lower portion of 402) of the neck portion (lower portion of 402) of the conductive feature (402) are surrounded by the isolation layer (110) while a bottom section (bottom section of lower portion of 402) of the neck portion (lower portion of 402) of the conductive feature (402) is surrounded by the block layer (104, 106 and 108);
wherein a thickness (DT can be 2000 angstroms; paragraph 40) of the isolation layer (110) is greater than a thickness (DV can be 50 angstroms; paragraph 41) of the block layer (104, 106 and 108);
wherein a thickness (DT can be 2000 angstroms; paragraph 40) of the head portion (upper portion of 402) of the conductive feature (402) is greater than a thickness (DV can be 50 angstroms; paragraph 41) of the neck portion (lower portion of 402) of the conductive feature (402);
wherein the neck portion (lower portion of 402) has a first critical dimension (WV).
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Yang et al. appears not to explicitly disclose the first critical dimension gradually decreases at positions of increasing distance from the head portion.
Shih et al., however, in Fig. 1 and in paragraphs 31 and 44, discloses wherein the neck portion (132) has a first critical dimension (W1), which gradually decreases at positions of increasing distance from the head portion (134) in order to create a void-free layer.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yang et al. with the disclosure of Shih et al. to have made the first critical dimension gradually decreases at positions of increasing distance from the head portion in order to create a void-free layer (paragraph 44 of Shih et al.).
Claim 2: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1.
Yang et al. in view of Shih et al., as applied to claim 1, appears not to explicitly disclose wherein an included angle between the neck portion and the metal interconnect is less than 90 degrees.
Shih et al., however, in Fig. 1 and in paragraphs 31 and 44, further discloses an included angle (angle between outer surface of 132 and upper surface of M3) between the neck portion (132) and the metal interconnect (M3) is less than 90 degrees in order to create a void-free layer.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yang et al. in view of Shih et al., as applied to claim 1, with the further disclosure of Shih et al. to have made an included angle between the neck portion and the metal interconnect is less than 90 degrees in order to create a void-free layer (paragraph 44 of Shih et al.).
Claim 5: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1, and Yang et al., in Figs. 2B and 4 and in paragraph 45, further discloses wherein the head portion (upper portion of 402) has a second critical dimension (WT) greater than the first critical dimension (WV).
Claim 6: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1, and Yang et al., in Fig. 2E and in paragraph 45, wherein the isolation layer (110) has a trench (111) extended therethrough to communicate with the hole (113) of the block layer (104, 106 and 108), wherein the diffusion barrier liner (306) is further formed on sidewalls of the trench (111) of the isolation layer (110).
Claim 7: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 6, and Yang et al., in Figs. 2B and 4, further discloses disclose wherein the block layer (104, 106 and 108) includes an underlying layer (104) in contact with the metal interconnect (103) and an overlying layer (106 and 108) between the underlying layer (104) and the isolation layer (110), wherein the diffusion barrier liner (306) is formed on a top surface of the overlying layer (104), wherein the overlying layer (106 and 108) is in contact and between the diffusion barrier liner (306) and the underlying layer (104).
Claim 9: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 6, and Yang et al., in Figs. 2B and 4, further discloses wherein the diffusion barrier liner (306) sandwiched between the conductive feature (402) and the metal interconnect (103), between the conductive feature (402) and the block layer (104, 106 and 108), and between the conductive feature (402) and the isolation layer (110).
Claim 11: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1, and Yang et al., in Figs. 2B and 4, further discloses wherein the thickness of the isolation layer (110) is equal to a sum of a thickness of the diffusion barrier liner (306) and the thickness of the head portion (upper portion of 402) of the conductive feature (402), wherein the thickness of the block layer (104, 106 and 108) is equal to the thickness of the neck portion (lower portion of 402) of the conductive feature (402).
Claim 12: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1, and Yang et al., in paragraphs 33, 52 and 55, further discloses wherein the metal interconnect (103; can be Ag, paragraph 30) and the conductive feature (402; can be Ag, paragraph 54) have identical conductive materials.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Shih et al. as applied to claim 2 above, and further in view of Lin et al. (U.S. Pub. 2015/0318243).
Claim 3: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 2, and Yang et al., in Figs. 2B and 4, further discloses the diffusion barrier liner (306) has a first thickness (paragraph 52), wherein the first thickness of the diffusion barrier liner (306) is less than the thickness of the block layer (110; paragraph 35).
Yang et al. in view of Shih et al. appears not to explicitly disclose smaller values of the included angle correspond to greater values of the first thickness of the diffusion barrier liner.
Lin et al., however, in paragraph 16, discloses the thickness of the diffusion barrier liner (106) and the included angle are result-affecting parameters because the thickness of the diffusion barrier liner (106) and the included angle (sidewall angle of 120) of the conductive feature (120) affects the electrical characteristics of the metal interconnect (104).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the thickness of the diffusion barrier and the included angle of Yang et al. in view of Shih et al. in order to have the desire electrical characteristics of the metal interconnect according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Claim 4: Yang et al. in view of Shih et al. in view of Lin et al. discloses the semiconductor device of claim 3, and Yang et al., in Fig. 4, further discloses the neck portion (lower portion of 402) has a second thickness (DV can be 50 angstroms; paragraph 41), the head portion (upper portion of 402) has a third thickness (DT can be 2000 angstroms; paragraph 40), greater than the second thickness, wherein the hole (113) of the block layer (104, 106 and 108) has a width (WV; paragraph 45) to receive the neck portion (lower portion of 402) of the conductive feature (402) while the head portion (upper portion of 402) of the conductive feature (402) is positioned out of the hole (113) of the block layer (104, 106 and 108).
Yang et al. in view of Shih et al. in view of Lin et al., as applied to claim 3, appears not to explicitly disclose the width gradually reduced from the top surface of the block layer to the top surface of the metal interconnect.
Shih et al., however, in Fig. 6 and in paragraphs 31 and 44, further discloses the hole (210) of the block layer (151) has a width gradually reduced from the top surface of the block layer (151) to the top surface of the metal interconnect (M3) in order to create a void-free layer.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yang et al. in view of Shih et al. in view of Lin et al., as applied to claim 3, with the further disclosure of Shih et al. to have made the width gradually reduced from the top surface of the block layer to the top surface of the metal interconnect in order to create a void-free layer (paragraph 44 of Shih et al.).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Shih et al. as applied to claim 6 above, and evidenced by Kiyotoshi (U.S. Pub. 2004/0169255).
Claim 8: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 6 and Yang et al. further discloses wherein the underlying layer (104, which can be SiON; paragraph 31) has a first permittivity (SiON has permittivity of 5.2, as evidenced by Kiyotoshi in paragraph 120), and the overlying layer (106 and 108, which can be SiN; paragraphs 33 and 34) has a second permittivity (SiN has permittivity of 7.5, as evidenced by Kiyotoshi in TABLE 1) greater than the first permittivity.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Shih et al. as applied to claim 1 above, and further in view of Agarwala et al. (U.S. Pub. 2002/0182855).
Claim 10: Yang et al. in view of Shih et al. discloses the semiconductor device of claim 1,
Yang et al. in view of Shih et al. appears not to explicitly disclose an adhesion liner interposed between the metal interconnect and the substrate and between the metal interconnect and the insulative layer.
Agarwala et al., in Fig. 2A and in paragraphs 4 and 6, discloses an adhesion liner (115) interposed between the metal interconnect (120) and the substrate (150) and between the metal interconnect (120) and the insulative layer (145).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yang et al. in view of Shih et al. with the disclosure of Agarwala et al. to have made an adhesion liner interposed between the metal interconnect and the substrate and between the metal interconnect and the insulative layer in order to provide better adhesion between the metal interconnect and the surrounding elements to increase reliability of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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