DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s response filed 01/16/2026 has been fully considered.
Applicant’s amendments to claim 5 overcomes the rejection under 35 U.S.C. 112, however the similar subject matter new present in amended claim 1 remain rejected, see below.
Applicant’s amendments and the accompanying arguments with respect to the dielectric layer having an even thickness equal to a distance between the first metallic layer and the second metallic layer in claims 1 and 7 and the rejections under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Barth et al. (US 7,812,424).
Claim Objections
Claim 1 is objected to because of the following informalities: the word ‘first’ should be added before the word ‘metallic’ in line 16. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim11-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to
In reference to claim 11, the claim requires “the first conductive block and the second conductive block are made of material different from the first conductive feature and the second conductive feature,” in lines 14-15. This is not disclosed. Applicant cited paragraphs 61 and 68 of the specification as supporting this limitation. However, paragraph 61 lists materials for the first metallic layer (180), and not the conductive blocks (160).
Paragraph 55 lists materials for the conductive blocks (160) as “copper, copper alloy, aluminum, aluminum alloy or a combination thereof.”
Paragraph 68 lists materials for the conductive features (220) as including “copper, aluminum, or the like.”
While those paragraphs list possible materials for the conductive blocks and conductive features, they, nor any other portion of the disclosure, specify that the materials are different from one another. In addition, the substantial overlap of materials in common in these lists along with materials for the conductive features including “or the like,” it is not at all clear that the inventor or a joint inventor, had possession of the claimed invention at the time the application was filed, with regard to this limitation.
Claims 12-15 depend on claim 11 and are unsupported due to their dependence on unsupported claim 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In reference to claim 1, the claim requires “ the first metallic layer and the second metallic layer are made of conductive and high-heat resistant material” in lines 3-4. The bounds of “high-heat resistant material” are not clear. Although the specification lists materials of tungsten, copper, aluminum, gold, titanium or a combination thereof as being high-heat resistant materials, this list is not disclosed as being a complete list of materials (that are high-heat resistant) and no definition of a high-heat resistant material is disclosed such that one could determine which, if any, other materials are high-heat resistant.
For purposes of examination, conductive materials such as tungsten, copper, aluminum, gold, titanium or a combination thereof have been interpreted to read on this limitation.
Claims 2-6 depend on claim 1 and are indefinite due to their dependence on indefinite claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii (US 2009/0102059) in view Allen et al. (US 9,070,751) and Barth et al. (US 7,812,424).
In reference to claim 1, Ishii (US 2009/0102059), hereafter “Ishii,” discloses a semiconductor device, with reference to Figure 2, including a wiring structure, comprising:
a first metallic layer 5M3;
a second metallic layer 5M4 above the first metallic layer, wherein the first metallic layer and the second metallic layer are made of conductive and high-heat resistant material, (aluminum) paragraphs 84 and 85;
at least one first conductive feature 9, having a first critical dimension x above the first metallic layer;
at least one second conductive feature 7, having a second critical dimension y less than the first critical dimension above the first metallic layer, paragraph 105, wherein the first conductive feature has less conductive resistance than the second conductive features, (an inherent result of the second conductive feature having a smaller cross-sectional area and resistance being inversely proportional to cross-sectional area. Ishii discloses the first and second conductive features are of the same material and have equal thickness, but have different cross-sectional areas by the second conductive feature having a width less than the first conductive feature);
a dielectric layer 6 formed between the first metallic layer and the second metallic layer, wherein the first conductive feature is surrounded by the dielectric layer, and the second conductive feature is surrounded by the dielectric, paragraph 110,
wherein the first conductive feature and the second conductive feature are positioned adjacent to each other and are formed between the first metallic layer and the second metallic layer.
Ishii does not disclose at least one isolation liner surrounding the second conductive feature,
wherein the isolation liner has a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer;
wherein the isolation liner is surrounded by the dielectric layer;
wherein the dielectric layer has an even thickness equal to a distance between the [first] metallic layer and the second metallic layer;
wherein the second conductive feature is enclosed by the first metallic layer, the second metallic layer, and the isolation liner.
Allen et al. (US 9,070,751), hereafter “Allen,” discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, and at least one isolation liner 121 surrounding the second conductive feature, col. 2 line 60 to col. 3 line 35.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least one isolation liner to surround the second conductive feature. One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
In reference to the isolation liner having a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer, Ishii discloses the second conductive feature having a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer, as addressed above, and Allen teaches the second conductive feature includes the isolation liner having the same height 131 as the second conductive feature, col. 5, lines 28-30 and 33-37. It results naturally from the combination of Ishii and Allen to surround the second conductive feature with the isolation liner that the isolation liner has a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer.
In reference to the isolation liner being surrounded by the dielectric layer; Ishii teaches the dielectric layer surrounding the first conductive feature and the second conductive feature and Allen teaches the second conductive feature includes the isolation liner, as addressed above. It results naturally form the combination of Ishii and Allen to surround the second conductive feature with the isolation liner that the isolation liner is surrounded by the dielectric layer.
In reference to the second conductive feature being enclosed by the first metallic layer, the second metallic layer, and the isolation liner, Ishii discloses the second conductive feature where the top and bottom are enclosed by the first metallic layer and the second metallic layer and Allen teaches the sides of the second conductive feature being enclosed by the isolation liner. It results naturally from the combination of Ishii and Allen to surround the second conductive feature with the isolation liner that the second conductive feature is enclosed by the first metallic layer, the second metallic layer, and the isolation liner.
Ishii in view of Allen does not disclose wherein the dielectric layer has an even thickness equal to a distance between the [first] metallic layer and the second metallic layer.
Barth et al. (US 7,812,424), hereafter “Barth,” discloses a semiconductor device including teaching a dielectric layer, 41 in Figure 7g, formed between the first metallic layer, M3, and the second metallic layer, M4, for example, wherein the dielectric layer has an even thickness equal to a distance between the [first] metallic layer and the second metallic layer; col. 9 lines 1-18. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric layer to have an even thickness equal to a distance between the [first] metallic layer and the second metallic layer. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the dielectric of Barth for that of Ishii to replace the metal-first buildup of Ishii (exemplified by Figs 8-13) for the dielectric-first buildup of Barth (exemplified by Figs. 7a-d).
In reference to claim 2, Allen discloses a sum of the second critical dimension 133 and two times a thickness of the isolation liner 121 is equal to the first critical dimension 132, and a height of the first conductive feature is equal to a height of the second conductive feature and is equal to a height of the isolation liner, Figure 1 and col. 5 lines 7-12 and 30-33, and
Ishii discloses a height of the first conductive feature is equal to a height of the second conductive feature, Figure 2.
In reference to claim 3, the combination of Ishii and Allen teaches the dielectric layer has a first trench and a second trench formed between the first metallic layer and the second metallic layer, Figures 1 and 12 of Ishii, wherein a width 132 of the first trench is equal to a width 132 of the second trench, wherein the first conductive feature 101A is formed in the first trench, wherein the second conductive feature 101B and the isolation liner 121 are formed in the second trench, Figure 1 of Allen.
In reference to claim 4, Ishii discloses the first conductive feature is in contact between the first metallic layer and the second metallic layer and the second conductive feature is in contact between the first metallic layer and the second metallic layer, Figure 2 and paragraphs 87, 89, and 90.
In reference to claim 5, Ishii discloses the first metallic layer and the second metallic layer are made of a same conductive material (aluminum) paragraph 85.
Ishii does not disclose the first metallic layer and the second metallic layer are made of a material which is selected from a group consisting of tungsten, copper, and gold.
Barth teaches the first metallic layer and the second metallic layer are made of a material which is selected from a group consisting of tungsten, copper, and gold, col. 6 lines 8-17. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first metallic layer and the second metallic layer to be made of a material which is selected from a group consisting of tungsten, copper, and gold. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one conductor for another as suggested by Barth, id.
In reference to claim 6, Ishii discloses the second conductive feature 7 formed between the first metallic layer 5M3 and the second metallic layer 5M4 and Allen discloses the second conductive feature includes the isolation liner, as addressed above in reference to claim 1. It results naturally from the combination of Ishii and Allen that the isolation liner is then also formed between the first metallic layer and the second metallic layer.
In reference to claim 7, Ishii discloses a semiconductor device, with reference to Figure 2, comprising:
a substrate 1S;
a wiring structure, disposed over the substrate, comprising
a first metallic layer 5M3;
a second metallic layer 5M4 above the first metallic layer, paragraph 84;
at least one first conductive feature 9, between the first and second metallic layers and having a first critical dimension x above the first metallic layer;
at least one second conductive feature 7, between the first and second metallic layers and having a second critical dimension y less than the first critical dimension above the first metallic layer, paragraph 105;
an inter-layer dielectric (ILD) layer 6 enclosing the first conductive feature, paragraph 110,
an interconnection structure, 5, 7, and 13 below 5M3, between the substrate 1S and the wiring structure for connecting the wiring structure to the substrate;
wherein a distance between the first metallic layer and the second metallic layer is equal to a height of the first conductive feature and is equal to a height of the second conductive feature.
Ishii does not disclose at least one isolation liner surrounding the second conductive feature.
wherein the isolation liner has a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer;
wherein the second conductive feature is enclosed by the first metallic layer, the second metallic layer, and the isolation liner, or
wherein the ILD layer has an even thickness equal to the distance between the first metallic layer and the second metallic layer.
Allen discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, and at least one isolation liner 121 surrounding the second conductive feature, col. 2 line 60 to col. 3 line 35.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least one isolation liner surrounding the second conductive feature. One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
In reference to the isolation liner having a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer, Ishii discloses the second conductive feature having a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer, as addressed above, and Allen teaches the second conductive feature includes the isolation liner having the same height 131 as the second conductive feature, col. 5, lines 28-30 and 33-37. It results naturally from the combination of Ishii and Allen to surround the second conductive feature with the isolation liner that the isolation liner has a bottom end in contact with the first metallic layer and a top end in contact with the second metallic layer.
In reference to the isolation liner being enclosed by the ILD layer; Ishii teaches the ILD layer surrounding the first conductive feature and the second conductive feature and Allen teaches the second conductive feature includes the isolation liner, as addressed above. It results naturally form the combination of Ishii and Allen to surround the second conductive feature with the isolation liner such that the isolation liner is enclosed by the ILD layer.
In reference to the second conductive feature being enclosed by the first metallic layer, the second metallic layer, and the isolation liner, Ishii discloses the second conductive feature where the top and bottom are enclosed by the first metallic layer and the second metallic layer and Allen teaches the sides of the second conductive feature being enclosed by the isolation liner. It results naturally from the combination of Ishii and Allen to surround the second conductive feature with the isolation liner that the second conductive feature is enclosed by the first metallic layer, the second metallic layer, and the isolation liner.
Ishii in view of Allen does not disclose wherein the ILD layer has an even thickness equal to the distance between the first metallic layer and the second metallic layer.
Barth discloses a semiconductor device including teaching an ILD layer, 41 in Figure 7g, with an even thickness equal to the distance between the first metallic layer, M3 and the second metallic layer, M4, for example; col. 9 lines 1-18. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the ILD layer to have an even thickness equal to the distance between the first metallic layer and the second metallic layer.
To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the dielectric of Barth for that of Ishii to replace the metal-first buildup of Ishii (exemplified by Figs 8-13) for the dielectric-first buildup of Barth (exemplified by Figs. 7a-d).
In reference to claim 8, Allen discloses a sum of the second critical dimension 133 and two times a thickness of the isolation liner 121 is equal to the first critical dimension 132, and col. 5 lines 7-12 and 30-33.
In reference to claim 9, the combination of Ishii and Allen teaches the ILD layer has a first trench and a second trench formed between the first metallic layer and the second metallic layer, Figures 1 and 12 of Ishii, wherein a width 132 of the first trench is equal to a width 132 of the second trench, wherein the first conductive feature 101A is formed in the first trench, wherein the second conductive feature 101B and the isolation liner 121 are formed in the second trench, Figure 1 of Allen.
In reference to claim 10, Ishii discloses a bottom surface and a top surface of the first conductive feature contact the first and second metallic layers, respectively, wherein a bottom surface and a top surface of the second conductive feature contact the first and second metallic layers respectively, Figure 2 and paragraphs 87, 89, and 90.
In reference to claim 16, Ishii discloses the wiring structure is formed over the substrate during back-end-of-line processes, paragraphs 85 and 93.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii (US 2009/0102059) in view Allen et al. (US 9,070,751) and Barth et al. (US 7,812,424) as applied to claim 7 above and further in view of Anderson et al. (US 2006/0189137) and Hsiao et al. (US 2023/0260790).
In reference to claim 11, Ishii discloses the interconnection structure comprises an insulating layer, 6 in Figure 35, disposed on the substrate;
at least one first conductive block 13 penetrating the insulating layer and
at least one second conductive block 13 penetrating through the insulating layer,
wherein the first metallic layer is in contact with the first conductive block and the second conductive block and is in contact with the first conductive feature and the second conductive feature (electrically),
wherein the first metallic layer is positioned between the first conductive block and the first conductive feature and is positioned between the second conductive block and the second conductive feature.
Ishii does not disclose a block layer disposed between the insulating layer and the substrate, wherein a thickness of the block layer is less than a thickness of the insulating layer;
at least one first conductive block penetrating the insulating layer and the block layer and having a third critical dimension and
at least one second conductive block penetrating through the insulating layer and the block layer and having a fourth critical dimension less than the third critical dimension,
wherein the first conductive block and the second conductive block penetrate through the insulating layer to contact the substrate,
wherein the first conductive block and the second conductive block are made of material different from the first conductive feature and the second conductive feature.
Anderson et al. (US 2006/0189137), hereafter “Anderson,” discloses an interconnection structure comprises an insulating layer, 14 in Figure 6, disposed on the substrate 12, paragraphs 42 and 43;
at least one first conductive block 32b penetrating the insulating layer and having a third critical dimension and
at least one second conductive block 32a penetrating through the insulating layer and having a fourth critical dimension less than the third critical dimension, paragraphs 45 and 50,
wherein the first conductive block and the second conductive block penetrate through the insulating layer to contact the substrate, Figure 6.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the interconnection structure to comprise an insulating layer disposed on the substrate;
at least one first conductive block penetrating the insulating layer and having a third critical dimension and
at least one second conductive block penetrating through the insulating layer and having a fourth critical dimension less than the third critical dimension,
wherein the first conductive block and the second conductive block penetrate through the insulating layer to contact the substrate.
One would have been motivated to do so in order to form substrate wiring with different widths on the same substrate, paragraph 45 and 53.
Hsiao et al. (US 2023/0260790), hereafter “Hsiao,” discloses a semiconductor device including teaching a block layer, 502 in Figure 5B, disposed between the insulating layer 504 and the substrate 204, wherein a thickness of the block layer is less than a thickness of the insulating layer, paragraphs 51 and 52;
at least one first conductive block, 606 in Figure 6C, penetrating the insulating layer and the block layer and having a third critical dimension and
at least one second conductive block 606 penetrating through the insulating layer and the block layer, paragraphs 85 and 88.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a block layer to be disposed between the insulating layer and the substrate, wherein a thickness of the block layer is less than a thickness of the insulating layer;
the at least one first conductive block penetrating the insulating layer and the block layer and
the at least one second conductive block penetrating through the insulating layer and the block layer.
One would have been motivated to do so in order to provide an etch stop layer for forming openings for the conductive blocks, paragraph 51.
Hsiao further teaches wherein the first conductive block and the second conductive block, 606 in Figure 6H, are made of material different from a first conductive feature and a second conductive feature, 618, paragraph 95. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first conductive block and the second conductive block to be made of material different from the first conductive feature and the second conductive feature. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting conductive materials, as suggested by Hsiao, id.
In reference to claim 12, Anderson discloses at least one insulative liner 24 interposed between the insulating layer 14 and the at least one second conductive block 32a wherein at least one second conductive block is enclosed by the at least one insulative liner, the substrate 12 and the first metallic layer 45a, wherein the insulative liner is in contact with the first metallic layer, Figure 16, paragraphs 47, 48, and 54.
In reference to the insulative liner being in contact with the block layer, Anderson teaches the insulative liner along the full height of the second conductive block, and Hsiao teaches the conductive block extending through the insulating layer and the block layer, as addressed above. It results naturally from the combination of that the insulative liner is in contact with the block layer.
In reference to claim 13, Ishii in view of Anderson does not disclose a sum of the fourth critical dimension and two times a thickness of the insulative liner is equal to the third critical dimension.
Allen discloses a semiconductor device including teaching a first conductive block 101A in Figure 1, in insulating layer 100 and having a first critical dimension 132, a second conductive block 101B, in insulating layer 100 having a second critical dimension 133 less than the first critical dimension, and at least one insulative liner 121 interposed between the insulating layer and the second conductive block, col. 2 line 60 to col. 3 line 35,
wherein a sum of the fourth critical dimension 133 and two times a thickness of the insulative liner 121 is equal to the third critical dimension 132, and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a sum of the fourth critical dimension and two times a thickness of the insulative liner to be equal to the third critical dimension.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the technique for wiring of different widths of Allen to the substrate contacting wiring of different widths of Anderson.
In reference to claim 14, Ishii does not disclose the first conductive block and the second conductive block are made of a same material which is selected from a group consisting of tungsten, copper, and gold.
Anderson teaches the first conductive block and the second conductive block are made of a same material, 30 in Figure 5, which is selected from a group consisting of tungsten, copper, and gold, (copper) paragraph 49. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first conductive block and the second conductive block to be made of a same material which is selected from a group consisting of tungsten, copper, and gold. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one conductor for another.
In reference to claim 15, Anderson discloses the at least one first conductive block 32b and the at least one second conductive blocks 32a are surrounded by diffusion barrier liners 26, paragraph 49.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Frohberg et al. (US 2011/0291292), Nakashima (US 2007/0032067), Mikolajick (US 2003/0072195), Allen et al. (US 9,111,935), and Allen et al. (US 9,099,471) disclose related wiring structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897