DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 11/18/2025. Claims 1, 4, 8, and 21 have been amended. No new claims have been added. Claims 14-20 were canceled. Currently, claims 1-13 and 21-27 are pending.
Applicant’s amendment to claim 4 successfully overcomes the 112(b) rejection of claim 4 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed 11/18/2025 have been fully considered but they are not persuasive.
The Applicants argue, on pages 8-9:
Currently, the amended claim 1 or 21 recites at least the feature of "wherein the dielectric
fin lands on a top surface of the substrate." Applicant respectfully submits that the cited
reference Min, fails to disclose the foregoing feature.
….
Referring to FIG. 25 of Min, a bottom surface of the lower isolation pattern 160B (alleged as the claimed "dielectric fin") is vertically offset from a top surface of the substrate 100. In addition, referring to FIGS. 33-3 7 and column 26, line 21 - line 54 of Min, Min further teaches the lower isolation pattern 160B is formed within a lower isolation space SP by removing a portion of a first field insulating layer 105, while the first field insulating layer 105 formed over the substrate 100 is sandwiched between the later formed lower isolation pattern 160B and the substrate 100. Clearly shown in Min's FIGS. 25 and 37, the bottom surface of the lower isolation pattern 160B lands on and contacts the top surface surface of the first field insulating layer 105, and does not land on the top surface of the substrate 100.
The Examiner responds:
The Examiner respectfully disagrees. The Examiner agrees with the Applicant that in the interpretation of Min set forth in the previous Office Action’s rejection, the dielectric fin 160B does not land on a top surface of substrate 100. In light of the specification, the Examiner interprets “lands on a top surface” to require direct contact. But, as set forth in the rejection, Min does teach this new limitation if the “substrate” is the first field insulating layer 105 instead of substrate 100. This is because a “substrate” is a very broad term under the art. Thus, Min renders obvious the limitations of amended claims 1 and 21. As a result, the rejection of claims 1-7 and 21-27 is maintained.
The Applicants argue, on pages 10-11:
In particular, referring to FIG. 25 of Min, the bottom surface of the lower isolation pattern 160B is in contact with a surface of the first field insulating layer 105, and the first field insulating layer 105 is located between the bottom surface of the lower isolation pattern 160B and the top surface of the substrate 100. That is, Min fails to explicitly disclose or teach the bottom surface of the lower isolation pattern 160B is in contact with the top surface of the substrate 100. On the other hand, the other cited reference Ching cannot cure the deficiencies of Min.
The Examiner responds:
The Examiner respectfully disagrees. The Examiner agrees with the Applicant that in the interpretation of Min set forth in the previous Office Action’s rejection, the bottom surface of dielectric fin 160B is not in contact with the top surface of substrate 100. In light of the specification, the Examiner interprets “in contact with” to require direct contact. But, as set forth in the rejection, Min does teach this new limitation if the “substrate” is the first field insulating layer 105 instead of substrate 100. This is because a “substrate” is a very broad term under the art. Thus, Min renders obvious the limitations of amended claim 8. As a result, the rejection of claims 8-13 is maintained.
Claim Objections
Claim 8 is objected to because of the following informalities: in line 5, it appears that “in contact with on” should be either “in contact with” or “in contact with and on”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-7, 21-22, and 24-26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Min et al. (US 12170281).
Regarding claim 1, Min teaches, in Fig. 25, a FinFET device (col. 4, lines 10-20), comprising:
a substrate (105; col. 7, lines 20-35);
a first fin (AP1) and a second fin (AP2) on the substrate (col. 22, lines 20-30; see Fig. 25);
a dielectric fin (160B; col. 13, lines 60-67; see Fig. 1 for 160) between the first fin (AP1) and the second fin (AP2), wherein the dielectric fin (160B) lands on a top surface of the substrate (105) (see Fig. 25);
a metal gate line (120; col. 4, lines 30-40) across the first fin (AP1), the dielectric fin (160B) and the second fin (AP2) (see Fig. 25);
a gate dielectric layer (130 and 230; col. 9, lines 15-20; col. 17, lines 20-25) located between the metal gate line (120) and the dielectric fin (160B), between the metal gate line (120) and the first fin (AP1), and between the metal gate line (120) and the second fin (AP2) (see Fig. 25); and
a gate isolation structure (160U; col. 13, lines 60-67) extending through the metal gate line (120) and the gate dielectric layer (130/230), and landing on the dielectric fin (160B) (see Fig. 25),
wherein a top surface of the gate dielectric layer (130/230) is lower than a top surface of the gate isolation structure (160U) (see Fig. 25).
Regarding claim 2, Min further teaches that a width of the gate isolation structure (160U) is equal to or smaller than a width of the dielectric fin (160B) (see Fig. 25 how the widths are equal where they connect).
Regarding claim 5, Min further teaches, in Fig. 25, that the gate dielectric layer (130/230) located on the dielectric fin (160B) is sandwiched longitudinally between the metal gate line (120) and the dielectric fin (160B) (see Fig. 25).
Regarding claim 6, Min further teaches, in Fig. 25, that a topmost surface of the gate dielectric layer (130/230) located over the dielectric fin (160B) is lower than a topmost surface of the metal gate line (120) located over the dielectric fin (160B) (see Fig. 25).
Regarding claim 7, Min further teaches, in Fig. 25, that the gate dielectric layer (130/230) is in contact with lower sidewalls of the gate isolation structure (160U) (see Fig. 25).
Regarding claim 21, Min teaches, in Fig. 25, a structure (col. 4, lines 10-20), comprising:
a substrate (105; col. 7, lines 20-35);
a first fin (AP1) and a second fin (AP2) over the substrate (105) (col. 22, lines 20-30; top portions of AP1 and AP2 are above 105, and thus are over 105);
a dielectric fin (160B; col. 13, lines 60-67; see Fig. 1 for 160) disposed between the first fin (AP1) and the second fin (AP2) and over the substrate (105), wherein the dielectric fin (160B) lands on a top surface of the substrate (105) (see Fig. 25);
a gate dielectric layer (130 and 230; col. 9, lines 15-20; col. 17, lines 20-25) disposed over the first fin (AP1), the dielectric fin (160B) and the second fin (AP2);
a metal gate line (120; col. 4, lines 30-40) disposed over the gate dielectric layer (130/230);
a gate isolation structure (160U; col. 13, lines 60-67) extending into the metal gate line (120) and disposed on the dielectric fin (160B) (see Fig. 25),
wherein an interface between the dielectric fin (160B) and the gate isolation structure (160U) is lower than a topmost surface of the gate dielectric layer (130/230) (see Fig. 25).
Regarding claim 22, Min further teaches, in Fig. 25, that the gate dielectric layer (130/230) extends along sidewalls of the dielectric fin (160B), and the dielectric fin (160B) is spaced laterally apart from the metal gate line (120) by the gate dielectric layer (130/230) (see Fig. 25).
Regarding claim 24, Min further teaches, in Fig. 25, that the topmost surface of the gate dielectric layer (130/230) is lower than a top surface of the gate isolation structure (160U) (see Fig. 25).
Regarding claim 25, Min further teaches, in Fig. 25, that a first height (greatest height) of the gate dielectric layer (130/230) extending from a bottom (most bottom) surface of the metal gate line (120), is greater than a second height (greatest height) of the dielectric fin (160B) extending from the bottom surface of the metal gate line (120) (see Fig. 25).
Regarding claim 26, Min further teaches, in Fig. 25, that from a top view, the gate isolation structure (160U) is confined to an overlapping region of the dielectric fin (160B) and the metal gate line (120) (see Fig. 25, where an overlapping region is located at the leftmost portion of dielectric fin 160B that is outside the orthographic projection of 160U onto 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 12170281) in view of Choi et al. (US 12324238).
Regarding claim 3, Min teaches the limitations of claim 2. Min, in Fig. 25, does not explicitly teach that a width of the dielectric fin is equal to or greater than a width of the first fin and a width of the second fin.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a width of the dielectric fin (SEP1; col. 19, lines 1-15) is equal to or greater than a width of the first fin (first CH1 to the left of SEP1; col. 5, lines 1-10) and a width of the second fin (first CH1 to the right of SEP1) (see Fig. 17), in order to “provide a semiconductor device with improved electric characteristics” (col. 1, lines 30-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Min with the widths of Choi, in order to provide a semiconductor device with improved electric characteristics.
Regarding claim 4, Min teaches the limitations of claim 1. Min does not explicitly teach that a top surface of the dielectric fin is covered by the gate dielectric layer.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a top surface of the dielectric fin (SEP1; col. 19, lines 1-15) is covered by the gate dielectric layer (GI; col. 9, lines 50-55), in order to “provide a semiconductor device with improved electric characteristics” (col. 1, lines 30-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Min with the dielectric fin configuration of Choi, in order to provide a semiconductor device with improved electric characteristics.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 12170281) in view of Ching et al. (US 20200058649).
Regarding claim 8, Min teaches, in Fig. 25, a FinFET device (col. 4, lines 10-20), comprising:
a substrate (105; col. 7, lines 20-35);
a first fin (AP1) and a second fin (AP2) on the substrate (105) (col. 22, lines 20-30; see Fig. 25);
a dielectric fin (160B; col. 13, lines 60-67; see Fig. 1 for 160) between the first fin and the second fin, wherein a bottom surface of the dielectric fin (160B) is in contact with on a top surface of the substrate (105) (see Fig. 25);
a metal gate line (120; col. 4, lines 30-40) across the first fin (AP1), the dielectric fin (160B) and the second fin (AP2) (see Fig. 25);
a gate dielectric layer (130 and 230; col. 9, lines 15-20; col. 17, lines 20-25) located between the metal gate line (120) and the dielectric fin (160B), between the metal gate line (120) and the first fin (AP1), and between the metal gate line (120) and the second fin (AP2) (see Fig. 25); and
a gate isolation structure (160U; col. 13, lines 60-67) extending through the metal gate line (120) and the gate dielectric layer (130/230), and landing on the dielectric fin (160B) (see Fig. 250.
Min does not explicitly teach that the metal gate line is in contact with upper sidewalls of the gate isolation structure.
In a similar field of endeavor, Ching, in Fig. 15C, teaches that the metal gate line (234, [0050]-[0051], labelled in Fig. 15A) is in contact with upper sidewalls of the gate isolation structure (240, [0054]) (see Fig. 15C), in order to “enhance the device performance” ([0052])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Min with the metal gate line and gate isolation structure configuration of Ching, in order to enhance the device performance.
Regarding claim 9, Min in view of Ching teaches the limitations of claim 8. Min, in Fig. 25, further teaches that the gate dielectric layer (130/230) is in contact with lower sidewalls of the gate isolation structure (160U) (see Fig. 25).
Regarding claim 10, Min in view of Ching teaches the limitations of claim 9. Min, in Fig. 25, further teaches that a contact area between the metal gate line (120) and a sidewall of a first side of the gate isolation structure (160U) is greater than a contact area between the gate dielectric layer (130/230) and the sidewall of the first side of the isolation structure (160U) (see Fig. 25).
Regarding claim 11, Min in view of Ching teaches the limitations of claim 8. Ching, in Fig. 15C, further teaches that a width of the dielectric fin (145, [0022]) is greater than a width of the first fin (110 to the left of 145, [0022]), a width of the second fin (110 to the right), and a width of the gate isolation structure (240) (see Fig. 15C).
Regarding claim 12, Min in view of Ching teaches the limitations of claim 8. Ching, in Fig. 15C, further teaches that a width of the dielectric fin (145, [0022]) is greater than a width of the first fin (110 to the left of 145, [0022]) and a width of the second fin (110 to the right) (see Fig. 15C).
Min, in Fig. 25, teaches that a width of the dielectric fin is equal to a width of the gate isolation structure (see Fig. 25 how the widths are equal where they connect).
Regarding claim 13, Min in view of Ching teaches the limitations of claim 8. Min, in Fig. 25, teaches that a width of the dielectric fin is equal to a width of the gate isolation structure (see Fig. 25 how the widths are equal where they connect).
However, Min in view of Ching does not explicitly teach that a width of the dielectric fin is equal to a width of the first fin and a width of the second fin. Nonetheless, the skilled artisan would know too that the width of the dielectric fin affects leakage and the widths of the first fin and second fin would impact “current control capability” and “short channel effect” (Min; col. 1, lines 25-35).
The specific claimed widths, absent any criticality, is only considered to be the “optimum” widths disclosed by Min in view of Ching that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired leakage, current control capability, short channel effect, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a width of the dielectric fin being equal to a width of the first fin and a width of the second fin is used, as already suggested by Min in view of Ching.
Since the applicant has not established the criticality (see next paragraph) of the widths stated and since these widths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Min in view of Ching.
Please note that the specification contains no disclosure of either the critical nature of the claimed widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (US 12170281).
Regarding claim 23, Min teaches the limitations of claim 21. Min does not explicitly teach, in Fig. 25 separately, that the gate isolation structure comprises a first portion and a second portion connected with the first portion, the first portion disposed on the dielectric fin and surrounded by the gate dielectric layer, and the second portion is in direct contact with the metal gate line.
Min, in Fig. 10, teaches that the gate isolation structure comprises a first portion (160B_UR; col. 14, lines 60-65) and a second portion (160U) connected with the first portion (col. 13, line 65 – col. 14, line 5; col. 19, lines 10-15), the first portion (160B_UR) disposed on the dielectric fin (160B_BR) (col. 14, line 60 – col. 15, line 15) and surrounded by the gate dielectric layer (130/230) (see Fig. 10), and the second portion (160U) is in direct contact with the metal gate line (120) (see Fig. 10), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Fig. 25 with the gate isolation structure of Fig. 10, in order to improve performance and reliability of the semiconductor device.
Regarding claim 27, Min teaches the limitations of claim 21. Min does not explicitly teach, in Fig. 25 separately, that the gate isolation structure further extends into the dielectric fin, and a bottom surface of the gate isolation structure is lower than a bottom surface of the metal gate line.
Min teaches, in Fig. 13 separately, that the gate isolation structure (160U) further extends into the dielectric fin (160B), and a bottom surface of the gate isolation structure (160U) is lower than a bottom surface (the topmost surface of 130 contacting 120) of the metal gate line (120) (see Fig. 13), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Fig. 25 with the gate isolation structure and dielectric fin of Fig. 13, in order to improve performance and reliability of the semiconductor device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893