DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/23/26 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 4/23/26. Claims 1, 8, 21, and 26 have been amended. No new claims have been added or canceled. Currently, claims 1-13 and 21-27 are pending.
Applicant’s amendment to claim 8 successfully overcomes the objection of claim 8 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 recites the limitation “the isolation structure” in the last line of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, the term “the isolation structure” will be treated as “the gate isolation structure,” which does provide sufficient antecedent basis for this limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 7, 21-22, and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 20210125875).
Regarding claim 1, Tsai teaches, in Fig. 20B, a FinFET device ([0009]), comprising:
a substrate (20, [0015]);
an isolation region (22, [0019]) formed on the substrate (20);
a first fin (second from left 24, [0019]) and a second fin (second from right 24, [0019]) on the substrate (20);
a dielectric fin (25, [0021]) between the first fin (second from left 24) and the second fin (second from right 24), wherein the isolation layer (22) extends along a top surface of the substrate (20) and bottom sidewalls of the dielectric fin (25), and the dielectric fin (25) penetrates through the isolation layer (22) and lands on the top surface of the substrate (20) (see Fig. 20B);
a metal gate line (94, [0054]-[0055]) across the first fin (second from left 24), the dielectric fin (25) and the second fin (second from right 24);
a gate dielectric layer (92, [0054], labelled in Fig. 17B) located between the metal gate line (94) and the dielectric fin (25), between the metal gate line (94) and the first fin (second from left 24), and between the metal gate line (94) and the second fin; and
a gate isolation structure (60, [0050]) extending through the metal gate line (94) and the gate dielectric layer (92), and landing on the dielectric fin (25), and
wherein a top surface (see annotated Fig. 20B below) of the gate dielectric layer (92) is lower than a top surface of the gate isolation structure (60) (see Fig. 20B).
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Regarding claim 2, Tsai further teaches that a width of the gate isolation structure (60) is equal to or smaller than a width of the dielectric fin (25) ([0052]).
Regarding claim 5, Tsai further teaches that the gate dielectric layer (92) located on the dielectric fin (25) is sandwiched longitudinally between the metal gate line (94) and the dielectric fin (25) (see Fig. 20B).
Regarding claim 7, Tsai further teaches that the gate dielectric layer (92) is in contact with lower sidewalls of the gate isolation structure (60) (see Fig. 20B).
Regarding claim 21, Tsai teaches, in Fig. 20B, a structure ([0009]), comprising:
a substrate (20, [0015]);
a first fin (second from left 24, [0019]) and a second fin (second from right 24, [0019]) over the substrate;
a dielectric fin (25, [0021]) disposed between the first fin (second from left 24) and the second fin (second from right 24) and over the substrate (20), wherein the dielectric fin (25) lands on a top surface of the substrate (20);
an isolation region (22, [0019]) formed between the first fin (second from left 24), the second fin (second from right 24) and the dielectric fin (25);
a gate dielectric layer (92, [0054], labelled in Fig. 17B) disposed over the first fin (second from left 24), the dielectric fin (25) and the second fin (second from right 24), wherein the gate dielectric layer (92) is spaced apart from the substrate (20) by the isolation region (22);
a metal gate line (94, [0054]-[0055]) disposed over the gate dielectric layer (92); and
a gate isolation structure (60, [0050]), extending into the metal gate line (94) and disposed on the dielectric fin (25), wherein an interface between the dielectric fin (25) and the gate isolation structure (60) is lower than a topmost surface of the gate dielectric layer (92) (see annotated Fig. 20B below, interface with 62).
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Regarding claim 22, Tsai further teaches, in Fig. 20B, that the gate dielectric layer (92) extends along sidewalls of the dielectric fin (25), and the dielectric fin (25) is spaced laterally apart from the metal gate line (94) by the gate dielectric layer (92) (see Fig. 20B).
Regarding claim 25, Tsai further teaches, in Fig. 20B, that a first height (from bottom to top of 94) of the gate dielectric layer (92) extending from a bottom surface of the metal gate line (94), is greater than a second height of the dielectric fin (25) extending from the bottom surface of the metal gate line (94) (see Fig. 20B).
Regarding claim 26, Tsai further teaches that from a top view, the dielectric fin (25) extends in a first direction over the substrate (20) (see Fig. 5B, first direction is dielectric fin’s longitudinal axis), the metal gate line (94) extends in a second direction orthogonal to the first direction (see Fig. 6, [0023], [0054], 94 replaced dummy gate electrode 34) and intersecting the dielectric fin (25), an overlapping region is defined by an intersection of the dielectric fin (25) and the metal gate line (94), the gate isolation structure (60) is confined to the overlapping region of the dielectric fin (25) and the metal gate line (64) ([0052], if W5 and W6 are less than the width of 25), and a dimension of the gate isolation structure (60) in the first direction is smaller than an extending length of the dielectric fin (25) in the first direction (see Fig. 9, [0036], gate isolation opening 56 is shorter than extending length of 25 in the first direction).
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (US 20210083072).
Regarding claim 8, Feng teaches, in Fig. 18A, a FinFET device ([0005]), comprising:
a substrate (20, [0012]);
a first fin (second from left 24, [0012]) and a second fin (second from right 24, [0012]) on the substrate (20);
an isolation layer (22, [0012]) formed between the first fin (second from left 24) and the second fin (second from right 24);
a dielectric fin (25, [0014]) between the first fin (second from left 24) and the second fin (second from right 24), wherein a bottom surface of the dielectric fin (25) is in contact with a top surface of the substrate (20), and the isolation layer (22) extends along the top surface of the substrate (20) and bottom sidewalls of the dielectric fin (25);
a metal gate line (52, [0024]-[0025]) across the first fin (second from left 24), the dielectric fin (25) and the second fin (second from right 24);
a gate dielectric layer (50, [0023]) located between the metal gate line (52) and the dielectric fin (25), between the metal gate line (52) and the first fin (second from left 24), and between the metal gate line (52) and the second fin (second from right 24); and
a gate isolation structure (78, [0052]) extending through the metal gate line (52) and the gate dielectric layer (50), and landing on the dielectric fin (25),
wherein the metal gate line (52) is in contact with upper sidewalls of the gate isolation structure (78) (see Fig. 18A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20210125875) in view of Choi et al. (US 12324238).
Regarding claim 3, Tsai teaches the limitations of claim 2. Tsai does not explicitly teach that a width of the dielectric fin is equal to or greater than a width of the first fin and a width of the second fin.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a width of the dielectric fin (SEP1; col. 19, lines 1-15) is equal to or greater than a width of the first fin (first CH1 to the left of SEP1; col. 5, lines 1-10) and a width of the second fin (first CH1 to the right of SEP1) (see Fig. 17), so that “electric characteristics of a semiconductor device may be improved” (col. 25, lines 15-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Tsai with the widths of Choi, so that electric characteristics of a semiconductor device may be improved (col. 25, lines 15-35).
Regarding claim 4, Tsai teaches the limitations of claim 1. Tsai does not explicitly teach that a top surface of the dielectric fin is covered by the gate dielectric layer.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a top surface of the dielectric fin (SEP1; col. 19, lines 1-15) is covered by the gate dielectric layer (GI; col. 9, lines 50-55), in order to “provide a semiconductor device with improved electric characteristics” (col. 1, lines 30-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Tsai with the dielectric fin configuration of Choi, in order to provide a semiconductor device with improved electric characteristics (col. 1, lines 30-35).
Claims 6, 23-24, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20210125875) in view of Min et al. (US 12170281).
Regarding claim 6, Tsai teaches the limitations of claim 1. Tsai does not teach that a topmost surface of the gate dielectric layer located over the dielectric fin is lower than a topmost surface of the metal gate line located over the dielectric fin.
In a similar field of endeavor, Min teaches, in Fig. 25, that a topmost surface of the gate dielectric layer (130/230) located over the dielectric fin (160B) is lower than a topmost surface of the metal gate line (120) located over the dielectric fin (160B) (see Fig. 25), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Tsai with the gate dielectric layer configuration of Min, in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
Regarding claim 23, Tsai teaches the limitations of claim 21. Tsai does not teach that the gate isolation structure comprises a first portion and a second portion connected with the first portion, the first portion disposed on the dielectric fin and surrounded by the gate dielectric layer, and the second portion is in direct contact with the metal gate line.
In a similar field of endeavor, Min teaches, in Fig. 10, that the gate isolation structure comprises a first portion (160B_UR; col. 14, lines 60-65) and a second portion (160U) connected with the first portion (col. 13, line 65 – col. 14, line 5; col. 19, lines 10-15), the first portion (160B_UR) disposed on the dielectric fin (160B_BR) (col. 14, line 60 – col. 15, line 15) and surrounded by the gate dielectric layer (130/230) (see Fig. 10), and the second portion (160U) is in direct contact with the metal gate line (120) (see Fig. 10), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate isolation structure configuration of Tsai with the gate isolation structure of Min, in order to improve performance and reliability of the semiconductor device (col. 1, lines 35-40).
Regarding claim 24, Tsai teaches the limitations of claim 21. Tsai does not teach that the topmost surface of the gate dielectric layer is lower than a top surface of the gate isolation structure.
In a similar field of endeavor, Min teaches, in Fig. 25, that the topmost surface of the gate dielectric layer (130/230) is lower than a top surface of the gate isolation structure (160U) (see Fig. 25), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate dielectric layer configuration of Tsai with the gate dielectric configuration of Min, in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
Regarding claim 27, Tsai teaches the limitations of claim 21. Tsai does not teach that the gate isolation structure further extends into the dielectric fin, and a bottom surface of the gate isolation structure is lower than a bottom surface of the metal gate line.
In a similar field of endeavor, Min teaches, in Fig. 13, that the gate isolation structure (160U) further extends into the dielectric fin (160B), and a bottom surface of the gate isolation structure (160U) is lower than a bottom surface (the topmost surface of 130 contacting 120) of the metal gate line (120) (see Fig. 13), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate isolation structure configuration of Tsai with the gate isolation structure and dielectric fin of Min, in order to improve performance and reliability of the semiconductor device.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 20210083072) in view of Min et al. (US 12170281).
Regarding claim 9, Feng teaches the limitations of claim 8. Feng does not teach that the gate dielectric layer is in contact with lower sidewalls of the gate isolation structure.
In a similar field of endeavor, Min teaches, in Fig. 25, that the gate dielectric layer (130/230; col. 9, lines 15-20; col. 17, lines 20-25) is in contact with lower sidewalls of the gate isolation structure (160U, col. 13, lines 60-67), in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate dielectric layer configuration of Feng with the gate dielectric layer configuration of Min, in order to “improve performance and reliability” of the semiconductor device (col. 1, lines 35-40).
Regarding claim 10, Feng in view of Min teaches the limitations of claim 9. Min, in Fig. 25, further teaches that a contact area between the metal gate line (120; col. 4, lines 30-40) and a sidewall of a first side of the gate isolation structure (160U) is greater than a contact area between the gate dielectric layer (130/230) and the sidewall of the first side of the isolation structure (160U) (see Fig. 25).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 20210083072) in view of Choi et al. (US 12324238).
Regarding claim 11, Feng teaches the limitations of claim 8. Feng does not teach that a width of the dielectric fin is greater than a width of the first fin, a width of the second fin, and a width of the gate isolation structure.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a width of the dielectric fin (SEP1; col. 19, lines 1-15) is equal to or greater than a width of the first fin (first CH1 to the left of SEP1; col. 5, lines 1-10), a width of the second fin (first CH1 to the right of SEP1), and a width of the gate isolation structure (CT; col. 9, lines 10-25), so that “electric characteristics of a semiconductor device may be improved” (col. 25, lines 15-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the widths of Feng with the widths of Choi, so that “electric characteristics of a semiconductor device may be improved” (col. 25, lines 15-35).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 20210083072) in view of Choi et al. (US 12324238) and Tsai et al. (US 20210125875).
Regarding claim 12, Feng teaches the limitations of claim 8. Feng does not teach that a width of the dielectric fin is greater than a width of the first fin, a width of the second fin, and equal to a width of the gate isolation structure.
In a similar field of endeavor, Choi teaches, in Fig. 17, that a width of the dielectric fin (SEP1; col. 19, lines 1-15) is equal to or greater than a width of the first fin (first CH1 to the left of SEP1; col. 5, lines 1-10) and a width of the second fin (first CH1 to the right of SEP1) (see Fig. 17), so that “electric characteristics of a semiconductor device may be improved” (col. 25, lines 15-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Feng with the widths of Choi, so that electric characteristics of a semiconductor device may be improved (col. 25, lines 15-35).
Feng in view of Choi does not explicitly teach that a width of the dielectric fin is equal to a width of the gate isolation structure.
Tsai teaches that a width of the dielectric fin (25, [0021]) is equal to a width of the gate isolation structure (60, [0050]) ([0052]-[0053]), so that the gate stack material can be deposited with greater fill efficiency and to improve device performance and processing reliability ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Feng in view of Choi with the widths of Tsai, so that the gate stack material can be deposited with greater fill efficiency and to improve device performance and processing reliability ([0053]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20210125875) in view of Ching et al. (US 20200058649), and further in view of Wang et al. (US 20200006075).
Regarding claim 13, Feng teaches the limitations of claim 8. Feng does not explicitly teach that a width of the dielectric fin is equal to a width of the first fin, a width of the second fin, and a width of the gate isolation structure.
In a similar field of endeavor, Tsai teaches that a width of the dielectric fin (25) is equal to a width of the gate isolation structure (60) ([0052]), so that the gate stack material can be deposited with greater fill efficiency and to improve device performance and processing reliability ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the FinFET device of Feng with the widths of Tsai, so that the gate stack material can be deposited with greater fill efficiency and to improve device performance and processing reliability ([0053]).
Feng in view of Tsai does not explicitly teach that a width of the dielectric fin is equal to a width of the first fin and a width of the second fin.
In a similar field of endeavor, Wang teaches that a width of the dielectric fin is equal to a width of the first fin and a width of the second fin, in order to “help improve the uniformity of the fins” and control the thickness of the isolation structure ([0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the fin widths of Feng in view of Tsai with the equal fin widths of Wang, in order to help improve the uniformity of the fins and control the thickness of the isolation structure ([0036]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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