DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/31/2026 has been entered.
Response to Amendment
The amendments filed on 3/31/2026 have been entered and considered. The amendments to claims 1, 2, 6-7, 12, 14-15, and 17 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 1 and 12 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Song et al. US 20160049378 A1, which has been previously presented, Chen et al. US 20140231125 A1, newly presented in this office action, and in view of Yap et al. US 20150333028 A1, which has been previously presented. Song teaches the general semiconductor structure, Chen teaches a first tapered surface on a bonding pad, and Yap teaches a second tapered surface on a first film over a bonding pad.
Applicant' s arguments with respect to claim 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
Claims 1, 7, and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "solder material" in line 16 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner understands the applicant refers to “solder material portion” as previously claimed.
Claim 7 recites “the exposed portion of the bonding pad. There is insufficient antecedent basis for this limitation in the claim. The examiner understands a surface of the bonding pad becomes exposed since a portion of the surface of the bonding pad has the first film thereon, as claimed in claim 1.
Claim 15 recites the limitation “the second taper angle”. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the examiner will consider the limitation to mean “a second taper angle in the second aperture”.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites “the portion of the bonding pad has a second thickness less than the first thickness, wherein the first tapered surface extends from the exposed portion of the bonding pad, and the first tapered surface includes a partial portion of the bonding pad and a sidewall of the first film.” The limitations appear to mean that the bonding pad portion upon which the first film is disposed is thinner than the exposed portion of the bonding pad. No support was found in the applicant’s specification or figures regarding such limitations. Furthermore, the examiner is unable to conceive a structure where a partial portion of the bonding pad is part of the first tapered surface when the portion of the bonding pad covered by the first film has the second thickness. For the bonding pad to have a surface that is part of the first tapered surface, the exposed portion of the bonding must have a tapered portion and a central portion of lesser thickness. For purposes of examination, the examiner will treat the limitations as “the exposed portion of the bonding pad has a second thickness less than the first thickness, wherein the first tapered surface extends from the exposed portion of the bonding pad, and the first tapered surface includes a partial portion of the bonding pad and a sidewall of the first film.”, which is consistent with applicant’s disclosure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US 20160049378 A1 (hereinafter referred to as Song), in view of Chen et al. US 20140231125 A1 (hereinafter referred to as Chen), in view of Yap et al. US 20150333028 A1 (hereinafter referred to as Yap).
Regarding claim 1, Song teaches
A semiconductor device (“integrated device” para. 0045 FIG. 4H), comprising:
an electrical interconnect layer (“via 214” para. 0023);
a bonding pad having a first thickness electrically coupled to the electrical interconnect layer (“pad 210” para. 0046);
a stacked film structure comprising a first film (“dielectric layer 232” para. 0048) such that the bonding pad is formed within the first film (“dielectric layer 232” is formed on top of and around “pad 210, para. 0048) and a second film (“solder-resist 234” para. 0050) partially covering the first film (only portions of “solder-resist 234” above or near “pad 210” are removed, para. 0051);
a first aperture formed in the first film over a portion of the surface of the bonding pad (etching is performed to expose portions of “pad 210” while leaving portions of “dielectric layer 232” intact, para.0048);
a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture (portions of “solder-resist 234” above or near “pad 210” are removed and FIG. 4G-4H show portions in contact with “dielectric layer 232”, para. 0051);
a solder material portion (“first solder ball 208” para. 0052) formed in contact with the bonding pad, wherein the solder material portion comprises a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film (FIG. 4H shows “underfill 236” between “first solder ball 208” and “solder-resist 234”), and wherein the solder material fills the first aperture and forms a bottom of the solder material portion (“solder ball 208” is coupled to “pad 210” and at least partially fills the aperture of “dielectric layer 232” as suggested in FIG. 4H); and
an underfill material (“underfill 236”) portion surrounding a sidewall of the solder material portion, covering a top surface of the first film and the second film, wherein the bonding pad is separated from the underfill material portion (since “underfill 326” is provided in the space under “die 204”, it is understood to fill the space around “solder ball 208”, on “dielectric layer 232”, and on “solder-resist 234” as seen in FIG. 4H, para. 0053).
However, Song fails to teach wherein the first aperture includes a first tapered surface having a first taper angle and the second aperture include a second tapered surface having a second taper angle, the solder material portion does not contact the second tapered surface of the second film, the solder material abuts the first tapered surface, the underfill material covers the second tapered surface.
Nevertheless, Chen teaches
the first aperture (opening in “NCF 402” where “connector 302” is disposed, para. 0036 FIG. 8) includes a first tapered surface having a first taper angle (“NCF 402” conforms to the sides of “connector 302”, para. 0024, and a “sidewall angle 602” forms between a tangent of the “connector 302” and the top surface of “NCF 402”, para. 0031),
the solder material abuts the first tapered surface (“connector 302” is in contact with the sidewall of “NCF 402”, ass seen in FIG. 8).
Song and Chen teach interconnects on bond pads within apertures of an insulating layer. Since “NCF 402” conforms to the sides of “connector 302”, the “connector 302” having a round shape, the width of “NCF 402” in contact with “connector 302” reduces as it reaches the bottom portion of “connector 302”: the sidewall of “NCF 402” tapers towards the bottom. In the different embodiments, “NCF 402” is used to support “connector 302” during reflow (para. 0017) and reduce the stress between “connector 302” and the underlying interconnect, which improves the reliability of the connector (para. 0042). In the embodiment of FIG. 8, a tangent of “connector 602” and the top surface of “NCF 402” form a “sidewall angle 602”. The examiner understands that the sidewall of “NCF 402” in contact with the tangent of “connector 302” also has a same angle as “sidewall angle 602”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “dielectric 232” in Song having a tapered sidewall in contact with the “first solder ball 208” protects the shape of “first solder balls 208” and reduces stress between “first solder balls 208” and the underlying “pad 210”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Song with the first tapered surface taught in Chen. The first aperture having a tapered sidewall supports the solder material portion during reflow and reduces stress.
However, Song, modified by Chen, fail to teach the second aperture include a second tapered surface having a second taper angle, the solder material portion does not contact the second tapered surface of the second film, the underfill material covers the second tapered surface.
Nevertheless, Yap teaches
the second aperture (aperture of “solder mask layer 38” para. 0015 FIG. 2) includes a second tapered surface having a second taper angle ("solder mask layer 38" has slanted "sidewall surfaces 44", para. 0015 FIG. 2.),
the solder material portion does not contact the second tapered surface of the second film (there is a “clearance C.sub.1” between “solder ball 34” and sidewalls of “solder mask layer 38”, para. 0017 FIG. 2).
Song, modified by Chen, and Yap teach film stack structures over a bonding pad with a solder ball. The “sidewall surfaces 44” are slanted and provide a clearance between the “solder balls 34” and “solder mask layer 38” (para. 0017). Clearance reduces the likelihood of crack formation and delamination of the caused by crack formation at the interface of “solder balls 34” and “solder balls 34” during thermal cycling (para. 0017). Even though the angle of “sidewall surface 44” is not specified, the clearance can have any value as long as there is a gap between “solder balls 34” and “solder mask layer 38” (para. 0017). The examiner understands that a wider opening is either due to a smaller taper angle or a greater diameter along the entire “sidewall surface 44”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a clearance between “solder balls 34” and “solder mask layer 38” minimizes the risk of cracking and delamination. The angle of the “sidewall surface 44” can be as small or large as desired as long as a gap is maintained, smaller angles providing a larger gap.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song and Chen with the tapered surface of the second aperture as taught in Yap. The tapered surface maintains a clearance between the second film and the solder material, reducing the risk of cracking and delamination.
Song, modified by Chen and Yap, further teaches
the underfill material covers the second tapered surface (“underfill 236” contacts the side surface of “solder-resist 234”, now tapered as taught in Yap).
Regrading claim 2, Song, modified by Chen and Yap, teaches the semiconductor device of claim 1, wherein the solder material portion comprises a second width that is similar to a size of the first aperture such that the solder material portion is in contact with the first film (“solder ball 208” is shown as being in contact with “dielectric layer 232”).
Regrading claim 3, Song, modified by Chen and Yap, teaches the semiconductor device of claim 1, further comprising wherein the underfill material portion is formed between the solder material portion and an edge of the second aperture (“underfill 236” fills the space under “die 204” as is shown in FIG. 4H to be between “solder ball 208” and “solder-resist 234”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Song, modified by Chen and Yap, as applied to claim 1 above, in view of Kim et al. US 20200020637 A1 (hereinafter referred to as Kim).
Song, modified by Chen and Yap, teaches the semiconductor device of claim 1, wherein the first film comprises a polymer material (“NCF 402” may be a nonconductive material such as a polymer, para. 0017).
However, Song, modified by Chen and Yap, fails to teach the second film comprises an epoxy material.
Nevertheless, Kim teaches
the second film comprises an epoxy material (“first molding layer 390 may be formed of a dielectric polymer such as an epoxy molding compound” para. 0055).
Song, modified by Chen and Yap, and Kim, teach semiconductor devices with solder materials exposed through film apertures. The “solder-resist 234” in Song has recesses that expose “pad 210” so that “solder ball 208” can be formed for external connection. Similarly, “first molding layer 390” exposes a “first pad 410” so that solder material can be formed for external connection. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that an epoxy molding compound is a suitable alternative for use as a dielectric film that protects a side of the semiconductor device and allows for the formation of apertures to expose connection points.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song, Chen, and Yap, with the second film material taught in Kim. Epoxy material is a suitable material for use as an insulating film.
Claims 5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Song, modified by Chen and Yap, as applied to claim 1 above, in view of Yim et al. US 20230021867 A1 (hereinafter referred to as Yim).
Regarding claim 5, Song, modified by Chen and Yap, teaches the semiconductor device of claim 1 and further teaches
wherein the electrical interconnect layer is formed as part of a redistribution layer (“via 214” and “trace 216” along with the “vias 216, 314, 326” and “traces “228, 316, 328” are understood to be part of a redistribution layer, para. 0035).
However, Song, modified by Chen and Yap, fails to teach a first package comprising a first semiconductor die, wherein the electrical interconnect layer is electrically coupled to the first semiconductor die, the redistribution layer on a first side of the first package, wherein the first semiconductor die is configured as a system-on-chip die.
Nevertheless, Yim teaches
a first package (“semiconductor package 100A” para. 0019 FIG. 1A and 10) comprising a first semiconductor die (“semiconductor chip 120”, para. 0019 FIG. 1A and 10),
wherein the electrical interconnect layer (lower portion of “upper wiring layer 132” of “upper substrate 130” para. 0020) is electrically coupled to the first semiconductor die (“upper wiring layer 132” is connected to “semiconductor chip 120” through the “connection structure 140” and “lower substrate 110”, para. 0023 and 0032),
the redistribution layer on a first side of the first package (“wiring layer 132” of “upper substrate 130” is on a first side of “semiconductor package 100A”),
wherein the first semiconductor die (“semiconductor chip 120” para. 0044 FIG. 5A and 10) is configured as a system-on-chip die (“semiconductor chip 120 may be a system on chip” para. 0044).
Song, modified by Chen and Yap, and Yim teach packages of semiconductor die interconnected with solder bumps. A system-on-chip die has many components in a single integrated circuit and therefore greater functionality (para. 0044). Such as chip can be used in combination with multiple other dies such as the “second semiconductor chip 220” in FIG. 10 (para. 0057-0058) with use of “upper substrate 130” and “lower substrate 110”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a system-on-chip die can be used when multiple functions are required by the same die and multiple devices are connected to the die.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song, modified by Chen and Yap, with the system-on-chip die taught in Yim. The system-on-chip die can perform multiple functions and can be integrated with a plurality of other dies.
Regarding claim 8, Song, modified by Chen and Yap, teaches the semiconductor device of claim 5 but fails to teach wherein the first package further comprises: a molding material that partially or completely encloses the first semiconductor die within the first package; and a through-molding-material via formed within the molding material, wherein the through-molding-material via is electrically connected to the bonding pad.
Nevertheless, Yim teaches
wherein the first package (“semiconductor package 100A” para. 0019 FIG 1A) further comprises: a molding material (“encapsulant 150” para. 0020 FIG. 1 and 10) that partially or completely encloses the first semiconductor die (“semiconductor chip 120” para. 0028 FIG. 1 and 10within the first package (“encapsulant 150” encloses “semiconductor chip 120”);
a through-molding-material via (“connection structure 140” para. 0020 FIG. 1 and 10) formed within the molding material (“encapsulant 150” para. 0020 FIG. 1 and 10), wherein the through-molding-material via is electrically connected to the bonding pad (because “connection structure 140 may be disposed between the lower substrate 110 and the upper substrate 130 to electrically connect the lower substrate 110 and the upper substrate 130”, “connection structure 140” is understood to be connected to “upper wiring layer 132”, para. 0032 and 0055).
Song, modified by Chen and Yap, and Yim teach packages of semiconductor die interconnected with solder bumps. Yim teaches “semiconductor chip 120” in “first package 100” as a system-on-chip die used in combination with multiple “second semiconductor chip 220” of “second package 200” (para. 0057-0058 FIG. 10). “Semiconductor chip 120” and “semiconductor chips 220” are interconnected through “connection structure 140” but are also connected to “connection bumps 160” that connect to external devices (para. 0035 FIG. 10). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “connection structure 140” allows for communication between stacked packages in a device while also enabling connection to an external device. The first package can connect through both sides.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song, Chen, and Yap, with the through-molding-material via taught in Yim. The through-molding-material via enables electrical communication across the first package to its first and second sides.
Regarding claim 9, Song, modified by Chen, Yap, and Yim, teaches the semiconductor device of claim 8 and further teaches
wherein the first package further comprises: an interposer (“lower substrate 110” Yim para. 0020 FIG. 1 and 10) formed on a second side (bottom of “first package 100”) of the first package, wherein the interposer is electrically coupled to one or both of the first semiconductor die and the through-molding-material via (“connection structure 140” connects “upper substrate 130” and “lower substrate 110”, and “semiconductor chip 120” is mounted on “lower substrate 110”, para. 0023 and 0032).
Regarding claim 10, Song, modified by Chen, Yap, and Yim, teaches the semiconductor device of claim 5,
further comprising: a second package (“second package 200” Yim para. 0057 FIG. 10) comprising a second semiconductor die (“second semiconductor chip 220” para. 0058 FIG. 10), wherein the second package is electrically coupled to the solder material portion (“metal bump 260” made of low melting point metal or alloy of tin, para. 0060 FIG. 10).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Song, modified by Chen and Yap, as applied to claim 1 above, in view of Wang et al US 20230061167 A1 (hereinafter referred to as Wang).
Song, modified by Chen and Yap, teaches the semiconductor device of claim 1 but fails to teach wherein the first aperture comprises a first width that is an a range from approximately 100 microns to approximately 300 microns, and wherein the second aperture comprises a second width that is in a range from approximately 110 microns to approximately 500 microns.
Nevertheless, Wang teaches
wherein the first aperture comprises a first width that is an a range from approximately 100 microns to approximately 300 microns (opening in “first tier 108a” has a width “w.sub.b1” of 20-500 nm, para. 0063 FIG. 4), and wherein the second aperture comprises a second width that is in a range from approximately 110 microns to approximately 500 microns (opening in “second tier 108b” has a width “w.sub.b2” of 22-550 nm, para. 0063 FIG. 4).
Song, modified by Chen and Yap, and Wang teach insulating film stacks with openings for bumps. The openings in the “first tier 108a” and “second tier 108b” accommodate portions of the “conductive bump 103” (para. 0063). The tiers of insulating material function as solder resists that contain each “conductive bump 103” within each opening (para. 0042, 0063). The tiers of insulating material prevent shorting across neighboring “conductive bumps 103” and can also affect the distance between “first substrate 101” and “second substrate 106” (para. 0042, 0064). The greater the openings, the more the “conductive bump 103” can spread along the horizontal, which reduces the vertical dimension of the “conductive bump 103”. Likewise, Chen teaches that the thickness of “NCF 402” and “sidewall angle 602” can be determined based on the height of “connector 302” (Chen para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the diameters of the openings affect how much of the solder can be accommodated within each opening and how much is the separation between bonded substrates.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song, Chen, and Yap, with the aperture widths taught in Wang. The widths of the first and second aperture help determine the height of the solder material portion in the openings after bonding with another device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Song, modified by Chen and Yap, as applied to claim 1 above, in view of Yang et al. US 20230209926 A1 (hereinafter referred to as Yang).
Song, modified by Chen and Yap, teaches the semiconductor device of claim 1, wherein the first taper angle and the second taper angle are in a range from approximately 5 degrees to 50 degrees (“sidewall angle 602 is between about 90 degrees and about 65 degrees”, corresponding to an angle of 0-25 degrees relative to a vertical direction, Chen para. 0036, and the angle between "sidewall surfaces 44" and the surface of "contact point 43" is evidently between 0 and 90 degrees in Yap).
However, Song, modified by Chen and Yap, fails to teach wherein the portion of the bonding pad has a second thickness less than the first thickness, wherein the first tapered surface extends from the exposed portion of the bonding pad, and the first tapered surface includes a partial portion of the bonding pad and a sidewall of the first film.
Nevertheless, Yang teaches
wherein the portion of the bonding pad (“2-2 pad portion 400P3” of “pad 400” para. 0060 FIG. 3, 11, 12) has a second thickness (“thickness Tp3” para. 0123 FIG. 11) less than the first thickness (“thickness Tp1”, para. 0123), wherein the first tapered surface extends from the exposed portion of the bonding pad, and the first tapered surface includes a partial portion of the bonding pad and a sidewall of the first film (as seen in FIG. 12, the sidewall of the aperture “second hole OL-H” includes a sidewall of “organic insulating layer OL” and a sidewall of “first pad protective layer 407”, para. 0125-1027 FIG. 12).
Song, modified by Chen and Yap, and Yang teach bond pads exposed by dielectric films. The “pad 400” has portions with different thicknesses (para. 0123). This is due to loss of “first protective pad layer 407” during etching to form the aperture (para. 0127). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a portion of “pad 210” may be removed when the first aperture in “dielectric layer 232” is formed. A sidewall of “pad 210” and a sidewall of “dielectric 232” may constitute the sidewall of the aperture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first tapered surface in the semiconductor device taught between Song, Chen, and Yap includes a partial portion of the bonding pad and a sidewall of the first film as taught in Yang. When etching the first film, a portion of the bonding pad may be removed, forming an exposed portion with a second thickness smaller than the first. Due to this over-etching, a partial portion of the bonding pad forms part of the tapered surface.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Song, modified by Chen and Yap, as applied to claim 1 above, in view of Dangayach et al. US US 5037898 A (hereinafter referred to as Dangayach).
Song, modified by Chen and Yap, fails to teach wherein the second film comprises a film modulus greater than 3 GPa, a fracture toughness greater than 0.5 MPa mi2, and a film coefficient of thermal expansion greater than 10 ppm/ C.
Nevertheless, Dangayach teaches an epoxy molding composition with a modulus between 475-2033 ksi (3.28-14.02 GPa), a fracture toughness between 670-2142 psi*in^1/2 (0.74-2.35 MPa*m^1/2), and a coefficient of thermal expansion of 19.7-90 ppm/C in the 50-100C range (“Table 2” in columns 8-10 of Dangayach. The molding composition is for use with semiconductor devices and has low internal stress (col 1 lines 7-40). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “first molding layer 390” may comprise the epoxy molding compound in Dangayach for its high modulus, high fracture toughness, high coefficient of thermal expansion, and low internal stress.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Song, Chen, and Yap, with the second film material taught in Dangayach. Epoxy molding compounds can have strong physical and thermal characteristics suitable for protection of semiconductor devices.
Claims 12-13, 16, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yim, in view of Song, in view of Chen.
Regarding claim 12, Yim teaches
A semiconductor device (“semiconductor package 1000” para 0056 FIG. 10), comprising:
a first semiconductor package (“first package 100” para. 0057 FIG. 10) comprising a first semiconductor die (“semiconductor die 120” para. 0044 FIG. 10) and a first bonding pad (contact point in “upper wiring layer 132” of “upper substrate 130” para. 0028 in FIG. 1, as shown in annotated FIG. 10) electrically coupled to the first semiconductor die (“semiconductor die 120” is connected to the “lower substrate 110” and “connection structure 140 may be disposed between the lower substrate 110 and the upper substrate 130 to electrically connect the lower substrate 110 and the upper substrate 130”, para. 0032);
a second semiconductor package (“second package 200” para. 0058 FIG. 10) comprising a second semiconductor die (“second semiconductor chip 220” para. 0058 FIG. 10) and a second bonding pad (“lower pad 211” para. 0058 FIG. 10) electrically coupled to the second semiconductor die (“redistribution substrate 210 may include a redistribution circuit 213 electrically connecting the lower pad 211 and the upper pad 212” and “upper pad 212” is connected to the “semiconductor chip 220”, para. 0058 FIG. 10); and
a solder material portion (“metal bump 260” para. 0060 FIG. 10) electrically connecting the first bonding pad of the first semiconductor package to the second bonding pad of the second semiconductor package, wherein the first semiconductor package further comprises a film structure (“plurality of insulating layers 131a, 131b, and 131c” para. 0028 FIG. 1 and 10).
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However, Yim fails to teach the stacked film structure comprising a first film partially covering a surface of the first bonding pad and a second film partially covering the first film, and wherein the second film is separated from the solder material portion, wherein the solder material fills a first aperture in the first film and forms a bottom of the solder material portion, wherein the first aperture includes a first tapered surface having a first taper angle; and an underfill material portion surrounding a sidewall of the solder material portion, covering a top surface of the first film and the second film, wherein the first bonding pad is separated from the underfill material portion.
Nevertheless, Song teaches
The stacked film structure comprising a first film (“dielectric layer 232” para. 0048) partially covering a surface of the bonding pad (“pad 210” para. 0046) and a second film (“solder-resist 234” para. 0050) partially covering the first film, and wherein the second film is separated from the solder material portion (FIG. 4H shows “underfill 236” between “first solder ball 208” and “solder-resist 234”), and
wherein the solder material fills the first aperture and forms a bottom of the solder material portion (“solder ball 208” is coupled to “pad 210” and at least partially fills the aperture of “dielectric layer 232” as suggested in FIG. 4H); and
an underfill material (“underfill 236” para. 0053) portion surrounding a sidewall of the solder material portion, covering a top surface of the first film and the second film, wherein the bonding pad is separated from the underfill material portion (since “underfill 326” is provided in the space under “die 204”, it is understood to fill the space around “solder ball 208”, on “dielectric layer 232”, and on “solder-resist 234” as seen in FIG. 4H, para. 0053).
Yim and Song teach semiconductor packages with solder bumps. The “dielectric layer 232” and “solder-resist 234” structure in Song covers a “heat-dissipation layer 230” so that it is isolated from “solder ball 208” (para. 0033). Furthermore, the examiner understands that “solder ball 208” is more easily accommodated in a large aperture than in a small aperture. As a result of “solder ball 208” being in an aperture that is larger than the “solder ball 208”, “underfill 236” will fill the gap. “Underfill 236” provides structural and mechanical support to the “solder ball 208” (Song para. 0053). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the stacked film structure “dielectric layer 232” and “solder-resist 234” ensures isolation from neighboring conductors and the large aperture of “solder-resist 234” can easily accommodate the “solder ball 208”. The “solder ball 208” can be supported by the “underfill 236” from one bond end to the other.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Yim with the stacked film structure taught in Song. The stacked film structure comprising first and second films is an effective insulating structure for isolating nearby conductors and the stacked film structure opening above the bonding pad readily accepts solder material. The underfill material provides support for the solder material and the package.
However, Yim, modified by Song, fails to teach wherein the first aperture includes a first tapered surface having a first taper angle.
Nevertheless, Chen teaches
wherein the first aperture (opening in “NCF 402” where “connector 302” is disposed, para. 0036 FIG. 8) includes a first tapered surface having a first taper angle (“NCF 402” conforms to the sides of “connector 302”, para. 0024, and a “sidewall angle 602” forms between a tangent of the “connector 302” and the top surface of “NCF 402”, para. 0031).
Yim, modified by Song, and Chen teach interconnects on bond pads within apertures of an insulating layer. Since “NCF 402” conforms to the sides of “connector 302”, the “connector 302” having a round shape, the width of “NCF 402” in contact with “connector 302” reduces as it reaches the bottom portion of “connector 302”: the sidewall of “NCF 402” tapers towards the bottom. In the different embodiments, “NCF 402” is used to support “connector 302” during reflow (para. 0017) and reduce the stress between “connector 302” and the underlying interconnect, which improves the reliability of the connector (para. 0042). In the embodiment of FIG. 8, a tangent of “connector 602” and the top surface of “NCF 402” form a “sidewall angle 602”. The examiner understands that the sidewall of “NCF 402” in contact with the tangent of “connector 302” also has a same angle as “sidewall angle 602”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “dielectric 232” in Song having a tapered sidewall in contact with the “first solder ball 208” protects the shape of “first solder balls 208” and reduces stress between “first solder balls 208” and the underlying “pad 210”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Song with the first tapered surface taught in Chen. The first aperture having a tapered sidewall supports the solder material portion during reflow and reduces stress.
Regarding claim 13, Yim, modified by Song and Chen, teaches the semiconductor device of claim 12 and further teaches
further comprising: a first aperture formed in the first film over a portion of the surface of the bonding pad (etching is performed to expose portions of “pad 210” while leaving portions of “dielectric layer 232” intact, para.0048);
a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture (portions of “solder-resist 234” above or near “pad 210” are removed and FIG. 4G-4H show portions in contact with “dielectric layer 232”, para. 0051).
Regarding claim 16, Yim, modified by Song and Chen, teaches wherein the solder material portion comprises a second width that is similar to a size of the first aperture such that the solder material portion is in contact with the first film (“solder ball 208” is shown as being in contact with “dielectric layer 232”).
Regarding claim 21, Yim, modified by Song and Chen, teaches wherein the first package (“semiconductor package 100A” Yim para. 0019 FIG 1A) further comprises: a molding material (“encapsulant 150” para. 0020 FIG. 1 and 10) that partially or completely encloses the first semiconductor die (“semiconductor chip 120” para. 0028 FIG. 1 and 10) within the first package (“encapsulant 150” encloses “semiconductor chip 120”);
a through-molding-material via (“connection structure 140” para. 0020 FIG. 1 and 10) formed within the molding material (“encapsulant 150” para. 0020 FIG. 1 and 10), wherein the through-molding-material via is electrically connected to the bonding pad (because “connection structure 140 may be disposed between the lower substrate 110 and the upper substrate 130 to electrically connect the lower substrate 110 and the upper substrate 130”, “connection structure 140” is understood to be connected to “upper wiring layer 132”, para. 0032 and 0055).
Regarding claim 22, Song, modified by Song and Chen, teaches the semiconductor device of claim 21, wherein the first package further comprises: an interposer (“lower substrate 110” Yim para. 0020 FIG. 1 and 10) formed on a second side (bottom of “first package 100”) of the first package, wherein the interposer is electrically coupled to one or both of the first semiconductor die and the through-molding-material via (“connection structure 140” connects “upper substrate 130” and “lower substrate 110”, and “semiconductor chip 120” is mounted on “lower substrate 110”, para. 0023 and 0032).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yim, modified by Song and Chen, as applied to claim 12 above, in view of Wang et al US 20230061167 A1 (hereinafter referred to as Wang).
Yim, modified by Song, teaches the semiconductor device of claim 12 but fails to teach wherein the first aperture comprises a first width that is an a range from approximately 100 microns to approximately 300 microns, and wherein the second aperture comprises a second width that is in a range from approximately 110 microns to approximately 500 microns.
Nevertheless, Wang teaches
wherein the first aperture comprises a first width that is an a range from approximately 100 microns to approximately 300 microns (opening in “first tier 108a” has a width “w.sub.b1” of 20-500 nm, para. 0063 FIG. 4), and wherein the second aperture comprises a second width that is in a range from approximately 110 microns to approximately 500 microns (opening in “second tier 108b” has a width “w.sub.b2” of 22-550 nm, para. 0063 FIG. 4).
Yim, modified by Song and Chen, and Wang teach insulating film stacks with openings for bumps. The openings in the “first tier 108a” and “second tier 108b” accommodate portions of the “conductive bump 103” (para. 0063). The tiers of insulating material function as solder resists that contain each “conductive bump 103” within each opening (para. 0042, 0063). The tiers of insulating material prevent shorting across neighboring “conductive bumps 103” and can also affect the distance between “first substrate 101” and “second substrate 106” (para. 0042, 0064). The greater the openings, the more the “conductive bump 103” can spread along the horizontal, which reduces the vertical dimension of the “conductive bump 103”. Likewise, Chen teaches that the thickness of “NCF 402” and “sidewall angle 602” can be determined based on the height of “connector 302” (Chen para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the diameters of the openings affect how much of the solder can be accommodated within each opening and how much is the separation between bonded substrates.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Yim, Song, and Chen with the aperture widths taught in Wang. The widths of the first and second aperture help determine the height of the solder material portion in the openings after bonding with another device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yim, modified by Song and Chen, as applied to claim 1 above, in view of Yap et al. US 20150333028 A1 (hereinafter referred to as Yap).
Yim, modified by Song, teaches the semiconductor device of claim 1, wherein the first taper angle comprises a taper angle in a range from approximately 5 degrees to 50 degrees (“sidewall angle 602 is between about 90 degrees and about 65 degrees”, para. 0036, corresponding to an angle of 0-25 degrees relative to a vertical direction).
However, Yim, modified by Song and Chen, fails to teach a second taper angle in the second aperture comprises a taper angle in a range from approximately 5 degrees to 50 degrees.
Nevertheless, Yap teaches
a second taper angle in the second aperture ("solder mask layer 38" has slanted "sidewall surfaces 44", para. 0015 FIG. 2) comprises a taper angle in a range from approximately 5 degrees to 50 degrees (The angle between the sidewall and the surface of "contact point 43" is evidently between 0 and 90 degrees.).
Yim, modified by Song and Chen, and Yap teach film stack structures over a bonding pad with a solder ball. The “sidewall surfaces 44” are slanted and provide a clearance between the “solder balls 34” and “solder mask layer 38” (para. 0017). Clearance reduces the likelihood of crack formation and delamination of the caused by crack formation at the interface of “solder balls 34” and “solder balls 34” during thermal cycling (para. 0017). Even though the angle of “sidewall surface 44” is not specified, the clearance can have any value as long as there is a gap between “solder balls 34” and “solder mask layer 38” (para. 0017). The examiner understands that a wider opening, either due to a smaller taper angle or a greater diameter along the entire “sidewall surface 44”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a clearance between “solder balls 34” and “solder mask layer 38” minimizes the risk of cracking and delamination. The angle of the “sidewall surface 44” can be as small or large as desired as long as a gap is maintained, smaller angles providing a larger gap.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Yim, Song, and Chen with the tapered surface of the second aperture as taught in Yap. The tapered surface maintains a clearance between the second film and the solder material, reducing the risk of cracking and delamination.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Song, in view of Adachi et al. US 20230113278 A1 (hereinafter referred to as Adachi), in view of Yang, and in view of Pan et al. US 20150340330 A1 (hereinafter referred to as Pan).
Song taches
A method of forming a bonding structure for a semiconductor device (method of forming “integrated device” para. 0045 FIG. 4H), comprising:
forming a first film (“dielectric layer 232” para. 0048 FIG. 4C) over a bonding pad (“pad 210” para. 0046) of an electrical interconnect layer (“via 214” and “trace 216” in “dielectric layer 202” para. 0046);
forming a second film (“solder-resist 234” para. 0050 FIG. 4F) over the first film;
forming a solder material portion (“first solder ball 208” para. 0052) that is in contact with the bonding pad but is separated from the second film (FIG. 4H shows “underfill 236” between “first solder ball 208” and “solder-resist 234”), wherein the solder material fills the first aperture and forms a bottom of the solder material portion (“solder ball 208” is coupled to “pad 210” and at least partially fills the aperture of “dielectric layer 232” as suggested in FIG. 4H); and
forming an underfill material (“underfill 236”) portion surrounding a sidewall of the solder material portion, covering a top surface of the first film and the second film, wherein the bonding pad is separated from the underfill material portion (since “underfill 326” is provided in the space under “die 204”, it is understood to fill the space around “solder ball 208”, on “dielectric layer 232”, and on “solder-resist 234” as seen in FIG. 4H, para. 0053).
However, Song fails to teach exposing the first film and the second film to laser radiation, comprising: performing a first laser drilling process to generate the first aperture in the first film and to generate the second aperture in the second film; and performing a second laser drilling process to increase a width of the second aperture, wherein the first aperture exposes a portion of the bonding pad, and the second aperture is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, wherein the exposed portion of the bonding pad has a second thickness less than the first thickness and wherein the first aperture includes a first tapered surface extending from the exposed portion of the bonding pad.
Nevertheless, Adachi teaches
exposing the first film and the second film to laser radiation, comprising:
a first laser drilling process to generate the first aperture in the first film and to generate the second aperture in the second film (“by laser processing, openings (vo) are formed that continuously penetrate the second insulating layer 112 and the first resin insulating layer 111 to expose the conductor layer 12” para. 0045 FIG. 3D); and
performing a second laser drilling process to increase a width of the second aperture (“recesses (op1, op2) penetrating the second resin insulating layer 112 are drilled by ablation with laser such as excimer laser” para. 0048 FIG. 3E), wherein the first aperture exposes a portion of the bonding pad (“conductor layer 12” para. 0021 FIG. 2 and 3A), and the second aperture is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture (“opening (vo)” is within “recess (op2)”).
Song and Adachi openings of stacked insulating films for interconnect structures. The patterning of “dielectric layer 232” and “solder-resist 234” is done by etching (para. 0048 and 0051). Adachi teaches a first laser ablation using CO2 laser to form the “openings (vo)” in “first resin insulating layer 111” and “second insulating layer 112” (para. 0045) and a separate laser drilling to form the “recess (op2)” overlapping “conductor layer 12” (para. 0047). The resulting film stack has a first and second opening analogous to that in Song. Similar to etching, the laser processability of each film is different due to the different material of each film (Adachi para. 0038). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that laser ablation or drilling is a suitable alternative method to etching for forming openings in insulating layers of different materials.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Song with the first and second laser drilling processes taught in Adachi. Laser drilling processes are known to work for insulating layers having different materials and the separate processes allow for widening of the second opening.
However, Song, modified by Adachi, fails to teach wherein the exposed portion of the bonding pad has a second thickness less than the first thickness and wherein the first aperture includes a first tapered surface extending from the exposed portion of the bonding pad.
Nevertheless, Yang teaches
wherein the exposed portion of the bonding pad has a second thickness less than the first thickness and wherein the first aperture includes a first tapered surface extending from the exposed portion of the bonding pad.
wherein the exposed portion of the bonding pad (“2-2 pad portion 400P3” of “pad 400” para. 0060 FIG. 3, 11, 12) has a second thickness (“thickness Tp3” para. 0123 FIG. 11) less than the first thickness (“thickness Tp1”, para. 0123) and wherein the first aperture includes a first tapered surface extending from the exposed portion of the bonding pad (as seen in FIG. 12, the sidewall of the aperture “second hole OL-H” includes a sidewall of “organic insulating layer OL” and a sidewall of “first pad protective layer 407”, para. 0125-1027 FIG. 12).
Song, modified by Adachi, and Yang teach bond pads exposed by dielectric films. The “pad 400” has portions with different thicknesses (para. 0123). This is due to loss of “first protective pad layer 407” during etching to form the aperture (para. 0127). Yang discusses the dielectric films being etched but the etchant is unspecified (Yang para. 0107 and 0126-0127). Similarly, a recess extending into a pad can result when etching with lasers; Pan teaches a “recess 131” with a sidewall comprising sides of the “concave portion 132” of “conductive pad 130” and “oblique surface 126” of “first isolation layer 120” (para. 0044 FIG. 3). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a portion of “pad 210” may be removed when the first aperture in “dielectric layer 232” is formed by etching with a laser; it is a result of the aperture formation process. A sidewall of “pad 210” and a sidewall of “dielectric 232” may constitute the sidewall of the aperture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first tapered surface in the semiconductor device taught between Song and Adachi includes a partial portion of the bonding pad and a sidewall of the first film as taught in Yang. When laser etching the first film, a portion of the bonding pad may be removed, forming an exposed portion with a second thickness smaller than the first. Due to this over-etching, a partial portion of the bonding pad forms part of the tapered surface.
Regarding claim 18, Song, modified by Adachi, Yang, and Pan, teaches the method of forming a bonding structure for a semiconductor device of claim 17, wherein the forming the underfill material portion includes disposing the underfill material portion between the solder material portion and an edge of the second aperture (“underfill 236” fills the space under “die 204” as is shown in FIG. 4H to be between “solder ball 208” and “solder-resist 234”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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