DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) filed on 04 June 2026. Claims 1-20 are pending in the application.
This application is a divisional of application Serial No. 17/008,251, filed on 31 August 2020, now US Patent 12,224,213.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 May 2026 has been entered.
Claim Rejections - 35 USC § 112
In light of Applicant’s Amendment, the rejection of claims 16-20 under 35 U.S.C. 112(b) has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US 2019/0035934, newly cited.
With respect to claim 16, Chung et al. disclose an analog-to-digital converter, shown in Figs. 3 and 8, comprising:
a substrate 110 including a digital area I and an analog area III;
a plurality of fin structures FA1, FA2, FC1, and FC2 extending along a direction over the digital area I (as shown in Fig. 3) and the analog area III (as shown in Fig. 8) of the substrate 110;
a first transistor TR1 and a second transistor TR1 in the digital area I, wherein the first transistor includes a first gate structure NGA disposed over at least one the plurality of fin structures FA1 and the second transistor includes a second gate structure NGA disposed over at least one the plurality of fin structures FA2, see Fig. 3;
a first isolation structure 122 disposed between the first transistor TR1 and the second transistor TR1, wherein the first isolation structure 122 comprises a first isolation feature 122 extending a first depth into the plurality of fin structures FA1 and FA2 and a first isolation gate structure DG disposed on the first isolation feature 122, see Fig. 3;
a third transistor TR3 and a fourth transistor TR3 in the analog area III, wherein the third transistor TR3 includes a third gate structure NGC disposed over the plurality of fin structures FC1 and the fourth transistor TR3 includes a fourth gate structure NGC disposed over the plurality of fin structures FC2, see Fig. 8; and
a second isolation structure 122 disposed between the third transistor TR3 and the fourth transistor TR3, wherein the second isolation structure 122 comprises a second isolation feature 122 extending a second depth into the plurality of fin structures FC1 and FC2 and a second isolation gate structure DG3 disposed on the second isolation feature 122,
wherein top surfaces of the plurality of fin structures FA1 and FA2 below the first gate structure NGA and the second gate structure NGA arise above top surfaces of the first isolation structure 122 and the second isolation structure 122, as shown in Fig. 3 and 8. Since fins FA1, FA2, FC1 , and FC2 are formed on the substrate 110, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the top surfaces of the fin structures FA1 and FA2 are above the top surface of isolation structures 122, as shown in Figs. 3 and 8 of Chung et al.
Admittedly, the preamble of claim 16 recites an analog-to-digital convertor and the body of claim 16 requires a substrate including a digital area and an analog area. First, Chung et al. disclose that IC device 100 comprises a logic area (area I) and memory areas (area III), see paragraphs [0033] and [0070]-[0071]. Second, it has been well established that the manner of operating a device does not patentably distinguish a claimed device from a prior art device which is structurally the same. Device claims cover what a device is, not what a device does. Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed device is intended to operate does not differentiate the claimed device from a prior art device, if the prior art device teaches all the structural limitations of the device claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Therefore, requiring the device of claim 16 to be an analog-to-digital convertor (in the preamble) and requiring the substrate to include a digital area and an analog area are not deemed to structurally distinguish the device recited in claim 16 from the known device of Chung et al.
With respect to claim 17, in the analog-to-digital converter of Chung et al., the first depth is substantially identical to the second depth, since the first and second isolation structures 122 end through the fins FA1, FA2, FC1, and FC2 to the substrate 110m as shown in Figs. 3 and 8..
With respect to claim 18, in the device of Chung et al., the first isolation structure 122 includes a first width along the direction at the bottom of isolation structure 122 which is in contact with substrate 110, as shown in Fig. 3, and the second isolation structure 122 includes a second width along the direction at the top of isolation structure 122, as shown in Fig. 8, wherein the width of the first solation structure 122 is greater than the width of the first isolation structure 122, due to the tapered sidewalls of isolation structures 122, as shown in Figs. 3 and 8. However, Chung et al. do not disclose that the ratio of the second width to the first width is between about 3 and about 30. Since Chung et al. do teach that the width of the second isolation structure 122 measured near the top of isolation structure 122 is greater than the width of the first isolation structure 122 measured near substrate 110, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of the second width to the first width in the known device of Chung et al. to provide stability for forming the isolation gate structures. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Allowable Subject Matter
Claims 1-15 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter in claims 1-8: None of the references of record teach or suggest a semiconductor structure, as recited in independent claim 1, comprising a first gate structure disposed over the first fin segment; a first isolation gate structure disposed directly over the first isolation feature, wherein the first gate structure comprises a first gate length along the first direction, wherein the first isolation gate structure comprises a second gate length along the first direction, wherein the first gate length is greater than the second gate length.
The following is a statement of reasons for the indication of allowable subject matter in claims 9-15: None of the references of record teach or suggest a semiconductor device, as recited in independent claim 9, comprising a substrate including a first area and a second area; a plurality of fin structures extending along a direction over the first area and the second area of the substrate; a first transistor and a second transistor in the first area, wherein the first transistor includes a first gate structure disposed over at least one the plurality of fin structures and the second transistor includes a second gate structure disposed over at least one the plurality of fin structures; a first isolation structure disposed between the first transistor and the second transistor; a third transistor and a fourth transistor in the second area, wherein the third transistor includes a third gate structure disposed over the plurality of fin structures and the fourth transistor includes a fourth gate structure disposed over the plurality of fin structures; and a second isolation structure disposed between the third transistor and the fourth transistor, wherein the first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction, wherein the first width is below a resolution limit of a radiation source having a wavelength at about 248 nm, wherein the second width is within the resolution limit of the radiation source, wherein a ratio of the second width to the first width is between about 3 and about 30.
Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Chung et al., applied above. However, Chung et al. do not teach or suggest each of the first gate structure and the second gate structure includes a third width along the direction, wherein each of the third gate structure and the fourth gate structure includes a fourth width along the direction, wherein a ratio of the fourth width to the third width is between about 15 and about 400, as required in dependent claim 19.
Claim 20 has been objected to because of its dependency on claim 19.
Response to Arguments
Applicant’s arguments with respect to claims 16-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The additional references made of record and not relied upon are considered pertinent to applicant's disclosure. The additionally cited references disclose semiconductor devices with isolation gates.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
Prosecution Insights