Prosecution Insights
Last updated: April 19, 2026
Application No. 17/883,181

DISPLAY DEVICE

Final Rejection §102§103§112
Filed
Aug 08, 2022
Examiner
XU, ZHIJUN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
43 granted / 56 resolved
+8.8% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
43 currently pending
Career history
99
Total Applications
across all art units

Statute-Specific Performance

§103
67.5%
+27.5% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 56 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on Dec. 5th, 2025 has been entered. Claims 1-20 remain pending in the application. Claims 1-17 are examined in this office action. Claims 18-20 are withdrawn from further consideration. Applicant’s amendments to the Specification (Title) have overcome each and every objection previously set forth in the Non-Final Office Action mailed on Sep. 8th, 2025. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 13-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “gradually” in claim 13 is a relative term which renders the claim indefinite. The term “gradually” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, examiner has interpreted “gradually” to be consistent with the cited prior art. Claims 14-17 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 13. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 11 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Templier et al. (US 20210020688), hereinafter Templier. Regarding claim 11, Templier teaches an electronic device (Abstract) comprising: a substrate (fig. 2B, semiconductor substrate 151; para. 0040); contact electrodes (electrodes 161; para. 0062), a common contact electrode (common electrode 163; para. 0062) on the substrate (151); light-emitting elements (active LED stack of emissive layer 107; para. 0071) on the contact electrodes (161); and a common connecting electrode (metal connection pads 255, connection pads 205, metal electrode 113; para. 0038, 0067) on the common contact electrode (163), connected (electronically) to the light-emitting elements (LED of 107), and at a same layer (113 is at a same layer as LED of 107) as the light-emitting elements (LED of 107), wherein the common contact electrode (255, 205, 113) comprises conductive patterns (pattern of 205, 255), which are in contact with the common connecting electrode (163). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Templier. Regarding claim 12, Templier teaches the electronic device of claim 11 including the conductive patterns (fig. 2B, pattern of 205, 255). Templier fails to explicitly teach the conductive patterns account for 10% to 50% of a total area of the common connecting electrode. However, Templier teaches the conductive patterns (fig. 2B, pattern of 205, 255) account for around 5% to 50% (the rate of occupation by the metal pads is in the range from 5 to 50%; para. 0057), which overlaps the range of 10% to 50% of a total area of the common connecting electrode (163). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the area range from around 5% to 50% to 10% to 50%. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Claims 1-2 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Templier in view of Yoon et al. (KR 20170047641). Regarding claim 1, Templier teaches an electronic device (Abstract) comprising: a substrate (fig. 2B, semiconductor substrate 151; para. 0040); contact electrodes (electrodes 161 and metal connection pads 255; para. 0062, 0067), a common contact electrode (common electrode 163; para. 0062) on the substrate (151); light-emitting elements (active LED stack of emissive layer 107; para. 0071) respectively on the contact electrodes (161, 255); and a common connecting electrode (metal connection pads 255, connection pads 205, metal electrode 113; para. 0038, 0067) on the common contact electrode (163), connected (electronically) to the light-emitting elements (LED of 107), and comprising first conductive patterns (pattern of 205, 255) in contact with the common contact electrode (163). Templier fails to explicitly teach the first conductive patterns at a same layer as the light-emitting elements. However, Yoon teaches the first conductive patterns (Yoon: fig. 1, bumper bonding layer 20 on the left; para. 0014, similar to 113, 205 of Templier) at a same layer as the light-emitting elements (Yoon: light-emitting layer 35; para. 0016, similar to LED of 107 of Templier). Yoon and Templier are considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first conductive patterns at a same layer as the light-emitting elements as taught by Yoon. Doing so would realize forming each connection in one piece/step to increase production. Regarding claim 2, Templier in view of Yoon further teaches the display device of claim 1, wherein the first conductive patterns (Templier: fig. 2B, pattern of 205, 255) are spaced apart from one another (Templier: spaced apart from one another), and are formed as dots or lines (Templier: pattern of 205, 255 have lines). Regarding claim 5, Templier in view of Yoon further teaches the display device of claim 1, wherein the first conductive patterns (Templier: fig. 2B, pattern of 205, 255) comprise a same material (Templier: same material of 255) as the contact electrodes (Templier: 161, 255). Regarding claim 6, Templier in view of Yoon teaches the display device of claim 1 including the first conductive patterns (Templier: fig. 2B, pattern of 205, 255). Templier in view of Yoon fails to explicitly teach the first conductive patterns account for about 10% to 50% of a total area of the common connecting electrode. However, Templier teaches the conductive patterns (Templier: fig. 2B, pattern of 205, 255) account for around 5% to 50% (Templier: the rate of occupation by the metal pads is in the range from 5 to 50%; para. 0057), which overlaps the range of about 10% to 50% of a total area of the common connecting electrode (Templier: 163). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the area range from around 5% to 50% to about 10% to 50%. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 7, Templier in view of Yoon further teaches the display device of claim 1, wherein the common contact electrode (Templier: fig. 2B, in an alternative consideration, 255) further comprises second conductive patterns (Templier: pattern of 255) spaced apart from one another (Templier: 255 spaced apart from one another), and respectively overlapping the first conductive patterns (Templier: in an alternative consideration, pattern of 205). Regarding claim 8, Templier in view of Yoon further teaches the display device of claim 7, wherein the second conductive patterns (Templier: fig. 2B, pattern of 255) correspond one-to-one to the first conductive patterns (Templier: pattern of 205). Regarding claim 9, Templier in view of Yoon further teaches the display device of claim 7, further comprising a common electrode (Templier: fig. 2B, 163) between the substrate (Templier: 151) and the common contact electrode (Templier: 255). Templier in view of Yoon fails to explicitly teach the second conductive patterns account for about 10% to about 50% of a total area of the common electrode. However, Templier teaches the second conductive patterns (Templier: fig. 2B, pattern of 255) account for around 5% to 50% (Templier: the rate of occupation by the metal pads is in the range from 5 to 50%; para. 0057), which overlaps about 10% to about 50% of a total area of the common electrode (Templier: 163). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the area range from around 5% to 50% to about 10% to 50%. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 10, Templier in view of Yoon further teaches the display device of claim 1, wherein the light-emitting elements (Templier: fig. 2B, LED of 107) are in a display area (middle region), and wherein the common contact electrode (Templier: 163) and the common connecting electrode (Templier: 205, 255, 113) are in a non-display area (Templier: peripheral frame with no LED; para. 0050) surrounding the display area (Templier: middle region). Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Templier in view of Yoon as applied to claims 1 above, and further in view of Yoo et al. (US 20190164947). Regarding claim 3, Templier in view of Yoon teaches the display device of claim 1, wherein the light-emitting elements (Templier: fig. 2B, LED of 107) comprise a first semiconductor layer (Templier: semiconductor layer 109; para. 0071), an active layer (Templier: 107) on the first semiconductor layer (Templier: 109), a second semiconductor layer (Templier: semiconductor layer 105; para. 0071) on the active layer (Templier: 107). Templier in view of Yoon fails to explicitly teach a third semiconductor layer on the second semiconductor layer, and wherein the second semiconductor layer is a common layer connected in common to the light-emitting elements. However, Yoo teaches a third semiconductor layer (Yoo: fig. 8, GaN buffer layer 131a; para. 0069) on the second semiconductor layer (Yoo: n-type semiconductor layer 132; para. 0028, similar to 105 of Templier), and wherein the second semiconductor layer (Yoo: 132) is a common layer (Yoo: common layer on both LED cells 130; para. 0043) connected in common to the light-emitting elements (Yoo: LED cells 130; para. 0043, similar to LED of Templier). Yoo, Yoon and Templier are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add third semiconductor layer and the second semiconductor layer is a common layer as taught by Yoo. Doing so would realize third semiconductor layer and second semiconductor layer structure is very advantageous for flip-chip bonding of the micro-LED (Yoo: para. 0062). Regarding claim 4, Templier in view of Yoon and Yoo further teaches the display device of claim 3, wherein the first conductive patterns (Yoo: fig. 8, bonding connection member 270 and electrode pad 140; para. 0066, similar to 205, 255 and 113 of Templier) are between, and in contact with, the second semiconductor layer (Yoo: 132) and the common contact electrode (Yoo: electrodes 240; para. 0066, similar to 163 of Templier). Claims 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Li et al. (CN 109962094). Regarding claim 13, Yoo teaches a display device (micro-LED module; Abstract) comprising: a substrate (fig. 8, Si-based submount substrate 200; para. 0049) comprising a display area (middle area of trenches 101 for LED cells 130; para. 0043) and a non-display area (outer area 102; para. 0043); light-emitting elements (130) in the display area (middle area). Yoo fails to teach dummy patterns in the non-display area, adjacent to a first side of the substrate extending in a first direction, and having respective lengths in the first direction that gradually increase away from a center of the first side of the substrate along the first side. However, Li teaches dummy patterns (Li: fig. 6, isolation structure layer 181; para. 0080) in the non-display area (peripheral area PA; para. 0080), adjacent to a first side (left side) of the substrate (Li: substrate 110; para. 0080) extending in a first direction (Li: z-direction), and having respective lengths (Li: width W2, W1 of 181 respective in the middle region near AA and up PA region; para. 0110) in the first direction (Li: z-direction) that gradually increase (Li: W2 increase to W1) away from a center (Li: up PA region away from middle region near AA region) of the first side (left side) of the substrate along the first side (Li: z-direction). Li and Yoo are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add dummy patterns as taught by Li. Doing so would realize different size of LED grooves to improve the uneven evaporation rate of the light-emitting material droplets sprayed in the display area and thus improving the production qualification rate (Li: para. 0111). Regarding claim 14, Yoo in view of Li teaches the display device of claim 13, wherein the first side (Li: fig. 6, left side) of the substrate (Li: 110) is a long side (Li: left side is a long side of 110) of the substrate, and wherein the lengths of the dummy patterns (Li: w1, w2 of 181) extend along the long side (left side). Regarding claim 15, Yoo in view of Li teaches the display device of claim 14, wherein the dummy patterns (Li: fig. 6, 181) are further located along a second side (top side) extending in a second direction (Li: horizontal direction) crossing the first direction (Li: z-direction) of the first side (left side) of the substrate (Li: 110), the second side being a short side (Li: top side is shot side) of the substrate (Li: 110). Regarding claim 16, Yoo in view of Li teaches the display device of claim 13, wherein the light-emitting elements (Yoo: fig. 8, 130) comprise a first semiconductor layer (Yoo: p-type semiconductor layer 134; para. 0028), an active layer (Yoo: active layer 133; para. 0028) on the first semiconductor layer (Yoo: 134), a second semiconductor layer (Yoo: n-type semiconductor layer 132; para. 0028 on the active layer (Yoo: 133), and a third semiconductor layer (Yoo: GaN buffer layer 131a; para. 0069) on the second semiconductor layer (Yoo: 132), and wherein the display device (Yoo: micro-LED module) further comprises connecting electrodes (Yoo: bonding connection member 260; para. 0032) connected to the first semiconductor layer (Yoo: 151). Regarding claim 17, Yoo in view of Li teaches the display device of claim 16, wherein the dummy patterns (Li: fig. 6, 181) comprise a same material (Li: 181 has second electrode 172, 172 can be same material as first electrode 171; para. 0087, 0102, 0104) as the connecting electrodes (Li: 171, similar to 260 of Yoo). Response to Arguments Applicant’s arguments with respect to claims 1-10 and 13-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's arguments with respect to claims 11-12 filed on Dec. 5th, 2025 have been fully considered but they are not persuasive. With respect to pages 8-9 of applicant’s response of claim 11 is rejected under 35 U.S.C.102. Applicant submits "Templier does not appear to disclose the features now recited in claim 11. "a common connecting electrode on the common contact electrode, connected to the light-emitting elements, and at a same layer as the light-emitting elements." The examiner respectfully disagrees. As shown in fig. 2B of Templier, Templier teaches a common connecting electrode (113) on the common contact electrode (163), connected (electronically) to the light-emitting elements (LED of 107), and at a same layer (113 is at a same layer as LED of 107) as the light-emitting elements (LED of 107). As result, given a broadest reasonable interpretation, Templier teaches all limitations of claims 11. Details of rejections are discussed above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHIJUN XU/Examiner, Art Unit 2818 /BRIAN TURNER/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 08, 2022
Application Filed
Sep 04, 2025
Non-Final Rejection — §102, §103, §112
Nov 19, 2025
Applicant Interview (Telephonic)
Nov 19, 2025
Examiner Interview Summary
Dec 05, 2025
Response Filed
Mar 02, 2026
Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.9%)
3y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 56 resolved cases by this examiner. Grant probability derived from career allow rate.

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