Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Request for Continued Examination
The request filed on 3/4/26 for a Request for Continued Examination (RCE) under 37 CFR 1.114 is acceptable and an RCE has been established. An action on the RCE follows.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12, 33, 35 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sato et al. (U.S. Patent Publication No. 2011/0237066).
Referring to figures 1-7, Sato et al. teaches a method for forming a semiconductor device comprising:
forming a conductive feature (11/12/13) including a dielectric structure (11) and a conductive structure (12/13) disposed in the dielectric structure;
forming a first dielectric feature (20/22) over the conductive feature;
forming a trench structure (21) in the first dielectric feature to expose the conductive structure (11/12/13);
forming a conductive element (30/31) in the trench structure to be connected to the conductive structure (12/13), the conductive element including a first metal (copper seed) and a second metal (Mn) different from the first metal and distributed in the first metal (paragraph# 47, figure 4a); and
reacting the second metal of the conductive element with the first dielectric feature to form a barrier feature including silicide of second metal (see paragraphs# 47), wherein the second metal includes Al, Mn, Ti, Zr, Hf, Nb, Ta, Zn, V, Cr, Sc, Fe, or Y metal (paragraph# 47, figure 4a).
Regarding to claim 33, the first metal includes Cu, Ag, Au, Ni, Fe, Os, Re, Pt, Pd, Rh, Al, or a transition metal (see paragraphs# 47).
Regarding to claim 34, wherein the conductive element (30/31) includes a first portion disposed on the conductive structure (12/13) and a second portion disposed on the first dielectric feature (20); and a thickness of the first portion of the conductive element is greater than a thickness of the second portion of the conductive element.
Regarding to claim 35, the barrier feature (30) is formed between the conductive element and the first dielectric feature (20/22, see figure 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 15, 17, 20, 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (U.S. Patent Publication No. 2011/0237066) applied in claim(s) 12, 33, 35 above in view of Lin et al. (U.S. Patent Publication No. 2023/0402384).
Referring to figures 1-7, Sato et al. teaches a method for forming a semiconductor device comprising:
forming a conductive feature (11/12/13) including a dielectric structure (11) and a conductive structure (12/13) disposed in the dielectric structure;
forming a first dielectric feature (20/22) over the conductive feature;
forming a trench structure (21) in the first dielectric feature to expose the conductive structure (11/12/13);
forming a conductive element (30/31) in the trench structure to be connected to the conductive structure (12/13), the conductive element including a first metal (copper seed) and a second metal (Mn) different from the first metal and distributed in the first metal (paragraph# 47, figure 4a); and
reacting the second metal of the conductive element with the first dielectric feature to form a barrier feature including silicide of second metal (see paragraphs# 47), wherein the second metal includes Al, Mn, Ti, Zr, Hf, Nb, Ta, Zn, V, Cr, Sc, Fe, or Y metal (paragraph# 47, figure 4a).
However, the reference does not clearly teach forming a second dielectric feature over the first dielectric feature; forming a trench in the second dielectric feature to expose the conductive element; forming a barrier element in the trench; and filling the trench with a conductive layer (in claim 15), forming the barrier element, the barrier element cover the conductive element (in claim 17).
LIN et al. teaches forming a second dielectric feature (106b) over the first dielectric feature (106a); forming a trench in the second dielectric feature to expose the conductive element (see figure 1); forming a barrier element (107) in the trench; and filling the trench with a conductive layer (112, see figure 1, meeting claims 15, 17),
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form an interconnect in Sato et al. as taught by Lin et al. because forming the blocking layer to provide protection to the device, forming multilayer interconnect to provide multilevel interconnection device.
Regarding to claim 34, Sato et al. teaches the conductive element (30/31) includes a first portion disposed on the conductive structure (12/13) and a second portion disposed on the first dielectric feature (20). However, the reference does not teach the thickness of the first portion of the conductive element is greater than a thickness of the second portion of the conductive element.
It would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made to optimize the thickness of the first portion of the conductive element is greater than a thickness of the second portion of the conductive element, since it has been held that where the general conditions of a claim are disclosed in the prior art (i.e.- the thickness of the first portion of the conductive element and the second portion of the conductive element), discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the thickness of the first portion of the conductive element and the second portion of the conductive element) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the thickness of the first portion of the conductive element and the second portion of the conductive element with specific thickness in Sato et al. as taught by Lin et al. because forming the conductive portions with specific thickness is known in the semiconductor to form a desired interconnection.
Allowable Subject Matter
Claims 16, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the prior art teaches or suggests the step of selectively forming a blocking layer covering the conductive element, the barrier element being formed outside of the blocking layer and the conductive element; and removing the blocking layer after formation of the barrier element, in claim 16 and the trench structure includes a first trench portion and a second trench portion that is disposed over and connected to the first trench portion and that is wider than the first trench portion in forming the conductive element, the conductive element completely fills the first trench portion and partially fills the second trench portion; and the method further comprises forming a filling contact material to completely fill the second trench portion, in claim 20.
Claims 21-32 are allowed. None of the prior art teaches/suggests reacting the second metal of the conductive element with the first dielectric layer and the second dielectric layer so as to form a barrier feature between the conductive element and one of the first dielectric layer and the second dielectric layer (in claim 21); reacting the second metal of the conductive element with the first dielectric layer, the second dielectric layer, and the first etching stop layer so as to form a barrier feature between the conductive element and one of the first dielectric layer, the second dielectric layer, and the first etching stop layer (in claim 27).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893