DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 3, 2025 has been entered.
Response to Arguments
RE: the rejection of claim(s) 1-15, 21-25 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 8-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US20230053379A1 (“Choi”).
RE: Claim 1, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4), comprising:
parallel channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart from one another (FIG. 2A shows NS1 are spaced apart from one another);
a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members;
source/drain features (150, [0067]-[0068]) disposed besides the channel members and at opposite sides of the gate structure;
a silicide layer (combination of 155, 171, and 180a; 155 is a first silicide layer, [0109]; 171 includes TiSiN, [0128]; 180a includes TiSiN, [0138]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN is considered a silicide) disposed on the source/drain features, wherein the silicide layer includes a first silicide portion (combination of 155 and 171) interfacing with the source/drain features and a second silicide portion (180a) on the first silicide portion; and
a source/drain contact (combination of 172, 180b, [0110], [0137]) disposed on the silicide layer (FIG. 2A shows 172 is disposed on 155 and 171, and 180b is disposed on 155, 171, 180a), wherein the source/drain contact includes a first source/drain contact (172) in direct contact with the first silicide portion (FIG. 2A shows 172 is disposed on and in direct contact with the bottom surface and sidewalls of 171) and a second source/drain contact (180b) stacked on the first source/drain contact (FIG. 2A shows 180b is stacked on 172), and the second source/drain contact is in direct contact with a top surface of the second silicide portion (FIG. 2A shows 180b is disposed on and in direct contact with the top surface and sidewalls of 180a).
RE: Claim 3, Choi discloses The semiconductor device as claimed in claim 1, wherein a material of the source/drain contact comprises Co, Mo, Cu, Ru, W, or combinations thereof (Each of the source/drain filling layer 172 and/or the gate contact filling layer 177 may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), molybdenum (Mo), their combination, and/or the like, [0129]; Each of the first via filling layer 180 b and the second via filling layer 185 b may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), molybdenum (Mo), their combination, and/or the like, [0139]).
RE: Claim 4, Choi discloses The semiconductor device of claim 1, further comprising: a dielectric liner (For dependent claims 5 and 6: combination of 191, 156, and 195; Alternatively for dependent claim 8: 191; Alternatively for dependent claim 9: combination of 191, 156) disposed around the source/drain contact (191 is dielectric, [0104]; 156 is SiN, [0099]; 195 is SiN, [0132]; the instant application identifies SiN as dielectric, [0062]).
RE: Claim 5, Choi discloses The semiconductor device of claim 4, wherein the second silicide portion extends along a sidewall of the dielectric liner (FIG. 2A shows 180a extending along sidewall of 195).
RE: Claim 6, Choi discloses The semiconductor device of claim 4, wherein the second source/drain contact interfaces with the dielectric liner (FIG. 2A shows 180b interfacing with 195 through 180a; the word “interface” or “interfacing” is not defined in the instant application. Merriam-Webster’s dictionary defines the word “interface” as “to connect by means of an interface” (see definition 1 for the verb “interface” in Merriam-Webster’s dictionary available at https://www.merriam-webster.com/dictionary/interface, accessed on July 30, 2025). Accordingly, if a layer B is connected between a layer A and a layer C, under a broad reasonable interpretation, layer A is considered to interface with layer C since layer A would be connected to layer C by an interface between layer A and layer B).
RE: Claim 8, Choi discloses The semiconductor device of claim 4, further comprising an interlayer dielectric (ILD) layer (145 is SiN, [0092]; the instant application identifies SiN as dielectric, [0062]) and an etching stop layer (195, [0131]) and a contact opening (opening for 170, 180, 191) penetrating through the ILD layer and the etching stop layer (FIG. 2A shows the opening penetrating through 145, 195), wherein the dielectric liner (191) is located on sidewalls of the contact opening (FIG. 2A shows 191 is on sidewalls of the opening), and the ILD layer is interposed between the dielectric liner and the etching stop layer (FIG. 2A shows 145 is interposed between 191 and 195).
RE: Claim 9, Choi discloses The semiconductor device of claim 4, further comprising an interlayer dielectric (ILD) layer (145 is SiN, [0092]; the instant application identifies SiN as dielectric, [0062]) and an etching stop layer (195, [0131]) and a contact opening (opening for 170, 180, 191, 156) penetrating through the ILD layer and the etching stop layer (FIG. 2A shows the opening penetrating through 145, 195), wherein the dielectric liner (191, 156) is located on sidewalls of the contact opening and is in contact with the etching stop layer (FIG. 2A shows 191, 156 is on sidewalls of the opening and 156 is in contact with 195).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi.
RE: Claim 2, Choi does not explicitly disclose The semiconductor device as claimed in claim 1, wherein a material of the first source/drain contact is different from the second source/drain contact.
However, Choi discloses Each of the source/drain filling layer 172 and/or the gate contact filling layer 177 may include a conductive material. The conductive material may be (and/or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), their combination, and/or the like, [0129]. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for the source/drain filling layer 172.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use aluminum as the material of the source/drain filling layer 172 as this would have been obvious to try since aluminum is one solution for the material in a source/drain filling layer 172 identified by Choi and this would have had a reasonable expectation of success, see MPEP 2143.
Choi further discloses Each of the first via filling layer 180 b and the second via filling layer 185 b may include a conductive material. The conductive material may be (and/or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), their combination, and/or the like, [0139]. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for the via filling layer 180 b.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use tungsten as the material of the via filling layer 180 b of the source/drain via plug 180 as this would have been obvious to try since tungsten is one solution for the material in a via filling layer 180 b of the source/drain via plug 180 identified by Choi and this would have had a reasonable expectation of success, see MPEP 2143.
As a result, a material of the source/drain filling layer 172 would be different from the material of the of the via filling layer 180 b of the source/drain via plug 180.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1, further in view of US20210367054A1 (“Tzeng”).
RE: Claim 7, Choi does not explicitly disclose The semiconductor device of claim 1, wherein the first silicide portion has a composition different from that of the second silicide portion.
However, Choi discloses 155 is a silicide layer formed between the source/drain contact 170 and the first source/drain pattern 150, [0109].
Choi further discloses silicide 155 is a metal silicide layer, [0109].
In FIG. 2A, silicide layer 155 is formed between the source/drain pattern 150 and the barrier layer 171 of the source/drain contact 170, [0110].
In the same field of endeavor, Tzeng discloses in FIG. 22A: a silicide 104 having a first portion 104A between a source/drain region 82 and a source/drain contact 114, [0052], [0072].
Tzeng discloses the silicide 104 comprises the first portion 104A and a nitride portion, [0077].
Tzeng further discloses the silicide portion 104A is titanium silicide (TiSi), [0055].
Tzeng further discloses the nitride portion 104D is titanium silicon nitride, [0068].
Tzeng further discloses Because the silicides 104 were formed using conformal deposition processes, reduced source/drain contact resistance (Rcsd) can be achieved, [0072].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Tzeng in order to reduce the source/drain contact resistance.
As a result, Choi as modified by Tzeng discloses:
wherein the first silicide portion has a composition different from that of the second silicide portion (155 has a composition TiSi, and therefore the combination of 155, 171 includes or has the composition TiSi; 180a has the composition TiSiN as discussed for claim 1; TiSi is a different composition than TiSiN).
Claim 10-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Tzeng.
RE: Claim 10, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4, [0012]-[0015]), comprising:
a substrate (100);
channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart and arranged in parallel to a top surface of the substrate (FIG. 2A shows NS1 are spaced apart and arranged in parallel to a top surface of 100);
a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members;
source/drain features (150, [0067]-[0068]) disposed on the substrate, beside the channel members and beside the gate structure;
an interlayer dielectric (ILD) layer (192 is silicon oxide or silicon nitride, [0130]; the instant application identifies silicon oxide and silicon nitride as dielectric materials, [0017]; Accordingly, 192 is considered an interlayer dielectric layer) disposed on the source/drain features;
an etching stop layer (195, [0131]) lining a sidewall and a bottom surface of the ILD layer (FIG. 4 shows 195 lines a sidewall and bottom surface of 192; the sidewall of 192 is directly above the top of 171 in FIG. 4);
a contact opening (opening for 180, 170, 191, 155 in FIG. 2A) extending from a top surface of the ILD layer through the etching stop layer and into the source/drain features;
a liner (191, [0131]) disposed in the contact opening, extending along a sidewall of the contact opening and exposing a bottom of the contact opening (FIG. 2A shows 191 extends along a sidewall of the opening and exposes a bottom of the opening);
a first silicide layer (155; 155 is a first silicide layer, [0109]) disposed in the contact opening, on the bottom of the contact opening and in direct contact with the source/drain features;
a second silicide layer (171; 171 includes TiSiN, [0128]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN is considered a silicide) adjoined with the first silicide layer; and
a source/drain contact (172, [0110]) disposed in the contact opening and on the first and second silicide layers,
wherein a first portion of the source/drain contact (upper portion of 172) interfaces with the liner (FIG. 2A shows upper portion of 172 interfacing with 191 through 171; the word “interface” or “interfacing” is not defined in the instant application. Merriam-Webster’s dictionary defines the word “interface” as “to connect by means of an interface” (see definition 1 for the verb “interface” in Merriam-Webster’s dictionary available at https://www.merriam-webster.com/dictionary/interface, accessed on July 30, 2025). Accordingly, if a layer B is connected between a layer A and a layer C, under a broad reasonable interpretation, layer A is considered to interface with layer C since layer A would be connected to layer C by an interface between layer A and layer B), and a second portion of the source/drain contact (lower portion of 172) interfaces with the first and second silicide layers (FIG. 2A shows the lower portion of 172 interfaces with 171 and 155).
Choi does not explicitly disclose wherein the first silicide layer has a composition different from that of the second silicide layer.
However, Choi discloses 155 is a silicide layer formed between the source/drain contact 170 and the first source/drain pattern 150, [0109].
Choi further discloses silicide 155 is a metal silicide layer, [0109].
In FIG. 2A, silicide layer 155 is formed between the source/drain pattern 150 and the barrier layer 171 of the source/drain contact 170, [0110].
In the same field of endeavor, Tzeng discloses in FIG. 22A: a silicide 104 having a first portion 104A between a source/drain region 82 and a source/drain contact 114, [0052], [0072].
Tzeng discloses the silicide 104 comprises the first portion 104A and a nitride portion, [0077].
Tzeng further discloses the silicide portion 104A is titanium silicide (TiSi), [0055].
Tzeng further discloses the nitride portion 104D is titanium silicon nitride, [0068].
Tzeng further discloses the processing temperature during the conformal deposition process 102 is at least about 400° C. The relatively high processing temperature (e.g., at least about 400° C.) is also sufficiently high to cause the deposited, titanium layer to intermix with silicon molecules at exposed surfaces of the epitaxial source/drain regions 82, which forms a titanium silicide (e.g., first portion 104A) per the following reaction mechanism, [0055].
Tzeng further discloses Because the silicides 104 were formed using conformal deposition processes, reduced source/drain contact resistance (Rcsd) can be achieved, [0072].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Tzeng in order to reduce the source/drain contact resistance.
As a result, Choi as modified by Tzeng discloses:
wherein the first silicide layer has a composition different from that of the second silicide layer (155 has a composition TiSi; 171 has the composition TiSiN as discussed above; TiSi is a different composition than TiSiN).
RE: Claim 11, Choi in view of Tzeng discloses The semiconductor device of claim 10, wherein the first portion of the source/drain contact interfaces with a top surface of the second silicide layer (In Choi FIG. 2A shows upper portion of 172 interfaces with the top surface of 171 either indirectly through the lower portion of 172, or directly as inner surfaces of 171 are considered top surfaces which lie on top of bottom surfaces thereof).
RE: Claim 12, Choi in view of Tzeng discloses The semiconductor device of claim 10, wherein a width of the first portion of the source/drain contact is larger than or about the same as a width of the second portion of the source/drain contact (In Choi FIG. 2A shows a width of the upper portion of 172 is larger than a width of the lower portion of 172).
RE: Claim 13, Choi in view of Tzeng discloses The semiconductor device of claim 10, wherein a material of the liner includes a nitride material (In Choi 191 includes silicon nitride, [0104]), and the composition of the second silicide layer has a nitrogen content higher than that of the composition of the first silicide layer (As modified, 171 is TiSiN, 155 is TiSi; Accordingly, the composition of 171 has a nitrogen content higher than that of the composition of 155).
RE: Claim 15, Choi in view of Tzeng discloses The semiconductor device as claimed in claim 10, wherein a material of the source/drain contact comprises Co, Mo, Cu, Ru, W, or combinations thereof (In Choi Each of the source/drain filling layer 172 and/or the gate contact filling layer 177 may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), molybdenum (Mo), their combination, and/or the like, [0129]; Each of the first via filling layer 180 b and the second via filling layer 185 b may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), molybdenum (Mo), their combination, and/or the like, [0139]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Tzeng as applied to claim 10, further in view of US20180033646A1 (“Sharangpani”), and further in view of US 20210104397 A1 (“Jung”).
RE: Claim 14, Choi in view of Tzeng does not explicitly disclose The semiconductor device of claim 10, wherein the first silicide layer is a gradient silicide portion and a silicon content of the first silicide layer increases from the source/drain contact toward the source/drain features.
However, Choi discloses source/drain patterns 150 include semiconductor material, [0096] and semiconductor material includes silicon, [0049].
Further, Tzeng discloses the processing temperature during the conformal deposition process 102 is at least about 400° C. The relatively high processing temperature (e.g., at least about 400° C.) is also sufficiently high to cause the deposited, titanium layer to intermix with silicon molecules at exposed surfaces of the epitaxial source/drain regions 82, which forms a titanium silicide (e.g., first portion 104A), [0055].
In the same field of endeavor, Sharangpani discloses forming the metal silicide layer 474 by depositing a metallic element and inducing the silicidation of the deposited metallic element with at least a surface portion of the silicon-containing layer 472, [0160] and the first metallic element can be deposited as a thin metal layer, and a subsequently anneal process can be performed to form the metal silicide layer 474 by reacting the metallic layer with the silicon-containing layer, [0160].
Sharangpani further discloses Due to the diffusion of the various elements from, and into, the metal nitride layer 46A and from, and into, the metal portion {46B, (476, 478), 488}, the metal silicide layer (471, 474) can have a gradient in atomic concentration of silicon such that the atomic concentration of silicon increases with distance from an interface between the metal silicide layer (471, 474) and the metal portion {46B, (476, 478), 488}, [0234].
Accordingly, it is considered inherent that in Choi as modified by Tzeng, during the formation of silicide layer 155, the metal in the deposited titanium layer would mix and diffuse into the silicon of the source/drain regions 150 at the high processing temperature so that the silicon content increases toward the silicon of the source/drain regions 150, decreases away from the source/drain regions, and therefore would increase from the source/drain contact 172 toward the source/drain regions 150.
Alternatively, in a same field of endeavor, Jung teaches a gradient in Si concentration is created in the seed layer such that the bottom interface region near the substrate has a Si concentration that is higher than the average Si concentration, [0068] and that When the seed layer is formed to have such a Si concentration gradient, the bottom interface region, which may be more silicon-rich compared to upper regions of the seed layers, may reduce the contact resistance, [0068].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a Si concentration gradient in the silicide layer 155 so that a bottom portion thereof is more silicon rich compared to an upper portion thereof as taught by Jung in order to reduce the contact resistance.
Claim 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Tzeng.
RE: Claim 21, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4), comprising:
parallel channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart from one another (FIG. 2A shows NS1 are spaced apart from one another);
a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members;
source/drain features (150, [0067]-[0068]) disposed besides the channel members and at opposite sides of the gate structure;
a first silicide layer (combination of 155, 171; 155 is a first silicide layer, [0109]; 171 includes TiSiN, [0128]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN is considered a silicide) disposed on and in direct contact with the source/drain features;
a second silicide layer (180a; 180a includes TiSiN, [0138]) adjoined with the first silicide layer (the term “adjoin” is not defined in the instant specification; the term “adjoin” is defined as “to lie next to or in contact with,” see definition 2 by Merriam-Webster at https://www.merriam-webster.com/dictionary/adjoin, accessed March 12, 2026; Accordingly, FIG. 2A shows 180a is adjoined with 171 which is adjoined with 155 as these layers are all next to or in contact with each other); and
a source/drain contact (combination of 172, 180b, [0110], [0137]) disposed on the first and second silicide layers (FIG. 2A shows 172 is disposed on 155 and 171, and 180b is disposed on 155, 171, 180a), wherein the source/drain contact includes a first source/drain contact (172) and a second source/drain contact (180b) stacked on the first source/drain contact, the first source/drain contact is in direct contact with the first silicide layer (FIG. 2A shows 172 is in direct contact with 171), and the second source/drain contact is in direct contact with a top surface of the second silicide layer (FIG. 2A shows 180b is in direct contact with a top surface of 180a).
Choi does not explicitly disclose wherein the first silicide layer has a composition different from that of the second silicide layer.
However, Choi discloses 155 is a silicide layer formed between the source/drain contact 170 and the first source/drain pattern 150, [0109].
Choi further discloses silicide 155 is a metal silicide layer, [0109].
In FIG. 2A, silicide layer 155 is formed between the source/drain pattern 150 and the barrier layer 171 of the source/drain contact 170, [0110].
In the same field of endeavor, Tzeng discloses in FIG. 22A: a silicide 104 having a first portion 104A between a source/drain region 82 and a source/drain contact 114, [0052], [0072].
Tzeng discloses the silicide 104 comprises the first portion 104A and a nitride portion, [0077].
Tzeng further discloses the silicide portion 104A is titanium silicide (TiSi), [0055].
Tzeng further discloses the nitride portion 104D is titanium silicon nitride, [0068].
Tzeng further discloses Because the silicides 104 were formed using conformal deposition processes, reduced source/drain contact resistance (Rcsd) can be achieved, [0072].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Tzeng in order to reduce the source/drain contact resistance.
As a result, Choi as modified by Tzeng discloses:
wherein the first silicide layer has a composition different from that of the second silicide layer (155 has the composition TiSi, 180a has the composition TiSiN; Accordingly, the combination 155, 171 includes and therefore has a composition TiSi that is different from the composition of 180a which is TiSiN).
RE: Claim 22, Choi in view of Tzeng does not explicitly disclose The semiconductor device of claim 21, wherein a material of the first source/drain contact is different from the second source/drain contact.
However, Choi discloses Each of the source/drain filling layer 172 and/or the gate contact filling layer 177 may include a conductive material. The conductive material may be (and/or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), their combination, and/or the like, [0129]. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for the source/drain filling layer 172.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use aluminum as the material of the source/drain filling layer 172 as this would have been obvious to try since aluminum is one solution for the material in a source/drain filling layer 172 identified by Choi and this would have had a reasonable expectation of success, see MPEP 2143.
Choi further discloses Each of the first via filling layer 180 b and the second via filling layer 185 b may include a conductive material. The conductive material may be (and/or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), their combination, and/or the like, [0139]. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for the via filling layer 180 b.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use tungsten as the material of the via filling layer 180 b of the source/drain via plug 180 as this would have been obvious to try since tungsten is one solution for the material in a via filling layer 180 b of the source/drain via plug 180 identified by Choi and this would have had a reasonable expectation of success, see MPEP 2143.
As a result, a material of the source/drain filling layer 172 would be different from the material of the of the via filling layer 180 b of the source/drain via plug 180.
RE: Claim 23, Choi in view of Tzeng discloses The semiconductor device of claim 21, further comprising: a dielectric liner (In Choi: 191; 191 is silicon nitride (SiN), [0104]; the instant application identifies SiN as dielectric, [0062]) disposed around the source/drain contact.
RE: Claim 24, Choi in view of Tzeng discloses The semiconductor device of claim 23, wherein the second silicide layer is disposed on the dielectric liner (In Choi FIG. 2A shows 180a is disposed on 191).
RE: Claim 25, Choi in view of Tzeng discloses The semiconductor device of claim 23, wherein a material of the dielectric liner includes a nitride material (As modified, a material of 191 is silicon nitride (SiN)), and the composition of the second silicide layer has a nitrogen content higher than that of the composition of the first silicide layer (As modified for claim 21, 155 has the composition TiSi, 180a has the composition TiSiN; therefore, the composition of 180a TiSiN has a nitrogen content higher than the composition TiSi in 155).
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899