Prosecution Insights
Last updated: October 02, 2026
Application No. 17/885,577

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Aug 11, 2022
Examiner
ANGUIANO, MICHAEL
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
4 (Final)
52%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 52% of resolved cases
52%
Career Allowance Rate
14 granted / 27 resolved
-16.1% vs TC avg
Strong +20% interview lift
Without
With
+19.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
33 currently pending
Career history
78
Total Applications
across all art units

Statute-Specific Performance

§103
69.3%
+29.3% vs TC avg
§102
6.9%
-33.1% vs TC avg
§112
23.5%
-16.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 27 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments RE: the rejection of the claims under 35 USC 102 and 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable US20230053379A1 (“Choi”) in view of US20190311969A1 (“Liaw”). RE: Claim 1, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4), comprising: channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart from one another; a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members; source/drain features (150, [0067]-[0068]) disposed besides the channel members and at opposite sides of the gate structure; a silicide layer (combination of 155 and 171, [0109], [0128]; 155 is a first silicide layer, [0109]; 171 is TiSiN, [0128]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN 171 is considered a silicide) disposed on the source/drain features, wherein the silicide layer includes a first silicide portion (155) interfacing with the source/drain features and a second silicide portion (171) on the first silicide portion; and a source/drain contact (combination of 172 and 180, [0110], [0134]) disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact (172) and a second source/drain contact (180) stacked on and in direct contact with the first source/drain contact (FIG. 2A shows 180 is stacked on and in direct contact with the first source/drain contact 172), and the second source/drain contact is in direct contact with a top surface of the second silicide portion (FIG. 2A shows the second source/drain contact 180 is in direct contact with a top surface of the second silicide portion 171). Choi does not explicitly disclose: the first source/drain contact is in direct contact with the first silicide portion. However, Choi discloses 171 is a source/drain barrier layer, [0128]. In the same field of endeavor, Liaw discloses in FIG. 5: a first source/drain contact (160, [0061]) is in direct contact with a first silicide layer (300, [0071]). In FIG. 5, the barrier layer 280 exposes a bottom portion of the contact plug 160 to the silicide portion 300 so that the contact plug 160 is in direct contact with the silicide portion 300, [0061]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the barrier layer/second silicide portion 171 so that the first source/drain contact 172 is in direct contact with the first silicide portion 155 as taught by Liaw in order to make a more direct connection between the first source/drain contact 172 and the first silicide portion 155, thereby reducing the resistance between them. RE: Claim 2, Choi in view of Liaw discloses The semiconductor device as claimed in claim 1, wherein a material of the first source/drain contact is different from the second source/drain contact (Choi discloses a material of 172 is copper, [0129]; a material of 180b, which is part of 180, is ruthenium, [0138]; Accordingly, a material of 172 is different from that of 180), and a contact interface between the first source/drain contact and the second source/drain contact is a concave surface (FIG. 2A shows the contact interface between 172 and 180 is concave toward 180; Further, Choi teaches the boundary between the source/drain via plug 180 and the source/drain contact 170, the upper surface 170_US of the source/drain contact may include a concave curved portion 170_USX, [0160]; FIG. 13 shows the contact interface between the first source/drain contact 172 and the second source/drain contact 180 is a concave surface toward 170). RE: Claim 3, Choi in view of Liaw discloses The semiconductor device as claimed in claim 1, wherein a material of the source/drain contact comprises Co, Mo, Cu, Ru, W, or combinations thereof (Choi discloses a material of 172 includes copper, [0129]). RE: Claim 4, Choi in view of Liaw discloses The semiconductor device of claim 1, further comprising: a dielectric liner (From Choi FIG. 2A: 191; 191 is dielectric, [0104]) disposed around the source/drain contact. RE: Claim 5, Choi in view of Liaw discloses The semiconductor device of claim 4, wherein the second silicide portion extends along a sidewall of the dielectric liner (From Choi FIG. 2A: the second silicide portion 171 extends along a sidewall of the dielectric liner 191). RE: Claim 6, Choi in view of Liaw discloses The semiconductor device of claim 4, wherein the second source/drain contact interfaces with the dielectric liner (From Choi FIG. 2A: the second source/drain contact 180 interfaces with the dielectric liner 191 through 170; the word “interface” or “interfacing” is not defined in the instant application. Merriam-Webster’s dictionary defines the word “interface” as “to connect by means of an interface” (see definition 1 for the verb “interface” in Merriam-Webster’s dictionary available at https://www.merriam-webster.com/dictionary/interface, accessed on July 30, 2025). Accordingly, if a layer B is connected between a layer A and a layer C, under a broad reasonable interpretation, layer A is considered to interface with layer C since layer A would be connected to layer C by an interface between layer A and layer B). RE: Claim 7, Choi in view of Liaw discloses The semiconductor device of claim 1, wherein the first silicide portion has a composition different from that of the second silicide portion (In Liaw FIG. 5, a contact plug 160 is in direct contact with silicide portion 300, which is in direct contact with source/drain region 294, [0071]. Liaw discloses the silicide regions 300 include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide, [0071]. Accordingly before the effective filing date of the claimed invention, there was a need to select a silicide material for silicide layer 155 in Choi. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Liaw as this would have been obvious to try since titanium silicide is one solution for a silicide layer on a source/drain region identified by Liaw, and this would have had a reasonable expectation of success, see MPEP 2143. Choi teaches 171 is TiSiN, [0128]. As a result, the first silicide portion 155 would have a composition different from that of the second silicide portion 171). RE: Claim 8, Choi in view of Liaw discloses The semiconductor device of claim 4, further comprising an interlayer dielectric (ILD) layer (In Choi: 145 is SiN, [0092]; the instant application identifies SiN as dielectric, [0062]) and an etching stop layer (195, [0131]) and a contact opening (opening for 170, 180, 191) penetrating through the ILD layer and the etching stop layer (FIG. 2A shows the opening penetrating through 145, 195), wherein the dielectric liner is located on sidewalls of the contact opening (FIG. 2A shows 191 is on sidewalls of the opening), and the ILD layer is interposed between the dielectric liner and the etching stop layer (FIG. 2A shows 145 is interposed between 191 and 195). RE: Claim 9, Choi in view of Liaw discloses The semiconductor device of claim 4, further comprising an interlayer dielectric (ILD) layer (In Choi: 145 is SiN, [0092]; the instant application identifies SiN as dielectric, [0062]) and an etching stop layer (156, [0099]) and a contact opening (opening for 170, 180, 191) penetrating through the ILD layer and the etching stop layer (FIG. 2A shows the opening penetrating through 145, 156), wherein the dielectric liner is located on side walls of the contact opening and is in contact with the etching stop layer (FIG. 2A shows 191 is located on side walls of the opening and is in contact with the etching stop layer 156). Claim(s) 10-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of US20230402507A1 (“Galatage”), further in view of Liaw. RE: Claim 10, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4, [0012]-[0015]), comprising: a substrate (100); channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart and arranged over a top surface of the substrate; a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members; source/drain features (150, [0067]-[0068]) disposed on the substrate, beside the channel members and beside the gate structure; an interlayer dielectric (ILD) layer (192 is silicon oxide or silicon nitride, [0130]; the instant application identifies silicon oxide and silicon nitride as dielectric materials, [0017]; Accordingly, 192 is considered an interlayer dielectric layer) disposed on the source/drain features; an etching stop layer (195, [0131]) lining a sidewall and a bottom surface of the ILD layer (FIG. 4 shows 195 lines a sidewall and bottom surface of 192; the sidewall of 192 is directly above the top of 171 in FIG. 4); a contact opening (opening for 180, 170, 191, 155 in FIG. 2A) extending from a top surface of the ILD layer through the etching stop layer and into the source/drain features; a first silicide layer (155, [0109]) disposed in the contact opening, on the bottom of the contact opening and in direct contact with the source/drain features; a second silicide layer (171; 171 is TiSiN, [0128]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN 171 is considered a silicide) adjoined with the first silicide layer; and a source/drain contact (combination of 172 and 180, [0110], [0134]) disposed in the contact opening and on the first and second silicide layers, wherein a second portion (172) of the source/drain contact interfaces with the first and second silicide layers. Choi does not explicitly disclose: a liner disposed in the contact opening, extending along a sidewall of the contact opening and exposing a bottom of the contact opening; wherein a first portion of the source/drain contact is in direct contact with the liner; wherein the first silicide layer has a composition different from that of the second silicide layer. However, in a similar field of endeavor, Galatage discloses in FIG. 1A: a liner (102, [0075]) disposed in a contact opening (opening for 102, 118a, 118c), extending along a sidewall of the contact opening and exposing a bottom of the contact opening (FIG. 1A shows the liner exposing the bottom of the contact opening for 102, 118a, 118c); wherein a first portion of a source/drain contact (118a) is in direct contact with the liner (FIG. 1A shows an upper source/drain contact 118a stacked on a lower source/drain contact 118c, where the upper source/drain contact 118a is in direct contact with the liner 102). Galatage discloses the liner 102 protects the dielectric material 117, [0077]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner in contact with a first portion 180 of the source/drain contact as taught by Galatage in order to protect the insulating layer 192. In the same field of endeavor, Liaw discloses in FIG. 5, a contact plug 160 is in direct contact with silicide portion 300, which is in direct contact with source/drain region 294, [0071]. Liaw discloses the silicide regions 300 include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide, [0071]. Accordingly before the effective filing date of the claimed invention, there was a need to select a silicide material for silicide layer 155 in Choi. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Liaw as this would have been obvious to try since titanium silicide is one solution for a silicide layer on a source/drain region identified by Liaw, and this would have had a reasonable expectation of success, see MPEP 2143. Choi teaches 171 is TiSiN, [0128]. As a result, the first silicide layer 155 would have a composition different from that of the second silicide layer 171. RE: Claim 11, Choi in view of Galatage, Liaw discloses The semiconductor device of claim 10, wherein the first portion of the source/drain contact (180) interfaces with a top surface of the second silicide layer (Choi FIG. 2A shows 180 interfaces with a top surface of the second silicide layer 171). RE: Claim 12, Choi in view of Galatage, Liaw discloses The semiconductor device of claim 10, wherein a width of the first portion of the source/drain contact is larger than or about the same as a width of the second portion of the source/drain contact (Choi FIG. 2A shows a width of the first portion 180 of the source/drain contact is larger than a width of the second portion 172 of the source/drain contact). RE: Claim 13, Choi in view of Galatage, Liaw discloses The semiconductor device of claim 10, wherein a material of the liner includes a nitride material (Galatage discloses the liner 102 includes silicon nitride, [0077]), and the composition of the second silicide layer has a nitrogen content higher than that of the composition of the first silicide layer (As modified, 171 is TiSiN, 155 is TiSi; Accordingly, the composition of 171 has a nitrogen content higher than that of the composition of 155). RE: Claim 15, Choi in view of Galatage, Liaw discloses The semiconductor device as claimed in claim 10, wherein a material of the source/drain contact comprises Co, Mo, Cu, Ru, W, or combinations thereof (In Choi Each of the source/drain filling layer 172 and/or the gate contact filling layer 177 may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), molybdenum (Mo), their combination, and/or the like, [0129]; Each of the first via filling layer 180 b and the second via filling layer 185 b may include a conductive material. The conductive material may be (and/or include) at least one of, for example, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), molybdenum (Mo), their combination, and/or the like, [0139]. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Galatage, Liaw as applied to claim 10, further in view of US20210367054A1 (“Tzeng”), further in view of US20180033646A1 (“Sharangpani”), and further in view of US 20210104397 A1 (“Jung”). RE: Claim 14, Choi in view of Galatage, Liaw does not explicitly disclose The semiconductor device of claim 10, wherein the first silicide layer is a gradient silicide portion and a silicon content of the first silicide layer increases from the source/drain contact toward the source/drain features. In the same field of endeavor, Tzeng discloses in FIG. 22A: a silicide 104 having a first portion 104A between a source/drain region 82 and a source/drain contact 114, [0052], [0072]. Tzeng discloses the silicide 104 comprises the first portion 104A and a nitride portion, [0077]. Tzeng further discloses the silicide portion 104A is titanium silicide (TiSi), [0055]. Tzeng further discloses the nitride portion 104D is titanium silicon nitride, [0068]. Tzeng further discloses the processing temperature during the conformal deposition process 102 is at least about 400° C. The relatively high processing temperature (e.g., at least about 400° C.) is also sufficiently high to cause the deposited, titanium layer to intermix with silicon molecules at exposed surfaces of the epitaxial source/drain regions 82, which forms a titanium silicide (e.g., first portion 104A) per the following reaction mechanism, [0055]. Tzeng further discloses Because the silicides 104 were formed using conformal deposition processes, reduced source/drain contact resistance (Rcsd) can be achieved, [0072]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form 155 as a titanium silicide (TiSi) as taught by Tzeng in order to reduce the source/drain contact resistance. In the same field of endeavor, Sharangpani discloses forming the metal silicide layer 474 by depositing a metallic element and inducing the silicidation of the deposited metallic element with at least a surface portion of the silicon-containing layer 472, [0160] and the first metallic element can be deposited as a thin metal layer, and a subsequently anneal process can be performed to form the metal silicide layer 474 by reacting the metallic layer with the silicon-containing layer, [0160]. Sharangpani further discloses Due to the diffusion of the various elements from, and into, the metal nitride layer 46A and from, and into, the metal portion {46B, (476, 478), 488}, the metal silicide layer (471, 474) can have a gradient in atomic concentration of silicon such that the atomic concentration of silicon increases with distance from an interface between the metal silicide layer (471, 474) and the metal portion {46B, (476, 478), 488}, [0234]. Accordingly, it is considered inherent that in Choi as modified by Tzeng, during the formation of silicide layer 155, the metal in the deposited titanium layer would mix and diffuse into the silicon of the source/drain regions 150 at the high processing temperature so that the silicon content increases toward the silicon of the source/drain regions 150, decreases away from the source/drain regions, and therefore would increase from the source/drain contact 172 toward the source/drain regions 150. Alternatively, in a same field of endeavor, Jung teaches a gradient in Si concentration is created in the seed layer such that the bottom interface region near the substrate has a Si concentration that is higher than the average Si concentration, [0068] and that When the seed layer is formed to have such a Si concentration gradient, the bottom interface region, which may be more silicon-rich compared to upper regions of the seed layers, may reduce the contact resistance, [0068]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a Si concentration gradient in the silicide layer 155 so that a bottom portion thereof is more silicon rich compared to an upper portion thereof as taught by Jung in order to reduce the contact resistance. Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Liaw. RE: Claim 21, Choi discloses A semiconductor device (semiconductor device in FIGs. 1-4), comprising: parallel channel members (NS1 in FIG. 2A; The first active pattern AP1 and the second active pattern AP2 may be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1, [0042]) spaced apart from one another; a gate structure (GS_INT is a gate structure, [0063], [0070]) wrapping around the channel members; source/drain features (150, [0067]-[0068]) disposed besides the channel members and at opposite sides of the gate structure; a first silicide layer (155; 155 is a first silicide layer, [0109]) disposed on and in direct contact with the source/drain features; a second silicide layer (171; 171 is TiSiN, [0128]; the instant application identifies TiSiN as a silicide, [0038]; Accordingly, TiSiN 171 is considered a silicide) adjoined with the first silicide layer, a source/drain contact (combination of 172 and 180, [0110], [0134]) disposed on the first and second silicide layers, wherein the source/drain contact includes a first source/drain contact (172) and a second source/drain contact (180) stacked on and in direct contact with the first source/drain contact (FIG. 2A shows 180 is stacked on and in direct contact with the first source/drain contact 172), and the second source/drain contact is in direct contact with a top surface of the second silicide layer (FIG. 2A shows the second source/drain contact 180 is in direct contact with a top surface of the second silicide portion 171). Choi does not explicitly disclose: wherein the first silicide layer has a composition different from that of the second silicide layer the first source/drain contact is in direct contact with the first silicide layer. In the same field of endeavor, Liaw discloses in FIG. 5, a silicide portion 300, which is in direct contact with source/drain region 294, [0071]. Liaw discloses the silicide regions 300 include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide, [0071]. Accordingly before the effective filing date of the claimed invention, there was a need to select a silicide material for silicide layer 155 in Choi, which is in direct contact with source/drain regions 150. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use titanium silicide (TiSi) as the material of the silicide layer 155 as taught by Liaw as this would have been obvious to try since titanium silicide is one solution for a silicide layer on a source/drain region identified by Liaw, and this would have had a reasonable expectation of success, see MPEP 2143. Choi teaches 171 is TiSiN, [0128]. As a result, the first silicide layer 155 would have a composition different from that of the second silicide layer 171. Further, Choi discloses 171 is a source/drain barrier layer, [0128]. Further, Liaw discloses in FIG. 5: a first source/drain contact (160, [0061]) is in direct contact with a first silicide layer (300, [0071]). In FIG. 5, the barrier layer 280 exposes a bottom portion of the contact plug 160 to the silicide portion 300 so that the contact plug 160 is in direct contact with the silicide portion 300, [0061]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the barrier layer/second silicide portion 171 so that the first source/drain contact 172 is in direct contact with the first silicide portion 155 as taught by Liaw in order to make a more direct connection between the first source/drain contact 172 and the first silicide portion 155, thereby reducing the resistance between them. RE: Claim 22, Choi in view of Liaw discloses The semiconductor device of claim 21, wherein a material of the first source/drain contact is different from the second source/drain contact (Choi discloses a material of 172 is copper, [0129]; a material of 180b, which is part of 180, is ruthenium, [0138]; Accordingly, a material of 172 is different from that of 180). RE: Claim 23, Choi in view of Liaw discloses The semiconductor device of claim 21, further comprising: a dielectric liner (From Choi FIG. 2A: 191; 191 is dielectric, [0104]) disposed around the source/drain contact. RE: Claim 24, Choi in view of Liaw discloses The semiconductor device of claim 23, wherein the second silicide layer is disposed on the dielectric liner (Choi FIG. 2A shows 171 is disposed on 191). RE: Claim 25, Choi in view of Liaw discloses The semiconductor device of claim 23, wherein a material of the dielectric liner includes a nitride material (Choi discloses 191 includes silicon nitride, [0104]), and the composition of the second silicide layer has a nitrogen content higher than that of the composition of the first silicide layer (As modified, 171 is TiSiN, 155 is TiSi; Accordingly, the composition of 171 has a nitrogen content higher than that of the composition of 155). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL ANGUIANO/Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Show 7 earlier events
Sep 01, 2025
Interview Requested
Sep 10, 2025
Applicant Interview (Telephonic)
Sep 11, 2025
Examiner Interview Summary
Nov 03, 2025
Request for Continued Examination
Nov 11, 2025
Response after Non-Final Action
Mar 19, 2026
Non-Final Rejection mailed — §103
Jun 18, 2026
Response Filed
Aug 11, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
52%
Grant Probability
72%
With Interview (+19.9%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
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