Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The response of 12/8/2025 has been received, entered and given careful consideration. Rejections of the previous action which are not repeated below are withdrawn based upon the amendments and arguments of the applicant. Responses to the arguments of the applicant are presented after the first rejection they are directed to.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. 10990023 and Ho et al. 9786569, in view of Elazhary et al. WO 2021073854 .
Hsieh et al. 10990023 illustrates in figures 5A and 5D, a substrate with two different overlay measurement patterns (208,206) associated with different layers of the device/substrate (200). the reference pattern module 550 placed over the substrate 232. As shown, the reference pattern 502A is shifted by a shift distance 302A, e.g., an overlay error, in the negative X-direction with respect to the overlay measurement pattern 208 of the substrate 232 and thus the shift distance 302A is a negative distance. In addition, the reference pattern 502B is shifted by a shift distance 302B, e.g., an overlay error, in the positive X-direction with respect to the overlay measurement pattern 206 of the substrate 232 and thus the shift distance 302B is a positive distance. Thus, the total overlay shift distance (total overlay error) between the overlay measurement patterns 206 and 208 is the difference between the distances 302A and 302B and because the distances 302A and 302B have different polarity the values add to each other (8/60-11/24). In some embodiments, the first layer is covered with a second layer and a second layout pattern that includes a second overlay measurement pattern is created in the second layer. The second layer is initially covered with a resist material layer and the second layout pattern that includes the second overlay measurement pattern is imaged onto the resist material layer on top of the second layer. Therefore, the second overlay measurement pattern is in the resist material layer and the resist material layer is on top of the second layer that is on top of the first layer, which includes the first overlay measurement pattern. In some other embodiments, the second layer does not exist and the first layer is covered with the resist material layer and the second layout pattern that includes the second overlay measurement pattern is imaged onto the resist material layer that is directly on top of the first layer. Therefore, the second overlay measurement pattern is in the resist material layer and the resist material layer is on top of the first layer, which includes the first overlay measurement pattern. In either case, after the resist material is developed, if the first overlay measurement pattern of the first layer and the second overlay measurement pattern of the resist material layer on top of the first layer overlap, the overlay error between the first layout pattern and the second layout pattern may be measured. In some embodiments, when the overlay error is below a threshold, the developed resist material that includes the second layout pattern is used in the next processing step. Otherwise, the resist material is removed and a new resist layout pattern is formed with corrected alignment in lithography process (3/6-39)
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The measurement is described more fully in the text associated with figures 6A-6B. FIGS. 6A and 6B illustrate measurement systems for determining an overlay error in accordance with some embodiments of the disclosure. FIG. 6A shows a substrate 602, which is consistent with the substrate 232 of FIG. 5A. The substrate 602 is mounted on a stage 551, and the stage 551 is coupled to and controlled by a stage controller 560. The reference pattern module 550 is also mounted on top of and over the surface of the substrate 602 and in parallel with the stage 551. In some embodiments, the layout generator-controller 520 moves the reference patterns 502A and 502B to specific locations, e.g., by turning on/off the TFT transistors, and/or the stage controller 560 moves the substrate 602 such that the reference patterns 502A and 502B generated by the layout generator-controller 520 overlap, e.g., at least partially overlap, with the overlay measurement patterns 206 and 208 of the substrate 602. In some embodiments, the reference pattern 502A overlaps with the overlay measurement pattern 208 of the first layer 204 and the reference pattern 502B overlaps with the overlay measurement pattern 206 of the resist material layer 203. By measuring a relative position between the overlay measurement pattern 208 and the reference pattern 502A and a relative position between the overlay measurement pattern 206 and the reference pattern 502B, it is possible to measure an overlay error between the overlay measurement pattern 206 and the overlay measurement pattern 208 because the distance (e.g., center-to-center distance) between the reference pattern 502A and the reference pattern 502B is known or predetermined. In some embodiments as shown in FIG. 6A, one of the light sources of the optical system 220 transmits an incident light beam 514 to the overlay measurement patterns 208 and the reference pattern 502A that at least have an overlap in the X-direction. In some embodiments, the overlay measurement pattern 208 and the reference pattern 502A have a same pitch. A portion of the incident light beam 514 is diffracted and reflected from the reference pattern 502A and produces the negative and positive first order diffractions that are inner portions of first order diffractions 542 and 546 respectively. A remaining portion of the incident light beam 514 passes through the reference pattern 502A and is diffracted and reflected from the overlay measurement pattern 208 and produces the negative and positive first order diffractions that are outer portions of first order diffractions 542 and 546 respectively. The negative and positive first order diffractions 542 and 546 that are reflected are detected by the detector 222 of the optical system 220. FIG. 6A also shows the analyzer module 230 that is coupled to the optical system 220. The analyzer module 230 receives corresponding signals of the detected first order diffractions 542 and 546 and performs an analysis on the corresponding signals to determine a first drift, e.g., a first overlay error, between the overlay measurement pattern 208 and the reference pattern 502A. As described, in some embodiments, the wavelength of the light beam 514 is comparable with the pitch of the reference pattern 502A and the overlay measurement patterns 208. Also, in some embodiments, the wavelength of the light beam 515 is comparable with the pitch of the reference pattern 502B and the overlay measurement patterns 206. Thus, when the overlay measurement patterns 208 and 206 have different pitches, two different light sources of the optical system 220 having different wavelengths are used to produce the light beams 514 and 515. In some embodiments, when the overlay measurement patterns 208 and 206 have the same pitch, the same light source or two different light sources of the optical system 220 may be used to produce the light beams 514 and 515. In addition, as shown in FIG. 6A, one of the light sources of the optical system 220 transmits an incident light beam 515 to the overlay measurement patterns 206 and the reference pattern 502B that at least have an overlap in the X-direction. In some embodiments, the overlay measurement pattern 206 and the reference pattern 502B have a same pitch that is not the same as the pitches of the overlay measurement pattern 208 and the reference pattern 502A. A portion of the incident light beam 515 is diffracted and reflected from the reference pattern 502B and produces the negative and positive first order diffractions that are inner portions of first order diffractions 544 and 548 respectively. A remaining portion of the incident light beam 515 passes through the reference pattern 502B and gets diffracted and reflected from the overlay measurement pattern 206 and produces the negative and positive first order diffractions that are outer portions of first order diffractions 544 and 548 respectively. The negative and positive first order diffractions 544 and 548 that are reflected are detected by the detector 222 of the optical system 220. The analyzer module 230 receives corresponding signals of the detected first order diffractions 544 and 548 and performs an analysis on the corresponding signals to determine a second drift, e.g., a second overlay error, between the overlay measurement pattern 206 and the reference pattern 502B. As described, a wavelength of the light beam irradiating the overlapped reference pattern 502B and the overlay measurement pattern 206 and a wavelength of the light beam irradiating the overlapped reference pattern 502A and the overlay measurement pattern 208 may be comparable to the pitches of the overlay measurement patterns 206 and 208. In some embodiments, the layout generator-controller 520 has the information of the reference patterns 502A and 502B including a distance between the generated reference patterns 502A and 502B. In some embodiments, the overlap between the overlay measurement patterns 208 and the reference pattern 502A is concurrent with the overlap between the overlay measurement pattern 206 and the reference pattern 502B. In some embodiments, the distance between the generated reference patterns 502A and 502B is the expected distance between the overlay measurement patterns 206 and 208. Thus, the analyzer module 230 may determine the overlay error between the overlay measurement patterns 206 and 208 based on the first and second overlay errors. In some embodiments, the overlap between the overlay measurement pattern 208 and the reference pattern 502A is not concurrent with the overlap between the overlay measurement pattern 206 and the reference pattern 502B. In addition, the analyzer module 230 receives the distance between the generated reference patterns 502A and 502B from the layout generator-controller 520 and also receives the stage 551 movement from the stage controller 560, and receives the location of the reference pattern module 550 from the layout generator-controller 520. Thus, the analyzer module 230 may determine the total overlay error between overlay measurement patterns 206 and 208 based on the first and second overlay errors, the distance between the reference patterns 502A and 502B, and the movement distances of the reference pattern module 550 and the stage 551. Thus, in some embodiments, the reference patterns 502A and 502B of the reference pattern module 550 are generated on the fly and the width and pitch of the reference patterns 502A and 502B are selected based on the width and pitch of the overlay measurement patterns 206 and 208. In some embodiments, the pitch of the reference patterns 502A and 502B are adjusted to increase the diffracted signals that are detected by the detectors. In some embodiments, the pitch of the reference patterns 502A and 502B are adjusted to match with the corresponding pitch of the overlay measurement patterns 206 and 208. FIG. 6B shows the substrate 602, which is consistent with the substrate 232 of FIG. 5A. The substrate 602 is mounted on the stage 551 and the stage 551 is coupled to and controlled by the stage controller 560. The reference pattern module 550 is mounted on top of the substrate 602 and perpendicular to the stage 551. FIG. 6B also shows a beam splitter 606 that receives an incident light beam 650 and generates from the incident light beam 650 a first portion 652 parallel with incident light beam and second portion 656 perpendicular to the incident light beam. In some embodiments, the layout generator-controller 520 moves the reference patterns 502A and 502B to specific locations, e.g., by turning on/off the TFT transistors, and/or the stage controller 560 moves the substrate 602 such that the first portion 652 of the incident light beam 650 is incident on the reference pattern 502B and the second portion 656 of the incident light beam 650 is incident on the overlay measurement patterns 206. In some embodiments, the first portion 652 of the incident light beam 650 is diffracted and reflected from the reference pattern 502B and produces the negative and positive first order diffractions 210A and 212A. The second portion 656 of the incident light beam 650 is diffracted and reflected from the overlay measurement pattern 206 and produces the negative and positive first order diffractions 210B and 212B. In some embodiments, an optical system, e.g., the beam splitter 606, receives the negative and positive first order diffractions 210A and 212A from the reference pattern 502B and also receives the negative and positive first order diffractions 210B and 212B from the overlay measurement pattern 206 and combines the received diffractions and transmits the combined diffractions 654 to the detector 222 of the optical system 220. In some embodiments, the diffraction angles of the negative and positive first order diffractions 210A and 212A from the reference pattern 502B are small, e.g., less than 30 degrees. Also the diffraction angles of the negative and positive first order diffractions 210B and 212B from the overlay measurement pattern 206 are small. Thus, the beam splitter 606 may combine the first order diffraction pattern from the reference pattern 502B and from the overlay measurement pattern 206. In some embodiments, optical systems, e.g., objective lenses (not shown), are placed in front of the reference pattern 502B and the overlay measurement pattern 206. The optical systems collect the first order diffractions and direct the first order diffractions to be combined. The negative and positive first order diffractions of the combined diffractions 654 are detected by the detector 222 of the optical system 220. The analyzer module 230 receives corresponding signals of the detected first order diffractions and performs an analysis on the corresponding signals to determine a second drift, e.g., the second overlay error, between the overlay measurement patterns 206 and the reference pattern 502B. In some embodiments, the layout generator-controller 520 moves the reference patterns 502A and 502B to specific locations, e.g., by turning on/off the TFT transistors, and/or the stage controller 560 moves the substrate 602 such that the first portion 652 of the incident light beam 650 is incident on the reference patterns 502A and the second portion 656 of the incident light beam 650 is incident on the overlay measurement patterns 208. Similarly, the analyzer module 230 determines the first overlay error between the overlay measurement pattern 208 and the reference pattern 502A. Also, the analyzer module 230 may determine the total overlay error between overlay measurement patterns 206 and 208 based on the first and second overlay errors, the distance between the generated reference patterns 502A and 502B, and the movement distances of the reference pattern module 550 and the stage 551. In some embodiments, instead of or in addition to moving the substrate 602 and/or the reference pattern module 550, the beam splitter 606 is moved right-or-left and/or up-or-down (11/25-14/34). As discussed above, a stand-alone reference pattern module separate from the substrate can be used for determining an overlay error between different layout patterns of the substrate or between an existing layout pattern of the substrate and a layout pattern of a resist material layer on the substrate that is being patterned by a lithographic process. By using the stand-alone reference pattern module, the overlay error of each layer is measured with respect to the stand-alone reference pattern module. The overlay error of each two layers can be determined by an algebraic sum of the overlay errors between the two layers and the stand-alone reference pattern module. Therefore, the different patterned layers of the substrate do not need to have multiple overlay measurement patterns in each layer to make sure there is an overlap between the overlay measurement patterns of each two layers. Also, the overlay measurement pattern does not need to be re-designed when the film stack changes (17/50-67). FIGS. 2A and 2B respectively illustrate cross-sectional views of a substrate 232 having two overlay measurement patterns 206 and 208. FIG. 2B further illustrates an optical system 220 for determining an overlay error between the two overlay measurement patterns of the substrate in accordance with some embodiments of the present disclosure. FIG. 2A includes a cross-sectional view of an overlay measurement pattern 208 in a first layer 204 that is disposed on top of an underlying substrate 200. In some embodiments, the overlay measurement pattern 208 along with a corresponding circuit layout pattern (not shown) is initially disposed on the underlying substrate 200 and then the first layer 204 is disposed, e.g., epitaxially grown or deposited, over the overlay measurement pattern 208. In some embodiments, a second layer 202 is disposed, e.g., epitaxially grown or deposited, over the first layer 204. In some embodiments, a resist material layer 203 is deposited over the second layer 202 and the resist material layer 203 is exposed and developed to produce an overlay measurement pattern 206 along with a corresponding layout pattern (not shown) in the resist material layer 203. In some embodiments, the overlay measurement patterns 206 and 208 are consistent with the overlay measurement pattern 100 of FIGS. 1A and 1B. Also, consistent with FIGS. 1A and 1B, the overlay measurement patterns 206 and 208 are distributed in the X-direction to measure an overlay error in the X-direction. In some embodiments, overlay measurement patterns distributed in the Y-direction are also disposed to measure an overlay error in the Y-direction. In some embodiments, the second layer 202 does not exist and the overlay measurement pattern 206 is disposed on top of the first layer 204. In some embodiments, a substrate 232 includes the underlying substrate 200 and a structure including the first layer 204, the second layer 202, and the resist material layer 203, on top of the underlying substrate 200 (5/17-51).
Ho et al. 9786569 describes a method for semiconductor fabrication. The method includes receiving a device having a semiconductor substrate, a first layer over the semiconductor substrate, and a second layer over the first layer, the first layer having a first overlay mark. The method further includes forming a first resist pattern over the second layer using at least an exposure tool, the first resist pattern having a second overlay mark, wherein a position of the second overlay mark is adjusted by a first overlay compensation value when forming the first resist pattern. The method further includes performing a first overlay measurement using the second overlay mark in the first resist pattern and the first overlay mark; and performing one or more first manufacturing processes, thereby transferring the second overlay mark into the second layer and removing the first resist pattern. The method further includes performing one or more second manufacturing processes that include forming a third layer over the second layer. After the performing of the one or more second manufacturing processes, the method further includes performing a second overlay measurement using the second overlay mark in the second layer and the first overlay mark; and forming a second resist pattern over the third layer using at least the exposure tool. The second resist pattern has a third overlay mark, wherein a position of the third overlay mark is adjusted by a second overlay compensation value when forming the second resist pattern, and wherein the second overlay compensation value includes both a difference between results of the first and second overlay measurements and the first overlay compensation value (11/65-12/27). The description of the process of figure 4A-G (reproduced below) is found at (4/22-8/46). The exposure tool aligns a mask (e.g., the mask 106) with the device 400 so that an exposed image in the resist layer 408 will be properly aligned with features in the layer 404, particularly the overlay mark 408a in the exposed image will be properly aligned with the overlay mark 404a (5/56-61). The layer 404 may be an insulation layer, a semiconductor layer, or a metal layer (e.g., metal features embedded in a dielectric layer). For example, the layer 404 may include isolation features, semiconductor fin features, epitaxial features, transistor contact features, metal lines, and/or metal vias. In the present embodiment, the layer 404 is a metal layer, such as a layer having copper interconnect for connecting various active or passive components in the substrate 402. The layer 404 includes an overlay mark 404a, which has been formed into the layer 404 using apparatuses and processes, such as discussed with respect to FIG. 1. The various characteristics described with respect to the overlay mark 114 (FIG. 1) apply to the overlay mark 404a. The overlay mark 404a may be disposed in a chip area or a scribe line area of the layer 404. In an embodiment, the overlay mark 404a comprises a metal, such as copper, aluminum, or other suitable metals. For example, the overlay mark 404a may include metal lines embedded in a dielectric material such as an extreme low-k (ELK) dielectric material with a dielectric constant of 2.5 or less. There may be one or more layers between the layer 404 and the substrate 402, such as an etch stop layer, a low-k (k<3.9) dielectric layer, or other suitable material layers. In the present embodiment, the layer 406 is a dielectric layer or a low-k dielectric layer, where metal features such as metal vias and metal lines are to be formed. There may be one or more layers between the layer 406 and the layer 404, such as an etch stop layer, a low-k dielectric layer, or other suitable material layers (4/64-5/25). Subsequent to the metal deposition, operation 214 performs a CMP process to remove excessive metal over the layer 406 (7/40-53).
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Elazhary et al. WO 2021073854 teaches a structure of a semiconductor device having a sub-segment grating structure as a measurement mark and a method for configuring the measurement mark. The method for configuring the measuring mark can be used in the photo-etching process. The method includes determining an initial characteristic function of an initial measurement mark disposed within the overlay layer. The method further comprises making one or more variables of the plurality of sub-segments of the measurement mark (such as pitch of the plurality of sub-segments, duty ratio and/or line width) disturbance and other thickness disturbance of one or more layers in the overlay layer. The method further comprises iteratively performing a disturbance until a minimization characteristic function of the initial measurement mark is determined to set the configuration for the plurality of sub-segments (abstract). Figure 6B illustrates a horizontally sub-segmented grating for metrology [0034,00114-00115]. These horizontal sub-segments can vary in pitch, line width and/or duty cycle so that these are the same or different [00118-00119].
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Figure 6C illustrates a sub-segment grating structure having a constant pitch and six different line widths. In an embodiment, the sub-segment grating structure is configured to be used as an alignment mark [00120-00121]. Figure 7A is similar having lines with three different widths [00124-00131]. Figure 10A shows these as overlay marks on different levels [00160-00169].
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Hsieh et al. 10990023 does not exemplify the claimed process using an overlay pattern formed of two sub-overlay patterns composed having different areas or specifically describe the exposure and development of the resist after proper alignment.
With respect to claims 1-3 and 5-7, it would have been obvious to one skilled in the art to modify the alignment process described with respect to figurers 5A to 6B of Hsieh et al. 10990023 by using it with other overlay patterns known in the art such as the overlay patterns of figure 6B of Elazhary et al. WO 2021073854 where the lines have varying widths and each width has a periodicity as in figures 7A or 6C of Elazhary et al. WO 2021073854 and extending the process to expose a coated photoresist once a suitable alignment as is known in the art from Ho et al. 9786569 at (5/56-61) with a reasonable expectation of forming a useful resist pattern in alignment with the underlying structure.
With respect to claims 1-14, it would have been obvious to one skilled in the art to modify the alignment process described with respect to figurers 5A to 6B of Hsieh et al. 10990023 by using it with other overlay patterns known in the art such as the overlay patterns of figure 6B of Elazhary et al. WO 2021073854 where the lines have varying widths and each width has a periodicity as in figures 7A or 6C of Elazhary et al. WO 2021073854, which are formed in the substrate and embedded in a dielectric layer coated on the substrate by etching the dielectric, coating metals a planarizing the surface to remove the excess metal (outside the etched feature) as taught by Ho et al. 9786569 at (7/40-53) and extending the process to expose a coated photoresist once a suitable alignment as is known in the art from Ho et al. 9786569 at (5/56-61) with a reasonable expectation of forming a useful resist pattern in alignment with the underlying structure.
In the response of 5/20/2026, the applicant argues that the references do not teach the periodicity of the features in two direction. The examiner points to figure 6B, the associated text at [00114-00118] of Elazhary et al. WO 2021073854 which clearly teaches lines arranged in two dimensions and that the lines can have varied widths and/or periodicity and the figures 6C and 7A which illustrate specific patterns of lines with different widths arranged with a periodicity (702).
Claims 1-14 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. 10990023 and Ho et al. 9786569, in view of Elazhary et al. WO 2021073854, further in view of Eom et al. KR 20060071976.
Eom et al. KR 20060071976 (machine translation attached) teaches with respect to figures 2a-2e, the formation of overlay verniers for semiconductor devices.
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Referring to Figure 2a, to form a trench 203 in the normal device region (R2) and a high voltage device region (R3) of the semiconductor substrate 201 in a conventional trench forming step. The first area of the trench forming step when the scribe region (R1) and forming a first vernier (202a), the second region forms a second vernier (202b). Here, the first vernier (202a) is a vernier for use in a gate mask alignment, the second vernier (202b) is a vernier alignment for use in the contact hole mask after patterning the gate
Referring to Figure 2b, in order to secure the margin of the breakdown voltage of the high voltage transistor, by an etching process to form a deeper trench 204 than on the high voltage device region (R3). At this time, the etching process so that during normal device region (R2), the support to form an etch barrier film (not-ji), a deeper depth of the trench 203 formed in the common element region (R2) to form a trench (204) . At the same time, the etching scribe region (R1) is also in the second vernier (202b) are formed with the area so that the second vernier (202b) is formed while maintaining a deep height. Because of this, only the lower than the height of the second vernier (202b) added by the etching (D). On the other hand, by forming an etching film, even in the scribe region (R1) a first vernier (202a) is formed in the area, prevents the first vernier (202a) is formed deeply.
Referring to Figure 2c, to form a device isolation film 205 in the trench by conventional processes (203 and 204). The isolation film 205 is formed in an insulating layer by chemical mechanical polishing process, after forming the insulating layer made of a high density plasma (high density plasma) with the remaining oxide on the entire structure of the trench only way (203 and 204). At this time, in the scribing area (R1) a first vernier (202a) is then completely embedded by the insulating layer 205, a chemical mechanical polishing step by the upper is exposed. A second vernier (202b) is a trench 204 is etched during formation exists with the low height of the inner insulating layer 205. Since the formation deeply.
Referring to Figure 2d, to form a number of material for forming a gate on a semiconductor substrate 101. For example, the gate oxide film, a polysilicon layer, a dielectric film, and the tungsten layer may be formed to form the gate, in addition to commonly used materials that can be formed in addition. In general, the hard mask is choesangbueun of gate material layer 206. Collectively, these materials will be referred to as the gate material layer 206. second vernier planarized by the scribe area in (R1) the gate material layer 206 is a first vernier there is a level difference is the projecting upper (202a) and an upper insulating layer 205 (202b) is formed in the upper portion. At this time, since the second vernier (202b) is formed in the stepped region in an opaque state gate material layer that does not exist (206) is formed, the second vernier (202b) is not seen on a plane. However, the first vernier (202a) is formed because the area is the top of the first vernier (202a) projecting to the step is present, even if the first vernier forming a gate material layer 206 is held on the step difference plane (202a) may be able to distinguish between the types.
If reference to Figure 2e, and patterning the gate material layer 206 and align the gate mask to the etching process using the same, by using the generation step, depending on the form of the first vernier (202a) . Thereby, the gate line of the gate and flash memory cells of the transistor are formed.
In this case, the first vernier (202a) the upper portion of the gate material layer 206 and the remaining, second vernier (202b) formed on the gate material layer 206 is removed. Because the first vernier (202a) by removing the gate material layer 206 of the top can be lacy dew remains on the side wall of the first vernier (202a). However, the second vernier (202b) is formed in the region the second vernier (202b) is lacy dew hardly occurs because the gate material layer 206 is etched while the non-exposed. On the other hand, by removing the second vernier (202b) of the upper gate material layer 206, the insulating layer 205 is exposed. Insulating layer 205 is shown a second vernier (202b) onto the plane that is clearly inside the insulating layer 205 is transparent. To do this, after patterning the gate insulating layer 206, a second contact hole to align the mask by using a vernier (202b) is subjected to a contact hole forming step.
The combination of Hsieh et al. 10990023, Ho et al. 9786569 and Elazhary et al. WO 2021073854 does not exemplify the claimed process using an overlay pattern formed of two sub-overlay patterns composed of recesses formed at different depths in a single substrate/layer or specifically describe the exposure and development of the resist after proper alignment.
It would have been obvious to one skilled in the art to modify the alignment process rendered obvious by the combination of Hsieh et al. 10990023, Ho et al. 9786569 and Elazhary et al. WO 2021073854 by using it with other overlay pattern structures known in the art such as the overlay patterns 202a and 202b of Eom et al. KR 20060071976 which are formed of recesses having different depths in a substrate and extending the process to expose a coated photoresist once a suitable alignment as is known in the art from Ho et al. 9786569 at (5/56-61) with a reasonable expectation of forming a useful resist pattern in alignment with the underlying structure.
Further, it would have been obvious to one skilled in the art to modify the alignment processes rendered obvious by the combination of Hsieh et al. 10990023, Ho et al. 9786569 and Elazhary et al. WO 2021073854 and Eom et al. KR 20060071976 discussed above by extending the process to form a further layer over the second overlay pattern as illustrated in figure 4E of Ho et al. 9786569, coating a photoresist upon that further layer as illustrated in figure 4F of Ho et al. 9786569 and exposing and developing the photoresist to form a third overlay pattern as in figure 4G and the associated text in Ho et al. 9786569 with a reasonable expectation of forming a useful aligned pattern in the photoresist, noting the exposure of the resist and development discussed at (5/17-51)
The response above is relied upon without further comment.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Martin J Angebranndt whose telephone number is (571)272-1378. The examiner can normally be reached 7-3:30 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ching-Yu (Coris) Fung can be reached at 571-270-5713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARTIN J. ANGEBRANNDT
Primary Examiner
Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 July 24, 2026
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