DETAILED ACTION
This action is responsive to the amendment received July 24, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Objections
Claims 1-7 and 9 are objected to because of the following informalities:
Claim 1 has a period in the 4th line from the end of the claim in the line that reads “interconnect.; and”. The period must be deleted.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “…or more conductive interconnections through the via” (it appears for each via (singular), there is only one conductive interconnection), “at least one lateral interconnect on the insulating layer second side contacting the exposed surface of the via at the second insulating layer side” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the insulating layer second side”, “the exposed surface of the via”, and “the connection”, all lacking antecedence.
Claim 1 introduces “one or more conductive interconnections through the via” and later recites “a conductive interconnect contacting a lateral interconnect of the at least one lateral interconnect”. The number of required conductive interconnections are not clear, and it is also not clear if these are supposed to be the same conductive interconnect(ions) through the via or different conductive interconnections elsewhere in the device. In addition, it is not clear if the recited “a lateral interconnect of the at last one lateral interconnect” is referring to the same “at least one lateral interconnect” contacting the exposed surface of the via recited in lines 14-15 or a new lateral interconnect.
The “at least one lateral interconnect on the insulating layer second side contacting the exposed surface of the via” is confusing. As best understood, the “via” is the hole through the silicon core 102, while the lateral interconnect 156 contacts one or more conductive interconnections 144, not the via in 102. Further still, it is not clear where there is an exposed surface of the via in Fig. 1A and where this exposed surface of the via contacts at least one lateral interconnect.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (US 2015/0262972) in view of Chen et al. (US 2021/0159160), Hu et al. (US 2011/0193221), and Uchiyama (US 2014/0042617).
(Re Claim 1) Katkar teaches a semiconductor device assembly, comprising (see Figs. 20.1-21 and ¶¶34,44-46):
a silicon core comprising (Fig. 20.1, silicon core 120.1S):
a first side opposing a second side, wherein the silicon core has a via through the silicon core from the first side to the second side (vias 224);
an oxide layer on the first side (324); and
one or more conductive interconnections (M224) through the via;
a first redistribution layer on the first side (RDL 210T); and
a silicon stiffener frame (silicon frame 410) over the first redistribution layer on the first side, an outer surface of the stiffener frame disposed substantially along a perimeter of the semiconductor device assembly (see Figs. 20.1-21).
Katkar lacks numerous details regarding the silicon core and the RDL layer: an oxide layer on the second side, one or more conductive interconnections… having a surface exposed at the first side and the second side, an insulating layer over the oxide layer on the first side, the second side, and within the via, the insulating layer having a first insulating layer side facing the oxide layer and a second insulating layer side facing away from the oxide layer;one or more conductive interconnections through the via and havinq a surface protruding from the via at the second insulating layer side the redistribution layer including at least one lateral interconnect on the insulating layer second side contacting the exposed surface of the via at the second insulating layer side and at least one vertical interconnect extending from the at least one lateral interconnect, a conductive interconnect contactinq a lateral interconnect of the at least one lateral interconnect at a location spaced laterally from the connection of the at least one vertical interconnect to the at least one lateral interconnect” as Katkar discloses an older silicon interposer configuration and only schematically shows the RDL layer without much detail.
A PHOSITA desiring to make, use, and improve upon Katkar’s device would be motivated to look to related art to teach new and improved interposers and details of redistribution layers for making electrical connections to the TSVs in the interposer. Related art from Chen discloses a new and improved interposer (see Fig. 1B and ¶¶42-60) which has: a silicon core 102 comprising: a first side opposing a second side, wherein the silicon core has a via 103 through the silicon core from the first side to the second side; an oxide layer 104 on the first side and the second side; and one or more conductive interconnections 144+154 through the via and having a surface exposed at the first side and the second side (Fig. 1B); an insulating layer 118 over the oxide layer on the first side, the second side, and within the via; a first redistribution layer 150 on the first side. A PHOSITA would find it obvious to substitute Chen’s novel core structure that overcomes many of the disadvantages associated with conventional semiconductor package, PCB, spacer, and carrier structures described by Chen (see ¶¶3-5, 40-46). When substituting Chen’s new and improved silicon core for Katkar’s silicon core, the silicon frame will be over the insulating layer 118. While Chen shows the corresponding RDL 150, corresponding to Katkar’s RDL, Chen also lacks specific details of the RDL layer wiring. A PHOSITA would be motivated to look to related art to teach details of RDL layers where Chen and Katkar are silent, in particular, RDL configurations compatible with Chen’s interposer having the protruding TSVs. Related art from Hu teaches forming conductive interconnections (TSVs) 20 protruding from a silicon core interposer 10 at the second side of an insulating layer (individual insulating layers not shown, see dashed line in annotated Fig. 1B below) with lateral RDL interconnect wiring 14 contacting the TSVs, at least one vertical interconnect 16 extending from the lateral interconnect (see Figs. 1A-1B). Hu further teaching an additional conductive interconnect (as best understood, an additional TSV 20, see §112 above) contacting an additional lateral interconnect 14 (another horizontal wire) at a location spaced laterally from a connection of the at least one vertical interconnect to at least one lateral interconnect. Related art from Uchiyama also similarly teaches TSVs 124 protruding from a silicon core interposer 116 at a second side of an insulating layer, wherein the TSVs contact lateral interconnect wiring (horizontal wiring in 118, not labeled) in the redistribution layer, the lateral interconnect wiring contacting vertical interconnects (unlabeled vertical vias in 118, see annotated Fig. 11 below). Uchiyama further teaches an additional conductive interconnect (as best understood, an additional TSV 124, see §112 above) contacting an additional lateral interconnect (another horizontal wire) at a location spaced laterally from a connection of the at least one vertical interconnect to at least one lateral interconnect. In view of Hu and Uchiyama, a PHOSITA would recognize the RDL 150 of Chen, corresponding to the RDL 210T of Katkar, formed over the protruding conductive interconnect at the second side of the insulating layer 118, will obviously comprise conventional RDL structures comprising insulating layers and a combination of both lateral and vertical interconnections in the insulating layers, the lateral interconnections contacting the TSVs. This is a well known RDL configuration enabling high density interconnections between protruding TSVs and external chips/dies.
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(Re Claim 2) wherein the silicon stiffener frame is formed of substantially the same material as the silicon core (the silicon core is made of silicon and the silicon frame is made of silicon).
(Re Claim 3) wherein the silicon stiffener frame has a coefficient of thermal expansion (CTE) substantially matching a CTE of the silicon core (the silicon core is made of silicon and the silicon frame is made of silicon, the CTE’s will substantially match).
(Re Claim 4) wherein the silicon stiffener frame has an opening formed therein (see Fig. 20.1).
(Re Claim 5) wherein the semiconductor device assembly further comprises a first semiconductor die disposed within the opening of the silicon stiffener frame (see Fig. 20.1: die 110).
(Re Claim 6) wherein the first semiconductor die is electrically coupled to one or more contacts of the redistribution layer by flip-chip attachment (see Fig. 220.1, the dies are flip-chip mounted to contacts of the RDL 210.T).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. and Chen et al. as applied above, and further in view of Arai et al. (US 2010/0025081) and Savastiouk et al. (US 2005/0136634).
(Re Claim 7) wherein the silicon stiffener frame has a coefficient of thermal expansion (CTE) substantially matching a CTE of the silicon core and a CTE of the first semiconductor die.
As modified above, the silicon frame and silicon core will have substantially the same CTE, Katkar is silent regarding the material of the semiconductor dies 110. A PHOSITA may be motivated to look to related art to teach suitable materials of conventional semiconductor dies. Related art from Arai discloses (¶¶35, 38, 39) silicon semiconductor dies, and that it is beneficial to use a silicon die with a silicon interposer to minimize CTE mismatch. Related art from Savastiouk also discloses (¶¶3,8,26,66,79) silicon semiconductor dies, and that it is beneficial to use a silicon die with a silicon interposer to minimize CTE mismatch. In view of the prior art, a PHOSITA would find it obvious to use silicon dies in Katkar’s package to match CTEs as taught by Arai and Savastiouk. By selecting a silicon die along with the silicon interposer and silicon stiffener frame, the CTEs will substantially match, thereby minimizing stress and warp.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. and Chen et al. as applied above, and further in view of Wang et al. (US 7,585,702).
(Re Claim 9) Chen discloses wherein the silicon core has a thickness less than about 200 µm (Chen: ¶44).
Katkar is silent regarding the stiffener frame has a thickness greater than about 500 µm. A PHOSITA desiring to make and use Katkar’s package would be motivated to look to related art to determine appropriate dimensions where Katkar is silent. From Katkar’s Fig. 20.1, the frame extends above the dies. Related art from Wang teaches conventional semiconductor dies have thicknesses in a range of 21-32 mils thick, or a thinner die having a thickness up to 20 mils thick (col 5, lines 38-41). A PHOSITA would find it obvious to select dies of conventional thickness according to Wang. Then a conventional die having a maximum thickness of 20 mils to 32 mils thick, considering the frame is thicker than the dies + their bumps, the frame must be at least 500 µm thick.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaching conventional RDL structures depicted in a variety of different ways and varying detail.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
