DETAILED ACTION
This action is responsive to the application No. 17/886,102 filed on August 11, 2022.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I and Modifications A-J-M-P according to the restriction mailed 8/11/2025, pp. 2-3, corresponding to claims 1-7, 9, and 13-20, in the reply filed on January 5, 2026, is acknowledged. Claims 8 and 10-12 are withdrawn from consideration. In addition, claims 13-19 are drawn to nonelected Species II having the metal layer on the silicon core connected to ground as shown in Fig. 1B, and claim 20 is drawn to nonelected Species III having the stiffener frame contacting the oxide layer as shown in Fig. 1C. Claims 8 and 10-20 are withdrawn from consideration. Claims 1-7 and 9 are pending for examination.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “…one or more conductive interconnections through the via and having a surface exposed at the first side and the second side …”. This limitation is confusing because in the elected species depicted in Fig. 1A, the conductive interconnections 144 through the vias 113 are not exposed on either side, on both sides the conductive interconnections are covered by the RDL layers. It is unclear what Applicant regards as “exposed” in view of Fig. 1A which does not show “exposed” features.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. (US 2015/0262972) in view of Chen et al. (US 2021/0159160).
(Re Claim 1) Katkar teaches a semiconductor device assembly, comprising (see Figs. 20.1-21 and ¶¶34,44-46):
a silicon core comprising (Fig. 20.1, silicon core 120.1S):
a first side opposing a second side, wherein the silicon core has a via through the silicon core from the first side to the second side (vias 224);
an oxide layer on the first side (324); and
one or more conductive interconnections (M224) through the via;
a first redistribution layer on the first side (RDL 210T); and
a silicon stiffener frame (silicon frame 410) over the first redistribution layer on the first side, an outer surface of the stiffener frame disposed substantially along a perimeter of the semiconductor device assembly (see Figs. 20.1-21).
Katkar lacks numerous details regarding the silicon core: an oxide layer on the second side, one or more conductive interconnections… having a surface exposed at the first side and the second side, an insulating layer over the oxide layer on the first side, the second side, and within the via as Katkar discloses an older silicon interposer configuration. A PHOSITA desiring to make, use, and improve upon Katkar’s device would be motivated to look to related art to teach new and improved interposers. Related art from Chen discloses a new and improved interposer (see Fig. 1B and ¶¶42-60) which has: a silicon core (102) comprising: a first side opposing a second side, wherein the silicon core has a via (103) through the silicon core from the first side to the second side; an oxide layer (104) on the first side and the second side; and one or more conductive interconnections (144+154) through the via and having a surface exposed at the first side and the second side (Fig. 1B); an insulating layer (118) over the oxide layer on the first side, the second side, and within the via; a first redistribution layer (150) on the first side. A PHOSITA would find it obvious to substitute Chen’s novel core structure that overcome many of the disadvantages associated with conventional semiconductor package, PCB, spacer, and carrier structures described by Chen (see ¶¶3-5, 40-46). When substituting Chen’s new and improved silicon core for Katkar’s silicon core, the silicon frame will be over the insulating layer 118.
(Re Claim 2) wherein the silicon stiffener frame is formed of substantially the same material as the silicon core (the silicon core is made of silicon and the silicon frame is made of silicon).
(Re Claim 3) wherein the silicon stiffener frame has a coefficient of thermal expansion (CTE) substantially matching a CTE of the silicon core (the silicon core is made of silicon and the silicon frame is made of silicon, the CTE’s will substantially match).
(Re Claim 4) wherein the silicon stiffener frame has an opening formed therein (see Fig. 20.1).
(Re Claim 5) wherein the semiconductor device assembly further comprises a first semiconductor die disposed within the opening of the silicon stiffener frame (see Fig. 20.1: die 110).
(Re Claim 6) wherein the first semiconductor die is electrically coupled to one or more contacts of the redistribution layer by flip-chip attachment (see Fig. 220.1, the dies are flip-chip mounted to contacts of the RDL 210.T).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. and Chen et al. as applied above, and further in view of Arai et al. (US 2010/0025081) and Savastiouk et al. (US 2005/0136634).
(Re Claim 7) wherein the silicon stiffener frame has a coefficient of thermal expansion (CTE) substantially matching a CTE of the silicon core and a CTE of the first semiconductor die.
As modified above, the silicon frame and silicon core will have substantially the same CTE, Katkar is silent regarding the material of the semiconductor dies 110. A PHOSITA may be motivated to look to related art to teach suitable materials of conventional semiconductor dies. Related art from Arai discloses (¶¶35, 38, 39) silicon semiconductor dies, and that it is beneficial to use a silicon die with a silicon interposer to minimize CTE mismatch. Related art from Savastiouk also discloses (¶¶3,8,26,66,79) silicon semiconductor dies, and that it is beneficial to use a silicon die with a silicon interposer to minimize CTE mismatch. In view of the prior art, a PHOSITA would find it obvious to use silicon dies in Katkar’s package to match CTEs as taught by Arai and Savastiouk. By selecting a silicon die along with the silicon interposer and silicon stiffener frame, the CTEs will substantially match, thereby minimizing stress and warp.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Katkar et al. and Chen et al. as applied above, and further in view of Wang et al. (US 7,585,702).
(Re Claim 9) Chen discloses wherein the silicon core has a thickness less than about 200 µm (Chen: ¶44).
Katkar is silent regarding the stiffener frame has a thickness greater than about 500 µm. A PHOSITA desiring to make and use Katkar’s package would be motivated to look to related art to determine appropriate dimensions where Katkar is silent. From Katkar’s Fig. 20.1, the frame extends above the dies. Related art from Wang teaches conventional semiconductor dies have thicknesses in a range of 21-32 mils thick, or a thinner die having a thickness up to 20 mils thick (col 5, lines 38-41). A PHOSITA would find it obvious to select dies of conventional thickness according to Wang. Then a conventional die having a maximum thickness of 20 mils to 32 mils thick, considering the frame is thicker than the dies + their bumps, the frame must be at least 500 µm thick.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related interposers and stiffener rings/frames.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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