DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received 6/12/2026. Claims 1, 2, 4-10 & 19-25 are pending in this application. Claims 3 & 11-18 are canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
2. Claims 1, 2, 4-10 and 19-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitation in amended claim 1, in d) paragraph, which states, “wherein a doping concentration of the doped layer is greater than that of the semiconductor substrate", was not disclosed in the original filing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 10 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2015/0061007) in view of Roy et al. (US 2012/0261784).
Re claim 1, Yang teaches, under BRI, Fig. 7, [0019-0023], an electrode structure, comprising:
a) a semiconductor substrate (702);
b) a trench (704 defined between 724) extending from an upper surface of the semiconductor substrate into the semiconductor substrate (702);
c) two contact regions (736, 738) extending from the upper surface of the semiconductor substrate (702) into the semiconductor substrate (702), and being located on two sides of the trench (704);
d) a doped layer (724) located on and fully covering outer sidewalls (704a) of the trench (704) and a bottom of the trench (704b of 704), wherein the doped layer (724) extends from the upper surface of the semiconductor substrate (702) to the bottom of the trench (704) along the outer sidewalls of the trench (704), wherein the semiconductor substrate (702) surrounds the doped layer (724); and
e) filling material (726) in the trench (704), wherein the two contact regions (736, 738) are in contact with the doped layer (724) such that portions of the doped layer (724) on the outer sidewalls of the trench (704) are between the trench (704) and the contact regions (736, 738) (in horizontal direction), wherein a doping type (P type) of the contact regions (736, 738) matches a doping type (P type) of the doped layer (724), and wherein the doping type (N type) of the semiconductor substrate region (702) adjacent to the two contact regions (736, 738) is the same as that of the two contact regions (736, 738).
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Yang does not explicitly teach wherein a doping concentration of the doped layer is greater than that of the semiconductor substrate.
Roy teaches, Fig. 3A, [0055-0056], a doping concentration of the doped layer (P+ type 67) is greater than that of the semiconductor substrate (P-type 62, 63).
As taught by Roy, one of ordinary skill in the art would utilize & modify the above teaching into Yang to obtain a doping concentration of the doped layer is greater than that of the semiconductor substrate as claimed, because it aids in achieving desired dopant concentration(s) in each region to improve the performance of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Roy in combination Yang due to above reason.
Re claim 10, in combination cited above, Roy teaches wherein the filling material (68) is metal or doped polycrystalline material [0054].
Re claim 25, Yang teaches, Fig. 7, the doped layer (724) is thinner than a smallest width of the trench (704).
4. Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Roy as applied claim 1, and further in view of Davari et al. (US 6,333,532).
The teachings of Yang/Roy have been discussed above.
Re claim 2, Yang/Roy does not explicitly teach the trench is a trapezoidal trench with a top width greater than a bottom width.
Davari teaches, Fig. 8, the trench (94) is trapezoid with a top width greater than a bottom width.
As taught by Davari, one of ordinary skill in the art would utilize & modify the above teaching to obtain the trench is a trapezoidal trench with a top width greater than a bottom width as claimed, because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Davari in combination with Yang/Roy due to above reason.
Re claim 9, Yang teaches the filling material (1300) is oxide (e.g., silicon oxide, Fig. 13, [0030]) or undoped polycrystalline material or borate glass.
5. Claims 4-8 and 19-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as modified by Roy as applied claim 1, and further in view of You (US 2013/0015523).
The teachings of Yang/Roy have been discussed above.
Re claim 4, Yang/Roy does not teach well regions located on both sides of the trench, wherein the two contacts regions are located in the well regions, and the well regions and the two contact regions are of the same doping type.
You teaches, Fig. 4H, [0026], well regions (118) located on both sides of the trench (consider 404, 402), wherein the two contacts regions (110) are located in the well regions (118), and the well regions (118) and the two contact regions (110) are of the same doping type.
As taught by You, one of ordinary skill in the art would utilize & modify the above teaching to obtain well regions located on both sides of the trench, wherein the two contacts regions are located in the well regions, and the well regions and the two contact regions are of the same doping type as claimed, because it aids in improving control of device channel length and improving device performance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by You in combination with Yang/Roy due to above reason.
Re claim 5, in combination cited above, You teaches, Figs. 4H & 9, [0055, 0056], the contact regions (110) are connected to a predetermined potential (voltage sources 902, 930) through a connection terminal (gate 102 or a node).
Re claim 6, in combination cited above, You teaches, under BRI, Fig. 4H, a connection potential of two contact regions differs based on the doping type of the contact region (N-type vs P-type).
Re claim 7, in combination cited above, You teaches, Fig. 4H, the connection potential of two contact regions (110) is higher when the doping type of the two contact regions is N-type.
Re claim 8, in combination cited above, You teaches, consider right side of Fig. 4H, when the doping type of the contact region is P-type (106 or 218), the contact region is connected to the GND potential (Fig. 9).
Re claim 19, in combination cited above, You teaches, Fig. 4H, a semiconductor structure, comprising the electrode structure according to claim 1 (see claim 1 above), and further comprising:
a) a first MOS transistor (left transistor) located in a first region of the semiconductor substrate; and
b) a second MOS transistor (right transistor) located in a second region of the semiconductor substrate,
c) wherein the electrode structure (discussed in claim 1 above) is located between the first MOS transistor and the second MOS transistor, and is used to absorb (as intended use) the carriers flowing between the first MOS transistor and the second MOS transistor to avoid a parasitic (as intended use) structure between the first MOS transistor and the second MOS transistor turning on.
Re claim 20, in combination cited above, You teaches, claim 1, the first MOS transistor and the second MOS transistor are both N-type MOS transistors (e.g., NMOS and N-LDMOS).
Re claim 21, in combination cited above, You teaches, under BRI, Fig. 4H, a) a parasitic PNP transistor is formed a P-type body region (114) located in a source region of the first MOS transistor (left transistor), a first N-type well region (118) of the first MOS transistor and a semiconductor substrate (124), a parasitic NPN transistor is formed by a first well region (118), the semiconductor substrate (124) and a N-type region (122, 126) of the second MOS transistor, and the N-type region (122, 126) is adjacent to the semiconductor substrate; and b) when the parasitic PNP transistor is turned on (e.g., operational purpose or based on similar teaching structure), the first carriers flow to the second region through the parasitic PNP transistor, and when the parasitic NPN transistor is turned on (e.g., operational purpose or based on similar teaching structure), the second carriers flow to the first region through the NPN transistor.
(*) The limitation “when the PNP transistor is turned on…flow to the first region of through the NPN transistor” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114.
Re claim 22, in combination cited above, You teaches, under BRI, Fig. 4H, an extension depth of the electrode structure (110) in the semiconductor substrate is not greater than the depth of the first MOS transistor (e.g., 114 or 118) in the semiconductor substrate.
Re claim 23, in combination cited above, You teaches, under BRI, Fig. 4H, an extension depth of the electrode structure (110) in the semiconductor substrate is not greater than the depth of the second MOS transistor (e.g., 118) in the semiconductor substrate.
Re claim 24, in combination cited above, You teaches, under BRI & best understanding, Fig. 4H, the electrode structure (see claim 1 above) absorbs (as intended use or based on similar teaching structure) first carriers flowing in the direction from the parasitic PNP transistor to the second region, and absorbs (as intended use or based on similar teaching structure) the second carriers flowing in the direction of the parasitic NPN transistor to the first direction.
Response to Arguments
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/23/26
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