DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status
Acknowledgment is made of the amendment filed on 8/29/2025, which amended claims 1, 3-9, 12, and 14. Claims 1-12 and 14-15 are currently pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/29/2025 has been entered.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2, line 1, “the exposed wafer” should be changed to --the wafer-- to correct antecedence.
Appropriate correction is required to place claims in better form.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus” in lines 14-15 is vague and indefinite. The limitation is rendered unclear because the language “can be” merely requires that it is possible that the experimentation or simulation is performed by the apparatus or a system external to the apparatus. That is, the broadest reasonable interpretation of the claim limitation including the language “can be” does not positively require experimentation or simulation performed by the apparatus or a system external to the apparatus. Thus, one of ordinary skill in the art would be unable to determine the scope of the selected process condition in the apparatus, and the metes and bounds of the claim scope is rendered indefinite. For the purposes of examination, the limitation is interpreted as meaning wherein the experimentation or simulation is performed by the apparatus or a system external to the apparatus. Thus, claims 1 and all claims depending therefrom are rejected as being indefinite. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tung-Sing Pak et al. (US PGPub 2010/0142800, Pak hereinafter) in view of Park (US PGPub 2015/0199803).
Regarding claim 1, as best understood, Pak discloses an apparatus (Figs. 5-6) comprising:
a memory storing a set of instructions (Figs. 5-6, paras. [0080]-[0081], [0086]-[0089], a storage medium stores steps of a method); and
at least one processor configured to execute the set of instructions to cause the apparatus to perform operations (Figs. 5-6, paras. [0086]-[0089], a computer system 58 includes one or more processors to execute instructions stored in a memory) comprising:
inspecting a wafer that has been exposed by a lithography system using a mask and a selected process condition applied to the wafer (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiple areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects), wherein the selected process condition has been:
determined based on a mask defect printability (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiple areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects); and
identifying, based on the inspection, a wafer defect that is caused by a defect on the mask to enable identification of the defect on the mask (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067]-[0071], the detected wafer defects caused by reticle defects are identified). Pak does not appear to explicitly describe wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus.
Park discloses wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition (Figs. 1-10, abstract, paras. [0028]-[0030], [0034], [0037]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0055]-[0070], [0073]-[0084], different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners. Park states “the process window may be determined to include only those focus and exposure conditions at which no or only acceptable defects are printed” in para. [0055], and numbers of defects from the modulations are evaluated (para. [0063])), wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus (Figs. 6-10, paras. [0055]-[0070], [0073]-[0084], claim 18, “any suitable commercially available method or system” (see para. [0059]) simulates the marginal focus and exposure conditions by simulating printing a wafer, and a further wafer is printed with process conditions to define target conditions to detect critical defects or particular defect types).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus as taught by Park in selecting the process condition in the apparatus as taught by Pak since including wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus is commonly used to improve patterning characterization within specification limits and can be used for pattern reliability checks (Park, para. [0052]) and to increase the signal-to-defect ratio by inspecting relevant modulations, thereby improving coverage of wafer variations, improve defect sampling, and improve review capability of systematic defects (Park, [0068], [0070]).
Regarding claim 2, Pak as modified by Park discloses wherein the exposed wafer comprises a first field and a second field, the first field being exposed with the selected process condition and the second field being exposed with a different process condition from the selected process condition (Pak, Figs. 1, 4-6, paras. [0012]-[0014], [0020]-[0021], [0040], [0043]-[0045], [0059]-[0061], [0064], the exposed wafer includes multiple areas exposed with different lithography process parameters).
Regarding claim 3, Pak as modified by Park discloses wherein, in identifying the wafer defect, the at least one processor is configured to execute the set of instructions to cause the apparatus to perform operations comprising: inspecting an entire area of the first field to identify a defect on the first field (Pak, Fig. 1, paras. [0012], [0014], [0015], [0020]-[0021], [0048]-[0050], [0052], [0056], [0057], [0067], [0070], the dies on the wafer are inspected to identify defects).
Regarding claim 4, Pak as modified by Park discloses wherein, in identifying the wafer defect, the at least one processor is configured to execute the set of instructions to cause the apparatus to perform operations comprising: inspecting the second field at a location corresponding to a location of the identified defect on the first field (Pak, Fig. 1, 4-6, paras. [0013], [0015]-[0017], [0021], [0039], [0050]-[0052], [0054], [0058]-[0061], [0064], [0067], [0076], [0078], the inspection system obtains images of exposed areas on the wafer, and images of first areas with defects are compared to images of second areas to identify defects).
Regarding claim 5, Pak as modified by Park discloses wherein the at least one processor is configured to execute the set of instructions to cause the apparatus to further perform operations comprising: inspecting a plurality of multiple fields of a test wafer to identify a defect on a corresponding field after each of the multiple fields of the test wafer was exposed, by a lithography system using a mask, with a different process condition (Pak, Figs. 1 and 4-6, paras. [0012], [0014], [0015], [0020]-[0021], [0035], [0048]-[0050], [0052], [0056], [0057], [0067], [0070], the focus and exposure does of the lithography process are varied during exposure of areas on the wafer, and the exposed areas are inspected to identify defects); and
determining the selected process condition based on the inspection (Figs. 1 and 4-6, paras. [0060], [0064]-[0067], the values of focus and exposure dose are arranged to enhance detection of defects).
Regarding claim 6, although Pak as modified by Park discloses wherein, in determining the selected process condition, the at least one processor is configured to execute the set of instructions to cause the apparatus to further perform operations comprising:
selecting a field that has the predetermined range of a number of defects identified in the corresponding field (Park, Figs. 1-10, abstract, paras. [0028]-[0030], [0034]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0057]-[0059], [0074]-[0084], different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners. The selected die printed at secondary modulation conditions are compared to determine defects);
determining the process condition used to expose the selected field to be the selected process condition (Pak, Figs. 1 and 4-6, paras. [0060], [0064]-[0067], the values of focus and exposure dose are arranged to enhance detection of defects, and as modified by Park, Figs. 1-6, abstract, paras. [0028]-[0030], [0034], [0037]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0057]-[0059], different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners).
Regarding claim 7, Pak as modified by Park discloses wherein, in inspecting the plurality of the multiple fields of the test wafer, the at least one processor is configured to execute the set of instructions to cause the apparatus to perform operations comprising: inspecting a partial area of a field of the multiple fields to identify a defect on the partial area (Pak, Figs. 1 and 4-6, paras. [0012], [0014], [0015], [0020]-[0021], [0048]-[0050], [0052], [0056], [0057], [0067], [0070], the dies on the wafer are inspected to identify defects).
Regarding claim 10, Pak as modified by Park discloses wherein the process condition comprises exposure dose, focus, or an illumination condition (Pak, Figs. 1, 4-6, paras. [0012], [0014], [0035]-[0036], [0038], [0040], [0042]-[0044], [0047], [0060], [0063]-[0064], [0067], the focus and dosage of the lithography exposure is modulated for different areas of the wafer).
Regarding claim 11, Pak as modified by Park discloses wherein the selected process condition comprises exposure dose less than a nominal dose (Pak, Fig. 1, 5-6, paras. [0038], [0063]-[0064], the dose is varied to underexpose areas of the wafer to enhance defect detection).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Pak as modified by Park as applied to claim 1 above, and further in view of Chang et al. (US PGPub 2002/0019729, Chang hereinafter).
Regarding claim 8, Pak as modified by Park discloses wherein the at least one processor is configured to execute the set of instructions to cause the apparatus to further perform operations comprising: determining the selected process condition for the lithography system (Pak, Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects during inspection), but Pak as modified by Park does not appear to explicitly describe setting a lithography model for simulating an exposure process of the wafer with the mask having a defect particle; simulating an electromagnetic field near the mask based on topography of the mask and the defect particle on the mask, the electromagnetic field enabling a determination of a light path near the mask; simulating an aerial image or resist image based on the simulated electromagnetic field at the wafer, and determining the selected process condition based on the simulated aerial image or resist image.
Chang discloses setting a lithography model for simulating an exposure process of the wafer with the mask having a defect particle (Figs. 4-6, 8-10, paras. [0059]-[0070], [0092], [0095]-[0096], [0103]-[0111], a photolithography process is simulated for forming images of a mask including defects on a wafer);
simulating an electromagnetic field near the mask based on topography of the mask and the defect particle on the mask, the electromagnetic field enabling a determination of a light path near the mask (Figs. 4-6, 8-10, paras. [0059], [0068], [0070]-[0078], [0087]-[0092], [0095]-[0096], an image simulator receives lithography conditions input for the process conditions of illuminating the physical mask, including the defects on the mask. The image of the mask having a defect is simulated for the illumination conditions);
simulating an aerial image or resist image based on the simulated electromagnetic field at the wafer (Figs. 4-6, 8-10, paras. [0059]-[0060], [0068]-[0078], [0087]-[0096], the simulation includes determining the printability of the defect by simulating the image formed in the photoresist of the wafer of the mask having the defect), and
determining the selected process condition based on the simulated aerial image or resist image (Figs. 4-6, 8-12, paras. [0060], [0099], [0106]-[0107], [0111]-[0117], the lithography process conditions are determined based on the simulated resist images).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included setting a lithography model for simulating an exposure process of the wafer with the mask having a defect particle; simulating an electromagnetic field near the mask based on topography of the mask and the defect particle on the mask, the electromagnetic field enabling a determination of a light path near the mask; simulating an aerial image or resist image based on the simulated electromagnetic field at the wafer, and determining the selected process condition based on the simulated aerial image or resist image as taught by Chang with determining the selected process condition for the lithography system in the apparatus as taught by Pak as modified by Park since including setting a lithography model for simulating an exposure process of the wafer with the mask having a defect particle; simulating an electromagnetic field near the mask based on topography of the mask and the defect particle on the mask, the electromagnetic field enabling a determination of a light path near the mask; simulating an aerial image or resist image based on the simulated electromagnetic field at the wafer, and determining the selected process condition for the lithography system based on the simulated aerial image or resist image is commonly used to provide efficient mask inspection to determine the acceptability of mask defects.
Regarding claim 9, Pak as modified by Park in view of Chang discloses wherein, in setting up the lithography model, the at least one processor is configured to execute the set of instructions to cause the apparatus to further perform operations comprising: setting a plurality of lithography models with a different processing condition (Chang, Figs. 4-6, 8-10, paras. [0059], [0062]-[0063], [0068], [0070]-[0078], [0087]-[0092], [0095]-[0096], the lithography conditions input includes a range of parameters to perform the image simulation a number of times for different combinations of lithography parameters).
Claims 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tam et al. (US PGPub 2015/0346610, Tam hereinafter) in view of Pak and Park.
Regarding claim 12, Tam discloses a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for determining a modulation condition (Figs. 1-8, paras. [0009]-[0024], [0053]-[0061], [0140], [0141], [0219], a non-transitory computer readable medium stores instructions to perform a method of determining the focus and exposure values for the next PWQ wafer), the operations comprising:
inspecting a plurality of multiple fields of a test wafer to identify a defect on a corresponding field after each of the multiple fields of the test wafer was exposed, by a lithography system using a mask, with a different process condition (Figs. 1-8, paras. [0014]-[0018], [0061], [0091], [0093], [0094], [0099]-[0124], [0126]-[0147], [0151]-[0160], a metrology process inspects the FEM wafer exposed with multiple focus and exposure values, and a metrology process inspects a PWQ wafer formed by exposing the mask pattern on multiple dies with different values of focus and exposure. The FEM wafer and PWQ wafer are used to identify weak points to evaluate a mask for defects); and
determining a modulation condition based on a mask defect printability under the modulation condition, wherein the modulation condition is determined based on the inspection of the plurality of multiple fields of the test wafer (Figs. 1-8, paras. [0009]-[0025], [0039], [0061], [0091], [0093], [0094], [0099]-[0116], [0117]-[0124], [0126]-[0147], [0151]-[0160], the process includes determining focus and exposure values for the next PWQ wafer and the desired process window to be used in downstream production based on the focus and exposure values associated with the weak points identified from the metrology results), determining the modulation condition comprising:
determining a process condition used to expose a selected field to be the modulation condition (Figs. 1-8, paras. [0009]-[0025], [0039], [0061], [0091], [0093], [0094], [0099]-[0116], [0117]-[0124], [0126]-[0147], [0151]-[0160], the process includes determining focus and exposure values for the next PWQ wafer and the desired process window to be used in downstream production based on the focus and exposure values associated with the weak points identified from the metrology results). Tam does not appear to explicitly describe a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition, selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field.
Pak discloses inspecting a plurality of multiple fields of a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition to identify a defect on a corresponding field (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0025], [0035], [0038]-[0040], [0043]-[0044], [0047], [0055]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiple areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included inspecting a plurality of multiple fields of a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition as taught by Pak in the inspecting the test wafer in the inspection in the operations performed by the non-transitory computer readable medium as taught by Tam since including inspecting a plurality of multiple fields of a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition is well-known and commonly used to produce a wafer used to qualify a reticle without requiring further reticle inspection systems, thereby improving inspection throughput (Pak, paras. [0009]-[0014], [0078]).
Tam as modified by Pak does not appear to explicitly describe selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field.
Park discloses selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field (Figs. 1-10, abstract, paras. [0028]-[0030], [0034]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0057]-[0065], [0068]-[0070], [0073]-[0084], claim 18, different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners. The selected die printed at secondary modulation conditions are compared to determine defects. Target conditions are defined to detect critical defects or particular defect types. Park states “the process window may be determined to include only those focus and exposure conditions at which no or only acceptable defects are printed” in para. [0055], and numbers of defects from the modulations are evaluated (para. [0063])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field as taught by Park in determining the modulation condition in the operations performed by the non-transitory computer readable medium as taught by Tam as modified by Pak since including selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field is commonly used to improve patterning characterization within specification limits and can be used for pattern reliability checks (Park, para. [0052]) and to increase the signal-to-defect ratio by inspecting relevant modulations, thereby improving coverage of wafer variations, improve defect sampling, and improve review capability of systematic defects (Park, paras. [0068], [0070]).
Regarding claim 14, Tam as modified by Pak Park discloses wherein, in inspecting the plurality of the multiple fields of the test wafer, the set of instructions that is executable by at least one processor of the computing device cause the computing device (Tam, Figs. 1-8, paras. [0014]-[0018], [0061], [0091], [0093], [0099]-[0124], [0126]-[0147]), to further perform operations comprising:
inspecting a partial area of a field of the multiple fields to identify a defect on the partial area (Tam, Figs. 1-8, paras. [0014]-[0018], [0061], [0091], [0093], [0096]-[0124], [0126]-[0147], the die on the wafer are inspected, and the suspected defects are reviewed to identify defects and weak points).
Regarding claim 15, Tam as modified by Park discloses wherein the process condition comprises exposure dose, focus, or an illumination condition (Tam, Figs. 1-8, paras. [0010]-[0011], [0040], [0091]-[0094], [0101]-[0111], [0112]-[0124], [0126]-[0147], [0159], forming the FEM wafer and the PWQ wafer involves varying the exposure parameters, such as focus and dose (or exposure), while exposing the mask pattern on the wafer).
Response to Arguments
Applicant’s arguments, see pages 9-11, filed 8/29/2025, with respect to the prior 35 U.S.C. 112(b) rejection of claim 1 have been fully considered and are persuasive in light of the clarifying amendment. The prior 35 U.S.C. 112(b) rejection of claim 1 has been withdrawn. However, as discussed above, the amended language introduces the indefinite language “wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus” in lines 14-15 of the claim. Appropriate correction is required.
Applicant's arguments filed 8/29/2025 have been fully considered but they are not persuasive.
Applicant argues on pages 12-14 that Pak as modified by Park fail to suggest the invention as recited in claim 1. The Applicant alleges Pak does not teach selecting a process condition based on defect printability and fails to describe preselected process conditions that meet a predetermined mask defectivity criterion. The Applicant further alleges that Park fails to “involve selecting a process condition in advance based on a mask defectivity threshold, nor does it teach using a predetermined range of defects as a selection criterion.” The Applicant additionally contends that the rationale to combine the teachings of Park with those of Pak is conclusory, lacks motivation for the combination. The Applicant asserts “[a]ccording to MPEP §2143(I)(A), a proposed modification that renders the prior art unsatisfactory for its intended purpose cannot support a finding of obviousness” and alleges that replacing Pak’s modulation with a single preselected process condition would defeat its purpose. The Applicant argues that there is no reasoned rationale as required by MPEP §2141.01(a) for motivating combination of Pak in view of Park and the combination fails to teach or suggest selecting a process condition based on a mask defect printability threshold and using a predetermined defect range as a selection criterion. The Applicant alleges both Pak and Park rely on post-exposure analysis and do not suggest selecting process conditions prior to inspection. The Applicant argues that there is no articulated reasoning or motivation to combine the teachings in the manner recited by the claim. The Examiner respectfully disagrees.
Claim 1 recites, in part, “inspecting a wafer that has been exposed by a lithography system using a mask and a selected process condition applied to the wafer, wherein the selected process condition has been: determined based on a mask defect printability; and acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus; and identifying, based on the inspection, a wafer defect that is caused by a defect on the mask to enable identification of the defect on the mask.” Pak discloses inspecting a wafer that has been exposed by a lithography system using a mask and a selected process condition applied to the wafer (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiple areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects), wherein the selected process condition has been: determined based on a mask defect printability (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiple areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects); and identifying, based on the inspection, a wafer defect that is caused by a defect on the mask to enable identification of the defect on the mask (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067]-[0071], the detected wafer defects caused by reticle defects are identified). Under the broadest reasonable interpretation, the claim language does not limit the selected process condition to a single selected process condition, and Pak discloses deliberately using modulated exposure values to which the defects are sensitive (see at least paras. [0060], [0064], [0067], [0081]-[0084]). Pak therefore discloses selected process conditions applied to the wafer determined based on a mask defect printability. However, Pak does not appear to explicitly describe wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus. Park discloses wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition (Figs. 1-10, abstract, paras. [0028]-[0030], [0034], [0037]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0055]-[0070], [0073]-[0084], different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners), wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus (Figs. 6-10, paras. [0055]-[0070], [0073]-[0084], claim 18, “any suitable commercially available method or system” (see para. [0059]) simulates the marginal focus and exposure conditions by simulating printing a wafer, and a further wafer is printed with process conditions to define target conditions to detect critical defects or particular defect types). The claim language does not require any specific criterion beyond “a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition.” For example, Park additionally states “the process window may be determined to include only those focus and exposure conditions at which no or only acceptable defects are printed” in para. [0055], and numbers of defects from the modulations are evaluated (para. [0063]). Park discloses a printing a FEM wafer using the lithography process, inspecting the wafer to detect defects, forming the process window based on the determined defects, determining the focus and exposure limits based on the determined process window (see, for example, Fig. 6 and paras. [0055]-[0058]). Park additionally discloses determining the process conditions to generate the process window by performing simulations of printing the wafer to determine an expected process window, simulating focus and exposure conditions to identify a rough window used to further define specifications and the process window (see Fig. 7 and paras. [0059]-[0060]) and describes printing a further FEM wafer with process conditions, comparing the detected defects, and determining the process window based on the detected defects (Fig. 7, paras. [0059]-[0063], [0065]).
To Applicant’s arguments with respect to the rationale to combine the teachings of Pak and Park to obtain the claimed invention, MPEP 2143(I)(A) pertains to combining prior art elements according to known methods to yield predictable results, and MPEP 2141.01(a) pertains to analogous and nonanalogous art. The Applicant has not provided specific arguments or evidence that the modification of Pak with the teachings of Park would render Pak unsatisfactory for its intended purpose. The claim language does not restrict the selected process condition to a single pre-selected process condition. Pak discloses using modulated exposure values to which the defects are known to be sensitive (see at least paras. [0060], [0064], [0067], [0081]-[0084]), and Park discloses determining the process conditions to generate the process window by performing simulations of printing the wafer and printing a FEM wafer (Fig. 7, paras. [0059]-[0060]), and Pak and Park are clearly both analogous to the claimed invention as they are both directed to the same field of endeavor of defect inspection (see Pak, Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0035], [0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], and see Park, Figs. 1-10, abstract, paras. [0028]-[0030], [0034]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0055]-[0065], [0068]-[0070], [0073]-[0084]). In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Park suggests that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus as taught by Park in selecting the process condition in the apparatus as taught by Pak since including wherein the selected process condition has been acquired based on experimentation or simulation such that a process condition that meets a criterion among various process conditions is selected to be the selected process condition, the criterion being a predetermined range of a number of defects to be identified in a predetermined wafer area when exposed with a corresponding process condition, wherein the experimentation or simulation can be performed by the apparatus or a system external to the apparatus is commonly used to improve patterning characterization within specification limits and can be used for pattern reliability checks (Park, para. [0052]) and to increase the signal-to-defect ratio by inspecting relevant modulations, thereby improving coverage of wafer variations, improve defect sampling, and improve review capability of systematic defects (Park, [0068], [0070]). Thus, Pak as modified by Park suggests the invention as currently recited in claim 1. Applicant’s arguments on these points have been fully considered, but they are not persuasive.
Applicant argues on pages 14-17 that Tam as modified by Park fails to suggest the invention as recited in claim 12. The Applicant alleges that Park fails to select “a process condition in advance based on a defectivity threshold, selecting a field based on a predetermined range of defects, or using empirical inspection results to determine a modulation condition” and alleges that Park’s adjustments are made in predefined process corners rather than on the basis of empirical inspection of individual fields. The Applicant alleges that Park fails to disclose “selecting a specific field that meets a defectivity criterion based on inspection, and determining a modulation condition from the process condition used to expose that selected field” and does not teach threshold-based decision-making required by the claim. The Applicant further contends that a reasoned rationale under MPEP 2141.01(a) has not been presented for why one of ordinary skill in the art would seek to combine the teachings of Tam and Park to arrive at the claimed invention, and the Applicant alleges the references serve different goals such that a combination would fail to yield the claimed invention. The Applicant also alleges the motivation to combine Park’s process condition selection is conclusory and does not provide the required motivation and that under MPEP 2143(I)(A), “a modification that undermines the purpose of the cited art cannot support a finding of obviousness.” The Examiner respectfully disagrees.
Claim 12 recites, in part, “determining a modulation condition based on a mask printability under the modulation condition, wherein the modulation condition is determined based on the inspection of the plurality of multiple fields of the test wafer, determining the modulation condition comprising: selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field; and determining a process condition used to expose the selected field to be the modulation condition.” Although Tam discloses determining a modulation condition based on a mask defect printability under the modulation condition, wherein the modulation condition is determined based on the inspection of the plurality of multiple fields of the test wafer (Figs. 1-8, paras. [0009]-[0025], [0039], [0061], [0091], [0093], [0094], [0099]-[0116], [0117]-[0124], [0126]-[0147], [0151]-[0160], the process includes determining focus and exposure values for the next PWQ wafer and the desired process window to be used in downstream production based on the focus and exposure values associated with the weak points identified from the metrology results), determining the modulation condition comprising: determining a process condition used to expose a selected field to be the modulation condition (Figs. 1-8, paras. [0009]-[0025], [0039], [0061], [0091], [0093], [0094], [0099]-[0116], [0117]-[0124], [0126]-[0147], [0151]-[0160], the process includes determining focus and exposure values for the next PWQ wafer and the desired process window to be used in downstream production based on the focus and exposure values associated with the weak points identified from the metrology results). Tam does not appear to explicitly describe a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition, selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field. The Examiner notes that the language “that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition” appears to be newly added to claim 12, and Pak discloses inspecting a plurality of multiple fields of a test wafer that have been exposed by a lithography system using a mask and a plurality of process conditions, wherein the plurality of multiple fields includes a first field that was exposed using a first process condition and a second field that was exposed using a second process condition different from the first process condition to identify a defect on a corresponding field (Figs. 1-6, paras. [0012]-[0014], [0020]-[0021], [0025], [0035], [0038]-[0040], [0043]-[0044], [0047], [0059]-[0061], [0064], [0067], [0081]-[0084], a reticle pattern is printed in multiples areas of a wafer using different values of a lithography process parameter and inspecting the resulting images on the wafer to detect defects of the reticle. Dose and focus values to which the defects are sensitive are used in the lithography process to detect the defects).
Park is relied upon to suggest selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field (Figs. 1-10, abstract, paras. [0028]-[0030], [0034]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0055]-[0065], [0068]-[0070], [0073]-[0084], claim 18, different dies are printed with different process conditions, and process conditions at secondary corners are used to discover defects when too many systematic defects are detected at the extreme corners. The selected die printed at secondary modulation conditions are compared to determine defects. Target conditions are defined to detect critical defects or particular defect types). The claim language does not require any specific criterion beyond “a predetermined range of a number of defects identified in the corresponding field.” Park additionally states “the process window may be determined to include only those focus and exposure conditions at which no or only acceptable defects are printed” in para. [0055], and numbers of defects from the modulations are evaluated (para. [0063]). Park describes printing a FEM wafer using the lithography process, inspecting the wafer to detect defects, forming the process window based on the determined defects, determining the focus and exposure limits based on the determined process window (see, for example, Fig. 6 and paras. [0055]-[0058]). Additionally, Park discloses determining a process window by simulating marginal focus and exposure conditions, printing a FEM wafer, comparing the detected defects and determining the process window based on the detected defects (Fig. 7, paras. [0059]-[0063], [0065]).
To Applicant’s arguments regarding the motivation for combining Tam and Park, the examiner notes that MPEP 2141.01(a) pertains to analogous and nonanalogous art. Tam and Park are clearly both analogous to the claimed invention as they are both directed to the same field of endeavor of defect inspection (Tam, Figs. 1-8, paras. [0014]-[0018], [0061], [0091], [0093], [0094], [0099]-[0124], [0126]-[0147], [0151]-[0160], and Park, Figs. 1-10, abstract, paras. [0028]-[0030], [0034]-[0041], [0044]-[0045], [0048]-[0049], [0052], [0055]-[0065], [0068]-[0070], [0073]-[0084]). The Applicant has not provided specific arguments or evidence that the combination of Tam as modified by Park would fail to yield the claimed invention and that the modification would undermine the purpose of Tam or that the modification of Tam with the teachings of Park would render Tam unsatisfactory for its intended purpose. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Park suggests the combination of selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field as taught by Park in determining the modulation condition in the operations performed by the non-transitory computer readable medium as taught by Tam as modified by Pak since including selecting a field that meets a criterion among the multiple fields, the criterion being a predetermined range of a number of defects identified in the corresponding field is commonly used to improve patterning characterization within specification limits and can be used for pattern reliability checks (Park, para. [0052]) and to increase the signal-to-defect ratio by inspecting relevant modulations, thereby improving coverage of wafer variations, improve defect sampling, and improve review capability of systematic defects (Park, paras. [0068], [0070]). The combination of Tam as modified by Pak in view of Park therefore suggests the invention as recited in claim 12. Applicant’s arguments on these points have been fully considered, but they are not persuasive.
Conclusion
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/CHRISTINA A RIDDLE/Primary Examiner, Art Unit 2882
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