DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on September 30th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on September 30th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 3-5, with respect to the rejections of claims under 35 U.S.C 102 (a)(2) have been considered but are moot in view of the new ground(s) of rejection.
Claim Objections
Claim 27 is objected to because of the following informalities: claim 27 recites “co-planer” in line 2 and should be amended to “coplanar” for correcting grammatical error. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 and 21-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitations “a conductive via embedded in a via hole of the first molding compound layer” in lines 2-3 and “a sidewall of the via hole spans from the first side to the second side” in lines 11-12. According to Applicant’s specification and Figs. 2E-2G, metal layers 122 that forming conductive vias are embedded and covered by first molding compound layer 130. There are no via holes existing in the first molding compound layer 130 for the meta layers 122 fill in or embedded in. Therefore, the limitation “a conductive via embedded in a via hole of the first molding compound layer” and “a sidewall of the via hole spans from the first side to the second side” are not described in the original specification and amended claim 1 recites new matter.
In view of the same reason above, claim 2 recites “a portion of the die connector is embedded in the via holes of the first molding compound layer” in lines 3-4 is also new matter and not being described in the original specification.
In view of the same reason above, claim 3 recites “the sidewall of the via hole is substantially perpendicular to the first side of the first molding compound layer” in lines 2-3 is also new matter and not being described in the original specification.
Claims 2-6 are also rejected for being depending on claim 1 and having the above issue incorporating into the claims.
Claim 21 recites the limitations “conductive vias, embedded in a via hole of the first molding compound layer, wherein the via holes extend from a first side of the first molding compound layer to a second side of the first molding compound layer” in line 3. According to Applicant’s specification and Figs. 2E-2G, metal layers 122 that forming conductive vias are embedded and covered by first molding compound layer 130. There are no via holes existing in the first molding compound layer 130 for the meta layers 122 fill in or embedded in. Therefore, the limitation “conductive vias, embedded in a via hole of the first molding compound layer, wherein the via holes extend from a first side of the first molding compound layer to a second side of the first molding compound layer” are not described in the original specification and amended claim 21 recites new matter.
Claims 22-27 are also rejected for being depending on claim 21 and having the above issue incorporating into the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (Pub. No.: US 2020/0176384 A1), hereinafter as Wu.
Regarding claim 1, Wu discloses a package in Fig. 1J, comprising: a first molding compound layer (combination of encapsulant 125 and protective layer 130) and a conductive via (a second conductive via 132b) embedded in a via hole (no via hole existing) of the first molding compound layer (see [0025-0026] and [0035]); a semiconductor device (first die 110) and a redistribution structure (RDL structure 160 and insulating structure 150) respectively disposed on opposite sides of the first molding compound layer, wherein the semiconductor device is electrically connected to the redistribution structure through the conductive via (see [0029-0030], [0040] and [0046-0047]); and a second molding compound layer (encapsulant 115) disposed on the first molding compound layer, wherein the semiconductor device is encapsulated by the second molding compound layer, wherein a first side of the first molding compound layer (bottom surface of protective layer 130) is in contact with a bottom surface of the second molding compound layer (top surface of encapsulant 115), a second side of the first molding compound layer (top surface of encapsulant 125) is in contact with a top surface of the redistribution structure (bottom surface of insulating structure 150) (see Fig. 1J in up-side down position and [0050]), and a sidewall of the via hole spans from the first side to the second side (there is no via hole when the conductive via embedded in encapsulant 125, but the sidewall of second conductive via 132b spans from the first side to the second side) (see Fig. 1J).
Regarding claim 3, Wu discloses the package according to claim 1, wherein the conductive via has a multilayer structure (seed layer and conductive material) (see [0027]), and the sidewall of the via hole is substantially perpendicular to the first side of the first molding compound layer (no via hole, but the sidewall of second conductive via 132b perpendicular to the bottom surface of protective layer 130) (see Fig. 1J).
Regarding claim 6, Wu discloses the package according to claim 1, wherein the redistribution structure comprises an insulating layer (PM1-PM4 made of BCB) and a redistribution layer (RDL1-RDL4) (see [0047]), wherein the Young's modulus of the first molding compound layer (encapsulant 125 made of epoxy resin) (see [0035]) is larger than the Young's modulus of the insulating layer (epoxy resin has higher young ‘s modulus than BCB).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (Pub. No.: US 2020/0176384 A1), hereinafter as Wu as applied to claim 1 above and in view of Ecton et al. (Pub. No.: US 2023/0197679 A1), hereinafter as Ecton.
Regarding claim 5, Wu discloses the package according to claim 1, but fails to disclose wherein the first molding compound layer comprises a polymer and inorganic fillers dispersed in the polymer.
Ecton discloses a package in Fig. 1, comprising: a first molding compound layer (layer 133-1) and a conductive via (combination of the lower 4 conductive lines 196, vias 194 and vias 152) embedded in the first molding compound layer (see [0017], [0029] and [0039]); wherein the first molding compound layer comprises a polymer and inorganic fillers dispersed in the polymer (insulating material 133 comprising an organic polymer with inorganic silica particles) (see [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the first molding compound layer (layer 133-1) of Ecton for making the first molding compound of the package of Wu because the modified structure would provide superior material for making electronic packaging by reducing coefficient of thermal expansion for improving mechanical strength and thermal stability.
Claim 21 and 23-27 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (Pub. No.: US 2020/0176384 A1), hereinafter as Wu as applied to claim 1 above in view of Ecton et al. (Pub. No.: US 2023/0197679 A1), hereinafter as Ecton, and further in view of LIU et al. (Pub. No.: US 2019/0051621 A1), hereinafter as Liu.
Regarding claim 21, Wu discloses a package in Fig. 1J, comprising: a first molding compound layer (combination of encapsulant 125 and protective layer 130) and conductive vias (second conductive vias 132b) embedded in via holes (no via holes existing) of the first molding compound layer extend from a first side of the first molding compound layer to a second side of the first molding compound layer (only the sidewall of vias 132b extend from top surface of encapsulant 125 to bottom surface of protective layer 130), (see [0025-0026] and [0035]); semiconductor devices (dies 110 and 120), disposed on the first side of the first molding compound layer and electrically connected to the conductive vias through die connectors (connectors 118), and a redistribution structure (RDL structure 160 and insulating structure 150), disposed on the second side of the first molding compound layer, wherein each of the conductive vias is in contact with the redistribution structure and a corresponding one of the die connectors (see [0021], [0029-0030], [0040] and [0046-0047]).
Wu fails to disclose inorganic fillers dispersed in the first molding compound, wherein the inorganic fillers of the first molding compound layer surround the conductive vias and the die connectors comprises solders.
Ecton discloses a package in Fig. 1, comprising: a first molding compound layer (layer 133-1) and a conductive via (combination of the lower 4 conductive lines 196, vias 194 and vias 152) embedded in the first molding compound layer (see [0017], [0029] and [0039]); wherein the first molding compound layer comprises a polymer and inorganic fillers dispersed in the polymer (insulating material 133 comprising an organic polymer with inorganic silica particles) and wherein the inorganic fillers of the first molding compound layer surround the conductive via (see [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the first molding compound layer (layer 133-1) of Ecton for making the first molding compound of the package of Wu because the modified structure would provide superior material for making electronic packaging by reducing coefficient of thermal expansion for improving mechanical strength and thermal stability.
The combination of Wu and Ecton fails to disclose the die connectors comprises solder.
Liu discloses a package comprising die connectors comprises solder (first conductive bump 104) (see Fig. 1 and [0026-0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate solder material of the die connectors of Liu for making the die connectors of Wu because the modified structure would provide a way for manufacturing electronic package with reliable and low cost material.
Regarding claim 23, the combination of Wu, Ecton and Liu discloses the package according to claim 21, further comprises: a second molding compound layer (encapsulant 115) disposed on the first molding compound layer, wherein the semiconductor devices are encapsulated by the second molding compound layer, and the first molding compound layer and the second molding compound layer comprise a same material (encapsulant 125 and encapsulant 115 comprises epoxy resin) (see Fig. 1J and [0024], [0035]).
Regarding claim 24, the combination of Wu, Ecton and Liu discloses the package according to claim 21, further comprises: a second molding compound layer (encapsulant 115) disposed on the first molding compound layer, wherein the semiconductor devices are encapsulated by the second molding compound layer, and the first molding compound layer is in contact with the second molding compound layer (see Fig. 1J and [0024], [0035]).
Regarding claim 25, the combination of Wu, Ecton and Liu discloses the package according to claim 21, wherein the first molding compound layer comprises a polymer and the inorganic fillers dispersed in the polymer (insulating material 133 comprising an organic polymer with inorganic silica particles) (see Ecton and [0029]).
Regarding claim 26, the combination of Wu, Ecton and Liu discloses the package according to claim 21, wherein the redistribution structure comprises an insulating layer (PM1-PM4 made of BCB) and a redistribution layer (RDL1-RDL4) (see [0047]), wherein the Young's modulus of the first molding compound layer (encapsulant 125 made of epoxy resin) (see [0035]) is larger than the Young's modulus of the insulating layer (epoxy resin has higher young ‘s modulus than BCB).
Regarding claim 27, the combination of Wu, Ecton and Liu discloses the package according to claim 21, wherein the second side of the first molding compound layer and bottom surfaces of the conductive vias co-planer (bottom surface of protective layer 130 and the top surface of encapsulant 115 are coplanar) (see Fig. 1J in up-side down view).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818