DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 5, 2026 has been entered.
Response to Arguments
RE: the objection to claim(s) 23, Applicant’s amendment and/or argument has been fully considered and resolve the typographical issue in this claim. Accordingly, the objection to claim(s) 23 has been withdrawn.
RE: the rejection of claim(s) 1, 2, 4, 7, 10-12, 21-23 under 35 USC 112(b), Applicant’s amendments and/or arguments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1, 2, 4, 7, 10-12, 21-23 has been withdrawn.
RE: the rejection of the claims under 35 USC 103, Applicant’s amendments and arguments have been fully considered but are moot in view of the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 7, 10, 12, 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220028842A1 (“Chang”) in view of US7023089B1 (“Lu”), and further in view of US 20200227338 A1 (“Gong”).
RE: Claim 1, Chang discloses A semiconductor package (400 in FIG. 13; FIGs. 2-13 show the process of making 400, [0005]), comprising:
an interposer substrate (the combination of 122, 300, 138, 150 in FIG. 13, hereinafter “interposer substrate”, [0061], [0063]; 122 is a redistribution structure including metallization patterns, [0025]; 300 includes substrate core 302 including metallization layers and vias, [0063]-[0065]; UBMs 138 are electrically coupled to vias 116 and dies 50, [0060]; 150 are conductive connectors, [0061]; Accordingly, the combination of 122, 300, 138, 150 functions as an interposer substrate and is therefore considered an interposer substrate under a broad reasonable interpretation);
a plurality of semiconductor dies (50, [0015]) disposed on the interposer substrate;
one or more heat dissipation elements (170) disposed on the plurality of semiconductor dies;
an encapsulant (combination of 120, 250) disposed on the interposer substrate and surrounding the plurality of semiconductor dies and the one or more heat dissipation elements; and
the interposer substrate comprises:
a semiconductor substrate (302; 302 is made of silicon, [0063]);
an interconnect structure (150, 138, [0095]) disposed between the semiconductor substrate and the plurality of semiconductor dies; and
a bonding structure (136 in 122; 136 is labeled in FIG. 6) disposed between the interconnect structure and the plurality of semiconductor dies and interfacing with the encapsulant (the hybrid bonding process may start by applying a surface treatment to the dielectric layer 136, [0038]; The anneal may further form covalent bonds between the passivation layer 68 and the dielectric layer 136, [0038]; Accordingly, 136 is a layer that directly bonds with passivation layer 68 and therefore, 136 is considered a bonding structure under a broad reasonable interpretation; FIG. 6 shows 136 interfacing with encapsulant 120).
Chang does not explicitly disclose:
a first backside metal layer disposed on the plurality of semiconductor dies;
a second backside metal layer disposed between the one or more heat dissipation elements and the first backside metal layer; and
a solder layer disposed between the first backside metal layer and the second backside metal layer, wherein:
an orthogonal projection of each of the first backside metal layer, the second backside metal layer and the solder layer on the interposer substrate along a thickness direction of the interposer substrate is equal to or larger than an orthogonal projection of the plurality of semiconductor dies on the interposer substrate along a thickness direction of the interposer substrate; and
the interposer substrate comprises:
through substrate vias penetrating through the semiconductor substrate.
However, Chang discloses heat spreaders 170 are attached to the dies 50 by a film 168, [0041].
Chang further discloses The film 168 may be a high-k polymer (e.g., a high-k DAF), a metal (e.g., In, Sn, or the like) attached by a reflow process, a thermal interface material (TIM), solder paste, or the like, [0041].
In the same field of endeavor, Lu discloses in FIG. 2:
a first backside metal layer (230) disposed on a semiconductor die (120; adhesion barrier layers 205, 230 may be required to adequately bond the base metal layers 210, 220 (e.g., the Sn layer) to the heat spreader 105 and/or the silicon die 120, Col. 5, lines 20-25);
a second backside metal layer (205) disposed between the one or more heat dissipation elements (105) and the first backside metal layer; and
a layer (110) disposed between the first backside metal layer and the second backside metal layer (a TIM layer 110 between the heat spreader 105 and the silicon die 120, Col. 4, lines 40-45; The base metal layers 210, 220 and the interlayer 215 may comprise various metals. The base metal may be selected from tin (Sn), Col. 4, lines 62-65; the interlayer may be a low melting point pure metal or alloy which may comprise lead (Pb), tin (Sn), indium (In), silver (Ag), gold (Au), or cadmium (Cd). Any combination of these metals may be used in accordance with the various embodiments of the present invention, Col. 5, lines 10-16; When heated to a predetermined bonding temperature, the interlayer metal 215 may liquify and diffuse into the base metal layers 210, 220. After a predetermined time period, the liquid interlayer 215 may diffuse completely into the base metals 210, 220 such that the two base metals 210, 220 bond together to form the TIM layer 110, Col. 4, lines 53-60).
Lu further discloses The adhesion barrier layers 205, 230 may comprise any material capable of strengthening the bond between the base metal layers 210, 220, and the heat spreader 105 and/or the silicon die 120; the adhesion barrier layers 205, 230 may also prevent inter-diffusion of molecules between the base metals 210, 220 and the heat spreader 105 interface and/or the base metals 210, 220 and the silicon die 120 interface. The adhesion barrier layers 205, 230 may include titanium (Ti), chromium (Cr), Col. 5, lines 24-34.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute each film 168 which is used as a TIM or solder paste with the adhesion barrier layers 205, 230 and the TIM 110 as taught by Lu in order to better adhere the TIMs to the heat spreaders 170 and/or dies 50 in Chang and prevent diffusion of molecules into the heat spreaders 170 and/or dies 50.
Further, the term “solder” is defined as “a metal or metallic alloy used when melted to join metallic surfaces; especially: an alloy of lead and tin so used.” In addition, “solder” is also defined as “something that unites.” See definitions 1 and 2 provided by Merriam-Webster’s dictionary available at <https://www.merriam-webster.com/dictionary/solder>, accessed on December 18, 2025.)
Accordingly, since in Lu 110 and/or its constituents were melted to join the adhesion barrier layers 205, 230 which are metal, and since 110 would be an alloy including lead (Pb) and tin (Sn), and since 110 unites the barrier layers 205, 230, under a broad reasonable interpretation, each TIM 110 would be considered a solder layer.
In the same field of endeavor, Gong discloses The multi-layered TIM may include at least a substrate material and an adhesion material (see abstract).
Accordingly, under a broad reasonable interpretation, the adhesion barrier layers 205, 230 and TIM 110 are considered to form a multi-layered TIM.
Gong further discloses a TIM stack 101 includes a material 105, and a material 110 over a surface 111 of material 105. Surface 111 has an area (e.g., X-Y plane) that defines a footprint of a dimensionalized pad comprising TIM stack 101. The footprint of TIM stack 101 may be any size suitable for a given IC package assembly. For example, TIM stack 101 may have a footprint of a few square millimeters sufficient for contacting a small IC die, up to around 1000 mm.sup.2, sufficient for contacting the majority of a large IC die surface, or multiple IC die surfaces, etc, [0021].
Gong further discloses the footprint of TIM stack 101 may be larger than the footprint of IC die 220, smaller than the footprint of IC die 220, or equal to the footprint of IC die 220, [0033].
Gong further discloses material 110 has substantially the same footprint as material 105, [0021].
Gong further discloses 105 may be considered a “substrate” or “base” material of a TIM stack, [0026] and the adhesion material deposited at block 520 may be expected to have precisely the same footprint as that of the substrate, [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each TIM stack, each including the adhesion barrier layers 205, 230 and TIM 110 so that within each stack, the adhesion barrier layers 205, 230 and TIM 110 have the same footprint as that of the respective die 50 underneath the TIM stack in order to form smoother side surfaces of the TIM stacks and prevent any gaps or voids between encapsulant 250 and the TIM stacks, thereby improving the connection between them.
As a result, the left die 50 and the right die 50 in FIG. 13 of Chang would each be under a respective first backside metal layer 230, and in combination these first backside metal layers 230 would be considered to correspond to the claimed first backside metal layer; the left die 50 and the right die 50 would each be under a respective solder layer 110, and in combination these solder layers 110 would be considered to correspond to the claimed solder layer; the left die 50 and the right die 50 would each be under a respective second backside metal layer 205, and in combination these second backside metal layers 205 would be considered to correspond to the claimed second backside metal layer.
As a result, an orthogonal projection of each of the first backside metal layer 230, the second backside metal layer 205 and the solder layer 110 on the interposer substrate along a thickness direction (i.e., vertical direction) of the interposer substrate would be equal to an orthogonal projection of the dies 50 on the interposer substrate along a thickness direction (i.e., vertical direction) of the interposer substrate in FIG. 13 Chang.
Further, Chang teaches 302 is a substrate core made of a semiconductor material such as silicon, [0063].
Chang further teaches substrate core 302 may also include metallization layers and vias (not shown), with the bond pads 304 being physically and/or electrically coupled to the metallization layers and vias, [0065].
Accordingly, as the vias are included in the substrate core 302, the vias are understood as being contained within the substrate core 302 (see definition 2 for “include” by Merriam-Webster, which defines “include” as “to contain between or within”). Under a broad reasonable interpretation, the vias would be within the silicon substrate core and therefore at least partially penetrate through the silicon substrate core 302.
RE: Claim 2, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein the number of the one or more heat dissipation elements is equal to the number of the plurality of semiconductor dies (In Chang FIG. 13 shows the number of 170 and the number of 50 are equal to two), and each of the heat dissipation elements is respectively overlapped with a corresponding semiconductor die among the plurality of semiconductor dies (FIG. 13 shows each 170 is overlapped with a corresponding 50).
RE: Claim 4, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 2, wherein the encapsulant is a stacked layer of a first encapsulant layer (In FIG. 13 of Chang: 120, [0039]) and a second encapsulant layer (250; In Chang FIG 13, encapsulants 250 and 120 are stacked, [0056]), rear surfaces of the plurality of semiconductor dies are level with a top surface of the first encapsulant layer (FIG. 13 of Chang shows rear / back / inactive surfaces of 50 level with the top surface of 120), and top surfaces of the heat dissipation elements are level with a top surface of the second encapsulant layer (FIG. 13 of Chang shows top surfaces of 170 level with a top surface of 250).
RE: Claim 7, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein the one or more heat dissipation elements are one or more silicon bulks (In Chang, 170 are made of silicon, [0041]).
RE: Claim 10, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein the number of the one or more heat dissipation elements is equal to the number of the plurality of semiconductor dies (In Chang FIG. 13 shows the number of 170 and the number of 50 are equal to two), and
the orthogonal projection of each of the first backside metal layer, the second backside metal layer and the solder layer on the interposer substrate along a thickness direction of the interposer substrate is equal to the orthogonal projection of the plurality of semiconductor dies on the interposer substrate along a thickness direction of the interposer substrate (As modified, an orthogonal projection of each of Lu’s first backside metal layer 230, the second backside metal layer 205 and the solder layer 110 on Chang’s interposer substrate in the thickness direction (i.e., vertical direction) of the interposer substrate in FIG. 13 Chang would be equal to an orthogonal projection of the dies 50 on the interposer substrate in the thickness direction (i.e., vertical direction) of the interposer substrate in FIG. 13 Chang).
RE: Claim 12, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein an outer edge of the encapsulant is aligned with an edge of the interposer substrate (In Chang, FIG. 13 shows outer edge of 120, 250 is aligned with an edge of 122 which is an edge of the interposer substrate).
RE: Claim 21, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein a distance between the one or more heat dissipation elements and the plurality of semiconductor dies along a stacking direction of the first backside metal layer and the second backside metal layer is equal to a total thickness of the first backside metal layer, the second backside metal layer and the solder layer (In Lu FIG. 2, the distance between heat spreader 105 and silicon die 120 along a stacking (vertical) direction of 230, 110, 205 is equal to a total thickness of 230, 110, 205; Accordingly, in FIG. 13 of Chang as modified by Lu, Gong, the distance between heat spreaders 170 and dies 50 along the stacking (vertical) direction of the first backside metal layer 230, the second backside metal layer 205 and the solder layer 110 would be equal to the total thickness of 230, 205, and 110).
RE: Claim 22, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein a sidewall surface of the solder layer is connected to the encapsulant (As modified, the sidewall surface of TIM 110 would be connected to 250 in FIG. 13 of Chang by being in direct contact with 250 and/or indirectly via 170).
RE: Claim 23, Chang, in view of Lu, Gong discloses The semiconductor package according to claim 1, wherein the solder layer is connected to the first backside metal layer and the second backside metal layer (In Lu FIG. 2, TIM 110 is connected to 205 and 230; Accordingly, in FIG. 13 of Chang as modified by Lu, Gong, TIM 110 would still be connected to 205 and 230).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Lu, in view of Gong as applied to claim 1, and further in view of US20070246735 A1 (“Yahata”).
RE: Claim 11, Chang, in view of Lu, Gong does not explicitly disclose The semiconductor package according to claim 1, wherein each of the first backside metal layer and the second backside metal layer is a stacked layer of two or more metallic layers.
In the same field of endeavor, Yahata discloses the barrier effect to the penetration/diffusion of the Sn can be enhanced by a barrier layer with a multilayer structure that the Ti layer and the Ni layer are alternately stacked as shown in FIG. 1C, [0013]. Yahata further discloses in the barrier layer composed as shown in FIG. 1C, the penetration/diffusion of Sn can be discontinued by the alternating barrier effects with different mechanism so as to prevent effectively the Sn penetration to the deep portion of the barrier layer, [0013].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each of the adhesion barrier layers 205, 230 to include a stacked layer of two or more metallic layers as taught by Yahata in order to better prevent diffusion of Sn from the TIM 110.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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