DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 8, 9, 21, and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) in view of Chan (U.S. PG Pub No US2022/0122895A1).
Regarding claim 1, Cheng teaches a method [see title, figs. 1-20], comprising:
forming fin structures (111) fig. 2 [0042] upwardly extending above a semiconductor substrate (110) fig. 1 [0037-0038];
forming an isolation structure (133) fig. 5 [0053] laterally surrounding lower portions of the fin structures (111);
conformally depositing a first dielectric layer (140) fig. 4 [0050] over the isolation structure (133) (at least partially over 133 in fig. 5);
conformally depositing a first dielectric layer over the fin structures (111);
depositing a flowable oxide (160) fig. 6 [0058-0059] over the first dielectric layer (140) and (laterally) between the fin structures (111);
performing, at a temperature lower than about 500°C (may be about 450 Celsius – about 800 Celsius [0070]), a steam annealing process [see fig. 10, 0068-0071] on the flowable oxide (160) to cure the flowable oxide (replace bonds under heat [0069-0073]);
after performing the steam annealing process [see fig. 10, 0068-0071], etching [see fig. 13, 0077-0079] the cured flowable oxide (165/160) [0073] until a top surface of the cured flowable oxide (165) is lower than top surfaces of the fin structures (111);
forming a second dielectric layer (190) fig. 16 [0084-0086] over the cured flowable oxide (165);
forming a first gate structure (left gate 210 hole-fill structure) fig. 17 [0087-0092] extending (partially, vertically) across a first one of the fin structures (left 111) and a second gate structure (right gate 210 hole-fill structure) fig. 17 [0087-0092] extending (partially, vertically) across a second one of the fin structures (right 111); and
forming first sources/drain regions on the first one of the fin structures (left 111) and second sources/drain regions [not shown, 0092] on the second one of the fin structures (right 111) (s/d regions not explicitly shown, however, [0092] indicates that multiple s/d may be formed, per device requirements [0092]),
and forming first source/drains regions [not shown, 0092] on the first one of the fin structures (left 111) and second source/drain regions [not shown, 0092] on the second one of the fin structures (right 111).
While Cheng does not explicitly disclose performing a steam annealing process “at a temperature lower than about 500°C”, [0070] of Cheng teaches performing the annealing process “in the range of about 450° C. to about 800° C” [0070 Cheng]. These ranges overlap. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process of Cheng to arrive at the claimed range - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
However, Cheng does not explicitly disclose wherein a bottom surface of the cured flowable oxide (165/160) [0073] is positioned higher than an interface between a bottom surface of one of the first source/drain regions and the top surface of one of the fin structures (source/drain regions not explicitly shown).
Chan teaches a method [see title, 0076] wherein a bottom surface of the cured flowable oxide (134) fig. 3H [0100, 0117] (134 is flowable oxide material [0100]; cured when incorporated in Cheng’s device) is positioned higher than an interface (see annotated fig. 3H below) between a bottom surface of one of the first source/drain regions (122) fig. 3H [0120] and the top surface of one of the fin structures (fin of 100) fig. 3H [0100] (see annotated fig. 3H below).
[AltContent: ][AltContent: textbox (133)][AltContent: arrow][AltContent: textbox (Fin-S/D interface)][AltContent: oval][AltContent: arrow][AltContent: textbox (Fin of 100)][AltContent: rect][AltContent: textbox (Local bottom of 134)][AltContent: rect][AltContent: arrow][AltContent: ]
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Annotated fig. 3h of Chan
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to include the formation of the source/drain features and adjacent insulation layers of Chan in order to improve the reliability of the source/drain contacts [0008] by reducing shorting [0007] and enhancing the electrical isolation of the FET circuitry [0089], as taught by Chan.
Regarding claim 4, Cheng teaches the method [see title, figs. 1-20] of claim 1. Cheng also teaches wherein the steam annealing process [see fig. 10, 0068-0071] is performed in a time duration less than about 2 hours (1 hour or less [0070]).
Regarding claim 8, Cheng teaches the method [see title, figs. 1-20] of claim 1. Cheng also teaches wherein the first dielectric layer (140) fig. 4 [0050] is made of metal oxide (may comprise Y, Sc, and/or Al-oxide impurities [0053-0056]).
Regarding claim 9, Cheng teaches the method [see title, figs. 1-20] of claim 1. Cheng also teaches wherein the second dielectric layer (190) fig. 16 [0084-0086] is made of metal oxide (such as HfO [0086]).
Regarding claim 21, Cheng teaches a method [see title, figs. 1-20], comprising:
forming fin structures (111) fig. 2 [0042] over a substrate (110) fig. 1 [0037-0038];
forming an isolation structure (133) fig. 5 [0053] laterally surrounding lower portions of the fin structures (111);
conformally depositing a first metal oxide layer (140) fig. 4 [0050] (may comprise Y, Sc, and/or Al-oxide impurities [0053-0056]) over the isolation structure (133);
after depositing the first metal oxide layer (140), filling a trench (middle gap between 111s) formed between first (left 111) and second (right 111) ones of the fin structures (111) with a dielectric material (160) fig. 6 [0058-0059] by using a flowable chemical vapor deposition (FCVD) process [0058-0059];
curing (replace bonds under heat [0069-0073]) the dielectric material (160) in a steam-containing ambient [see fig. 10, 0068-0071] at a temperature below about 500°C (may be about 450 Celsius – about 800 Celsius [0070]);
thinning down [see fig. 13, 0077-0079] the dielectric material (165/160) [0073] (by etching);
conformally depositing a second metal oxide layer (132) figs. 4-6[0053-0055, 0046-0050] (may comprise Y, Sc, and/or Al-oxide impurities [0053-0056]) over the thinned dielectric material (160) (in fig 13);
planarizing [see fig. 8, fig. 14, 0063, 0081] the first (140) and second (132) metal oxide layers to expose the fin structures (111);
forming first (left gate 210 hole-fill structure and surrounding top of left 111) fig. 17 [0087-0092] and second (right gate 210 hole-fill structure and surrounding top of right 111) fig. 17 [0087-0092] gate structures around (tops of) the first and second ones of the fin structure, respectively; and
forming first sources/drain regions [not shown, 0092] on the first one of the fin structures (left 111) and second sources/drain regions [not shown, 0092] on the second one of the fin structures (right 111) (s/d regions not explicitly shown, however, [0092] indicates that multiple s/d may be formed, per device requirements [0092]).
While Cheng does not explicitly disclose performing a steam annealing process “at a temperature lower than about 500°C”, [0070] of Cheng teaches performing the annealing process “in the range of about 450° C. to about 800° C” [0070 Cheng]. These ranges overlap. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process of Cheng to arrive at the claimed range - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
However, Cheng does not explicitly disclose forming a contact etch stop layer over one of the first source/drain regions [not shown, 0092], wherein a top surface of the thinned dielectric material (165/160) is positioned higher than an interface between a top surface of the one of the first source/drain regions [not shown, 0092] and the contact etch stop layer.
Chan teaches a method [see title, 0076] comprising forming a contact etch stop layer (133) fig. 3A [0097] over one of the first source/drain regions (122) fig 3A [0098], wherein a top surface of the thinned dielectric material (134) fig. 3H [0100] (polished) is positioned higher than an interface between a top surface of the one of the first source/drain regions (122) and the contact etch stop layer (133) (see annotated fig. 3H below).
[AltContent: arrow][AltContent: oval][AltContent: textbox (Interface of 133 and 122)][AltContent: ][AltContent: textbox (133)][AltContent: arrow][AltContent: textbox (Fin-S/D interface)][AltContent: oval][AltContent: arrow][AltContent: textbox (Fin of 100)][AltContent: rect][AltContent: textbox (Local bottom of 134)][AltContent: rect][AltContent: arrow][AltContent: ]
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Annotated fig. 3h of Chan
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to include the formation of the source/drain features and adjacent insulation layers of Chan in order to improve the reliability of the source/drain contacts [0008] by reducing shorting [0007] and enhancing the electrical isolation of the FET circuitry [0089], as taught by Chan.
Regarding claim 26, Cheng teaches a method [see title, figs. 1-20], comprising:
forming fin structures (111) fig. 2 [0042] over a substrate (110) fig. 1 [0037-0038];
forming an isolation structure (133) fig. 5 [0053] laterally surrounding lower portions of the fin structures (111);
conformally depositing a first dielectric layer (140) fig. 4 [0050] (see also fig. 5) over the isolation structure (133) and the fin structures (111);
depositing a flowable oxide material (160) fig. 6 [0058-0059] over the first dielectric layer (140);
performed an annealing process [see fig. 10, 0068-0071] on the flowable oxide material (160) in a steam-containing ambient [see fig. 10, 0068-0071] at a temperature below about 500°C (may be about 450 Celsius – about 800 Celsius [0070]);
thinning down [see fig. 13, 0077-0079] the flowable oxide material (165/160) [0073] (by etching);
conformally depositing a second dielectric layer (132) figs. 4-6 [0053-0055, 0046-0050] (may comprise Y, Sc, and/or Al-oxide impurities [0053-0056]) over the thinned flowable oxide material (160) (in fig 13);
planarizing [see fig. 8, fig. 14, 0063, 0081] the first (140) and second (132) dielectric layers to expose the fin structures (111), such that the first dielectric layer (140) cupping an underside of the flowable oxide material (160/165) and has a U-shaped profile from a cross-sectional view (in fig. 8, 14);
forming first (left gate 210 hole-fill structure and surrounding top of left 111) fig. 17 [0087-0092] and second (right gate 210 hole-fill structure and surrounding top of right 111) fig. 17 [0087-0092] gate structures around (tops of) the first and second ones of the fin structure, respectively; and
forming first source/drain regions [not shown, 0092] on the first one of the fin structures (left 111) and second source/drain regions [not shown, 0092] on the second one of the fin structures (right 111) (s/d regions not explicitly shown, however, [0092] indicates that multiple s/d may be formed, per device requirements [0092]).
While Cheng does not explicitly disclose performing a steam annealing process “at a temperature lower than about 500°C”, [0070] of Cheng teaches performing the annealing process “in the range of about 450° C. to about 800° C” [0070 Cheng]. These ranges overlap. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process of Cheng to arrive at the claimed range - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
However, Cheng does not explicitly disclose wherein the first dielectric layer (140) interfaces with a sidewall of one of the first source/drain regions (not shown).
Chan teaches a method [see title, 0076] wherein the first dielectric layer (132) fig. 3H [0092] interfaces with a sidewall of one of the first source/drain regions (122) fig 3A [0098].
[AltContent: arrow][AltContent: arrow][AltContent: textbox (132)][AltContent: textbox (132)][AltContent: ][AltContent: textbox (133)][AltContent: arrow][AltContent: textbox (Fin-S/D interface)][AltContent: oval][AltContent: arrow][AltContent: textbox (Fin of 100)][AltContent: rect][AltContent: textbox (Local bottom of 134)][AltContent: rect][AltContent: arrow][AltContent: ]
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Annotated fig. 3h of Chan
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to include the formation of the source/drain features and adjacent insulation layers of Chan in order to improve the reliability of the source/drain contacts [0008] by reducing shorting [0007] and enhancing the electrical isolation of the FET circuitry [0089], as taught by Chan.
Regarding claim 27, Cheng teaches the method [see title, figs. 1-20] of claim 26. Cheng also teaches wherein after thinning down [see fig. 13, 0077-0079] the flowable oxide material (165/160) [0073], the first dielectric layer (140) fig. 4 [0050] has a thinner thickness than the flowable oxide material (160).
Regarding claim 28, Cheng teaches the method [see title, figs. 1-20] of claim 26. Cheng also teaches wherein the first dielectric layer (140) fig. 4 [0050] has a thickness in a range from about 3 nm to about 5 nm (2-10 nm encompasses range [0051]).
While Cheng does not explicitly disclose performing a steam annealing process “wherein the first dielectric layer has a thickness in a range from about 3 nm to about 5 nm”, [0051] of Cheng discloses that the dielectric layer 140 can have a thickness “in the range of about 2 nm to about 10 nm” [0051 Cheng]. These ranges overlap. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized thickness of the dielectric layer of Cheng to arrive at the claimed range - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
Claims 2-3 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claims 1 and 21 above, and further in view of Ryan (U.S. PG Pub No US2016/0099168A1) (of record).
Regarding claim 2, Cheng teaches the method [see title, figs. 1-20] of claim 1. However, Cheng does not explicitly disclose further comprising:
after performing the steam annealing process [0018], performing a dry annealing process on the flowable oxide (160) fig. 6 [0058-0059] under a higher temperature than the steam annealing process (carried out at 450C-800C).
Ryan teaches a method [see title, 0018] further comprising:
after performing the steam annealing process [0018], performing a dry annealing process on the flowable oxide [0018] under a higher temperature (500C-1200C) [0018] than the steam annealing process (carried out at 400-700C) [0018].
While Ryan does not explicitly disclose performing a dry annealing process “under a higher temperature than the steam annealing process”, [0018] of Ryan teaches performing the dry annealing process “at a temperature of about 500° C to 1200° C” [0018 Ryan] and the steam annealing process “at a temperature of about 400° C. to 700° C”. These ranges have implied values that address the claimed condition of the dry annealing process taking place at a higher temperature than the steam annealing process. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process(es) of Ryan to meet the claimed condition - in the absence of any evidence of criticality for the claimed condition/range (See MPEP 2144.05, I).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the annealing of the flowable oxide material of Cheng to include the additional dry annealing step(s) of Ryan [0018] in order to facilitate extra cross-linkage [0018] of the flowable oxide material [0018], as taught by Ryan.
Regarding claim 3, Cheng teaches the method [see title, figs. 1-20] of claim 2. Cheng in view of Ryan (with reference to Ryan) also teaches wherein the dry annealing process is performed at a temperature lower than about 800°C (down to 500C) [0018].
While Ryan does not explicitly disclose performing a dry annealing process “at a temperature lower than about 800°C”, [0018] of Ryan teaches performing the dry annealing process “at a temperature of about 500° C to 1200° C” [0018 Ryan]. These ranges overlap. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process(es) of Ryan to arrive at the claimed range - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
Regarding claim 22, Cheng teaches the method of claim 21. However, Cheng does not explicitly disclose wherein after curing the dielectric material (160) fig. 6 [0058-0059], annealing the dielectric material (160) fig. 6 [0058-0059] in a steam-free ambient at a first temperature, and the first temperature is higher than about 500°C.
Ryan teaches a method [see title, 0018] further comprising:
after curing the dielectric material (“oxide”) [0018], annealing the dielectric material (“oxide”) [0018] in a steam-free ambient at a first temperature (dry annealing after steam annealing [0018]), and the first temperature is higher than about 500°C (up to about 1200°C) [0018].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the annealing of the flowable oxide material of Cheng to include the additional dry annealing step(s) of Ryan [0018] in order to facilitate extra cross-linkage [0018] of the flowable oxide material [0018], as taught by Ryan.
Regarding claim 23, Cheng teaches the method [see title, figs. 1-20] of claim 22. Cheng in view of Ryan (with reference to Ryan) also teaches wherein the FCVD process [0058-0059] is (in steam-annealing part of material formation) [0018] performed at a second temperature (400-700C) [0018] lower than the first temperature (up to about 1200°C) [0018].
While Ryan does not explicitly disclose performing a deposition process ‘at a temperature lower than the annealing process’, [0018] of Ryan teaches performing the dry annealing process “at a temperature of about 500° C to 1200° C” [0018 Ryan] and the portion of the deposition process “at a temperature of about 400° C. to 700° C”. These ranges have implied values that address the claimed condition of the dry annealing process taking place at a higher temperature than the steam annealing process. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized temperature range for the annealing process of Ryan to meet the claimed condition - in the absence of any evidence of criticality for the claimed condition/range (See MPEP 2144.05, I).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claim 1 above, and further in view of Yan (U.S. PG Pub No US2016/0099143A1) (of record).
Regarding claim 5, Cheng teaches the method [see title, figs. 1-20] of claim 2. However, Cheng does not explicitly disclose wherein the steam annealing process is performing in an ambient having a H2O concentration in a range from about 5 % to about 100 %.
Yan teaches a method [see title] wherein the steam annealing process [0092] is performing in an ambient having a H2O concentration in a range from about 5 % to about 100 % (10-50%) [0092].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to have performed the steam annealing process in an ambient having a concentration of about 10-50% water [0092] in order to improve film quality and decrease wet etch rate ratio [0092] according to art-recognized parameters [0092], as taught by Yan.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claim 1 above, and further in view of Kanakasabapathy (U.S. PG Pub No US2015/0236018A1) (of record).
Regarding claim 6, Cheng teaches the method [see title, figs. 1-20] of claim 1. However, Cheng does not explicitly disclose wherein depositing the flowable oxide (160) fig. 6 [0058-0059] is performed with precursors comprising tri-silylamine, ammonia, and oxygen.
Kanakasabapathy teaches a method [see title] wherein depositing the flowable oxide (610) fig. 8 [0032] (of silicon oxide) is performed with precursors comprising tri-silylamine, ammonia, and oxygen [0032].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to have performed the FCVD process using the art-recognized chemicals and deposition parameters [0032] of Kanakasabapathy in order to effectively produce the flowable oxide with an enhanced degree of short chained polymers [0032], as taught by Kanakasabapathy.
Regarding claim 7, Cheng teaches the method [see title, figs. 1-20] of claim 1. However, Cheng does not explicitly disclose wherein depositing the flowable oxide (160) fig. 6 [0058-0059] is performed at a temperature in a range from about 10°C to about 500°C (temperature not specified).
Kanakasabapathy teaches a method [see title] wherein depositing the flowable oxide (610) fig. 8 [0032] (of silicon oxide) is performed at a temperature in a range from about 10°C to about 500°C (about 50 degrees C) [0032].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng to have performed the FCVD process using the art-recognized chemicals and deposition parameters [0032] of Kanakasabapathy in order to effectively produce the flowable oxide with an enhanced degree of short chained polymers [0032], as taught by Kanakasabapathy.
Claims 10, 25, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claims 1, 21, and 26 above, and further in view of Sun (U.S. PG Pub No US2019/0131140A1) (of record)
Regarding claim 10, Cheng teaches the method [see title, figs. 1-20] of claim 1. However, Cheng does not explicitly disclose wherein the flowable oxide (160) fig. 6 [0058-0059] comprises sulfur (Silicon-oxide based polymer instead) [0058, 0056].
Sun teaches a method [see title, 0001] wherein the flowable oxide (106) fig. 1a [0227] comprises sulfur (group-IV oxide with impurities such as sulfur [0224, 0227]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng such that the oxide material comprises impurities such as sulfur [0227] in order to fine-tune the material’s etching resistance properties [0227], as taught by Sun.
Regarding claim 25, Cheng teaches the method [see title, figs. 1-20] of claim 21. However, Cheng does not explicitly disclose wherein the first metal oxide (140) fig. 4 [0050] layer comprises sulfur (GeO instead) [0050].
Sun teaches a method [see title, 0001] wherein the first metal oxide (106) fig. 1a [0227] layer comprises sulfur (group-IV oxide with impurities such as sulfur [0224, 0227]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng such that the oxide material comprises impurities such as sulfur [0227] in order to fine-tune the material’s etching resistance properties [0227], as taught by Sun.
Regarding claim 30, Cheng teaches the method [see title, figs. 1-20] of claim 26. However, Cheng does not explicitly disclose wherein the second dielectric layer (190) fig. 16 [0084-0086] comprises sulfur (silicon oxide instead [0086]).
Sun teaches a method [see title, 0001] wherein the second dielectric layer (106) fig. 1a [0227] comprises sulfur (group-IV oxide with impurities such as sulfur [0224, 0227]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Cheng such that the oxide material comprises impurities such as sulfur [0227] in order to fine-tune the material’s etching resistance properties [0227], as taught by Sun.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claim 21 above, and further in view of Bi (U.S. PG Pub No US2020/0144124A1).
Regarding claim 24, Cheng teaches the method [see title, figs. 1-20] of claim 21. However, Cheng does not explicitly disclose wherein the fin structures (111) are made of silicon germanium [0043] having a germanium atomic concentration in a range from about 17% to about 30% [0042] (range not disclosed).
Bi teaches a method [see title, 0047] wherein the fin structures (106) fig. 1 [0047] have a germanium atomic concentration in a range from about 17% to about 30% (about 10 to about 80 percent) [0047].
While Bi does not explicitly disclose performing a steam annealing process “wherein the fin structures (106) fig. 1 [0047] have a germanium atomic concentration in a range from about 17% to about 30%”, [0047] of Bi discloses that the fin structures 106 can be comprised of silicon germanium with germanium “having a germanium concentration of about 10 to about 80 percent” [0047 Bi]. These ranges overlap.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized Ge:Si ratio of the fin structures of Cheng with the teachings of Bi [0047 Bi] to arrive at the claimed range – in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0164843A1) (of record) modified by Chan (U.S. PG Pub No US2022/0122895A1), as applied in claim 26 above, and further in view of Ching (U.S. PG Pub No US2020/0395359A1) (of record).
Regarding claim 29, Cheng teaches the method [see title, figs. 1-20] of claim 26. However, Cheng does not explicitly disclose wherein after thinning down the flowable oxide material (160) fig. 6 [0058-0059], the flowable oxide material (160) fig. 6 [0058-0059] has a thickness in a range from about 7 nm to about 13 nm (could be reduced significantly depending on fin height variation [0079], but range not disclosed).
Ching teaches a method [see title] wherein after thinning down (planarizing) the flowable oxide material (148) fig. 6B [0026, 0086], the flowable oxide material (148) [0086] has a thickness in a range from about 7 nm to about 13 nm (3 nm to about 40 nm [0086 Ching], which encompasses the claimed range).
While Ching does not explicitly disclose the flowable oxide material (148) [0086] has a thickness in a range from about 7 nm to about 13 nm, [0086] of Ching discloses “the planarized second flowable oxide layer in the recess has a thickness in a range from about 3 nm to about 40 nm after planarizing the first and second dielectric layers is complete”. These ranges overlap.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the art-recognized thickness of the flowable oxide layer of Cheng to have a thickness in the claimed range as taught by Ching [0086] - in the absence of any evidence of criticality for the claimed range (See MPEP 2144.05, I).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 21, and 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior arts made of record on the PTO-892 and not relied upon are considered pertinent to applicant's disclosure are considered relevant to the present disclosure because they all disclose methods applied to the formation of oxide materials.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 02/15/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892