DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1-6 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0204215 (“Chang”) in view of US 2023/0113965 (“Liu”). 3
IV. Allowable Subject Matter 12
V. Response to Arguments 12
VI. Pertinent Prior Art 13
Conclusion 13
[The rest of this page is intentionally left blank.]
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 06/17/2026 has been entered.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-6 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0204215 (“Chang”) in view of US 2023/0113965 (“Liu”).
Claim 1 reads,
1. (Currently Amended) A method for manufacturing a semiconductor device, comprising:
[1a] forming a semiconductor structure that includes a base portion and a plurality of protrusions,
[1b] the plurality of protrusions being protruded from the base portion and including a semiconductor material,
[1c] two adjacent ones of the plurality of protrusions being spaced apart from each other in a predetermined direction to have a first recess therebetween;
[2] depositing metal sputtered from a metal target on the semiconductor structure, so as to fill the first recess;
[3] performing a chemical reaction on the metal deposited on the semiconductor structure to turn the metal into dielectric that serves as an isolation;
[4] etching the isolation to form a second recess that extends lengthwise in the predetermined direction; and
[5a] forming a gate structure over the plurality of protrusions and filling the second recess,
[5b] the gate structure extending lengthwise in the predetermined direction.
With regard to claim 1, Chang discloses, generally in Figs. 7-17,
1. (Currently Amended) A method for manufacturing a semiconductor device, comprising:
[1a] forming a semiconductor structure 1010/1020 that includes a base portion 1010 and a plurality of protrusions 1020 [¶¶ 97-98; Fig. 7],
[1b] the plurality of protrusions 1020 being protruded from the base portion 1010 and including a semiconductor material [i.e. silicon (¶ 98)],
[1c] two adjacent ones of the plurality of protrusions being spaced apart from each other in a predetermined direction to have a first recess therebetween [recess is shown between fins 1020 but not labeled];
[2] depositing …[a dielectric material 1050 (¶ 100)]… on the semiconductor structure 1010/1020, so as to fill the first recess [Fig. 8];
[3] … [the]… dielectric 1050 that serves as an isolation 1050 [¶¶ 100-102; Figs. 8-9];
[4] etching the isolation 1050 to form a second recess 1055 [¶ 115; Fig. 16] that extends lengthwise in the predetermined direction [as shown in Fig. 16]; and
[5a] forming a gate structure 1040 [¶¶ 120-121] over the plurality of protrusions 1020 and filling the second recess 1055 [as shown in Fig. 17],
[5b] the gate structure 1040 extending lengthwise in the predetermined direction.
With regard to features [2]-[3] of claim 1 and claims 2-6 and 8, Chang does not form the isolation 1050 in the manner claimed in features [2]-[3], as further limited by claims 2-6 and 8.
Liu is directed to the same endeavor as that in the Instant Application of forming a seamless dielectric fill in recesses for forming electrical isolation structures in semiconductor substrates (Instant Application: ¶ 39; Liu: abstract; ¶¶ 1-5). Liu further teaches that the seamless nature provides better electrical isolation (Liu: abstract; ¶¶ 1-5). Liu further teaches that the process of forming said dielectric in said narrowly-spaced recesses includes the processes of features [2]-[3] of claim 1, as follows:
[2] depositing metal 304A [Liu: ¶ 24] sputtered from a metal target [Liu: 604 in Fig. 6A (¶ 33) and 965 in rectangle (should be “914”) in Fig. 6B (Liu: ¶ 37); see explanation below] on the semiconductor structure 202, so as to fill the first recess 204 [Liu: ¶ 24] [as shown in Fig. 3 of Liu]
[3] performing a chemical reaction [i.e. oxidation or nitridation (¶ 26; Fig. 4)] on the metal 304A deposited on the semiconductor structure 202 to turn the metal 304A into dielectric 304A-T that serves as an isolation;
While Liu does not state that the substrate 202 is a semiconductor substrate, Liu states that it is the point of the invention disclosed in Liu to process semiconductor substrates, at least for the purposes of forming dielectric isolations in semiconductor substrates, stating in this regard,
[0001] Embodiments of the present principles generally relate to semiconductor processing of semiconductor substrates.
[0002] Various dielectric materials are used in semiconductor features to facilitate in electrically isolating structures. …
(Liu: ¶¶ 1, 2; emphasis added)
Liu states,
[0026] In block 104, the seamless metal gap fill is treated by oxidizing or nitridizing the metal material of the seamless metal gap fill with an oxidation process or a nitridation process to form a dielectric gap fill with a seamless high-k dielectric material. For the sake of brevity, examples of some embodiments may be given using oxidation processes but are not meant to be limiting as nitridation processes may be used as well to convert the metal material to a seamless dielectric material. In some embodiments for a single cycle process, the full seamless metal gap fill 304A is treated 402A by a thermal process or a plasma-assisted process to convert the metal material of the full seamless metal gap fill 304A into a seamless dielectric gap fill of treated full seamless metal gap fill 304A-T from top to bottom as depicted in a view 400A of FIG. 4.
(Liu: ¶ 26; emphasis added)
With regard to claims 2-5, Liu further teaches,
2. (Original) The method according to claim 1, wherein the metal sputtered from the metal target is ionized [Liu: abstract; ¶¶ 5, 7, 9, 11, 23-25, 31, claim 1; i.e. “high metal ionization”].
3. (Original) The method according to claim 1, wherein the semiconductor structure 202 is biased with a voltage while the metal is being sputtered and deposited [Liu: Fig. 6B; ¶ 38; ¶ 40: “An RF power source 980 may be coupled to the process chamber 902 through the substrate support 908 to provide a bias power between the target 914 and the substrate support 908.”].
4. (Original) The method according to claim 1, wherein the metal sputtered from the metal target [rectangular structure with “965” at top of chamber in Fig. 6B, which should be labeled “914” (see explanation under feature [1] of claim 1, above)] is collimated [by collimator 918] to travel in a direction perpendicular to the semiconductor structure 202 [Liu: ¶¶ 36-37; Fig. 6B].
5. (Original) The method according to claim 1, wherein the metal is sputtered and deposited under a pressure that falls within a range of from 50 mtorr to 400 mtorr [Liu: ¶¶ 7, 24, 33, claims 3 and 14; i.e. 50 mTorr to 500 mTorr].
6. (Original) The method according to claim 1, wherein the metal is sputtered and deposited at a temperature that falls within a range of from 18 ℃ to 450 ℃ [Liu: ¶ 40; i.e. 20 ℃ to 400 ℃].
8. (Currently Amended) The method according to claim 1, wherein the chemical reaction is performed at a temperature that falls within a range of from 18 °C to 300 °C [Liu: ¶ 40; i.e. 20 ℃ to 400 ℃].
Thus the claimed range falls within the range disclosed in Liu. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the dielectric material forming the isolation 1050 in Chang using the metal sputter/oxidation or nitridation process taught in Liu, in order to form an isolation that is seamless and therefore having better isolation characteristics than those formed by CVD, as taught in Liu (¶ 2), which is one of the inferior processes used in Chang to form the isolation 1050 (Chang: ¶ 100). As such, Liu may be seen as an improvement to Chang in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 1-6 and 8.
Claim 17 reads,
17. (Currently Amended) A method for manufacturing a semiconductor device, comprising:
[1a] forming a semiconductor structure that includes a base portion and a plurality of protrusions,
[1b] the plurality of protrusions being protruded from the base portion and including a semiconductor material,
[1c] two adjacent ones of the plurality of protrusions being spaced apart from each other to have a first recess therebetween;
[2] depositing metal sputtered from a metal target on the semiconductor structure, so as to fill the first recess;
[3] performing a chemical reaction on the metal deposited on the semiconductor structure to turn the metal into dielectric;
[4] etching the dielectric to form a second recess; and
[5a] forming a gate structure over the plurality of protrusions and filling the second recess,
[5b] the gate structure intersecting the two adjacent ones of the plurality of protrusions.
Claim 17 is merely broader than claim 1. As such, each of the limitations of claim 17 have been addressed above in rejecting claim 1.
With regard to claims 18-20, Liu further discloses,
18. (Previously Presented) The method according to claim 17, wherein the metal target 604 includes at least one of Hf, Zr, Ti or W [Liu: ¶ 33].
19. (Original) The method according to claim 17, wherein the chemical reaction includes nitridation [Liu: ¶ 26, supra].
20. (Original) The method according to claim 17, wherein the metal sputtered from the metal target is ionized [Liu: abstract; ¶¶ 5, 7, 9, 11, 23-25, 31, claim 1; i.e. “high metal ionization”].
Again, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the dielectric material forming the isolation 1050 in Chang using the metal sputter/oxidation or nitridation process taught in Liu, in order to form an isolation that is seamless and therefore having better isolation characteristics than those formed by CVD, as taught in Liu (¶ 2), which is one of the inferior processes used in Chang to form the isolation 1050 (Chang: ¶ 100). As such, Liu may be seen as an improvement to Chang in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 17-20.
Claim 9 reads,
9. (Currently Amended) A method for manufacturing a semiconductor device, comprising:
[1a] forming a semiconductor structure that includes a base portion and a plurality of protrusions,
[1b] the plurality of protrusions being protruded from the base portion, including a semiconductor material, and
[1c] extending lengthwise in a first direction;
[2a] forming a plurality of gate structures on the semiconductor structure,
[2b] the plurality of gate structures extending lengthwise in a second direction different from the first direction,
[2c] two adjacent ones of the plurality of gate structures being spaced apart from each other in the second direction to have a recess therebetween;
[3] depositing metal sputtered from a metal target on the plurality of gate structures and the semiconductor structure having a recess, so as to fill the recess; and
[4] performing a chemical reaction on the metal deposited on the plurality of gate structures and the semiconductor structure to turn the metal into dielectric.
With regard to claim 9, Chang discloses,
9. (Currently Amended) A method for manufacturing a semiconductor device, comprising:
[1a] forming a semiconductor structure 1010/1020 that includes a base portion 1010 and a plurality of protrusions 1020 [¶¶ 97-98; Fig. 7],
[1b] the plurality of protrusions 1020 being protruded from the base portion 1010 and including a semiconductor material [i.e. silicon (¶ 98)],
[1c] extending lengthwise in a first direction [direction shown in Figs. 10A and 10C];
[2a] forming a plurality of gate structures 1110 on the semiconductor structure 1010/1020 [Figs. 10A-13; ¶¶ 103-111],
[2b] the plurality of gate structures 1110 extending lengthwise in a second direction different from the first direction [i.e. the second direction is perpendicular to the first direction, as shown in Figs. 10A-10C],
[2c] two adjacent ones of the plurality of gate structures 1110 being spaced apart from each other in the second direction to have a recess [i.e. “opening 1030”] therebetween [Fig. 13; ¶ 111];
[3] depositing …[dielectric material 1060]… on the plurality of gate structures and the semiconductor structure having a recess, so as to fill the recess 1030 [(¶¶ 112-113 Fig. 14]; and
[4] … [not taught] …
With regard to features [3]-[4] of claim 9 and claims 11-15, Chang does not disclose the claimed metal sputtering to fill the recess 1030 followed by a chemical reaction to convert the sputtered metal fill into the dielectric 1060.
As explained above, Liu is directed to the same endeavor as that in the Instant Application of forming a seamless dielectric fill in recesses for forming electrical isolation structures in semiconductor substrates (Instant Application: ¶ 39; Liu: abstract; ¶¶ 1-5). Liu further teaches that the seamless nature provides better electrical isolation (Liu: abstract; ¶¶ 1-5).
As above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the dielectric material 1060 forming the gate cut isolation 1060 in Fig. 14 of Chang using the metal sputter/oxidation or nitridation process taught in Liu, in order to form a isolation that is seamless and therefore has better isolation characteristics than those formed by CVD, as taught in Liu (¶ 2), which is one of the inferior processes used in Chang to form the isolation 1060 (Chang: ¶ 112). As such, Liu may be seen as an improvement to Chang in this aspect. (See MPEP 2143.)
Thus, Chang modified to use the process of Liu to form the gate cut dielectric 1060 of Chang teaches features [3]-[4] of claim 9 as well as claims 10-15, as follows:
[3] depositing metal [304A of Liu] sputtered from a metal target [604 of Liu in Fig. 6A (¶ 33) and 965 in rectangle (should be “914”) in Fig. 6B (Liu: ¶ 37); see explanation above] on the plurality of gate structures [1110 of Chang in Fig. 13] and the semiconductor structure [1010/1020 of Chang in Fig. 13], so as to fill the recess [1030 of Chan in Fig. 13]; and
[4] performing a chemical reaction on the metal [304A of Liu] deposited on the plurality of gate structures [1110 of Chang in Fig. 13] and the semiconductor structure [1010/1020 of Chang in Fig. 13] to turn the metal [304A of Liu] into dielectric [304A-T in Fig. 4 of Liu that is 1060 in Fig. 14 of Chang].
10. (Original) The method according to claim 9, wherein the metal [304A of Liu] sputtered from the metal target [604, 965 (should be “914”) of Liu] is ionized [Liu: abstract; ¶¶ 5, 7, 9, 11, 23-25, 31, claim 1; i.e. “high metal ionization”].
11. (Original) The method according to claim 9, wherein the semiconductor structure is biased with a voltage while the metal is being sputtered and deposited [Liu: Fig. 6B; ¶ 38; ¶ 40: “An RF power source 980 may be coupled to the process chamber 902 through the substrate support 908 to provide a bias power between the target 914 and the substrate support 908.”].
12. (Original) The method according to claim 9, wherein the metal sputtered from the metal target is collimated to travel in a direction perpendicular to the semiconductor structure [Liu: ¶¶ 36-37; Fig. 6B].
13. (Original) The method according to claim 9, wherein the metal is sputtered and deposited under a pressure that falls within a range of from 50mTorr to 400 mTorr.
14. (Original) The method according to claim 9, wherein the metal is sputtered and deposited at a temperature that falls within a range of from 18 °C to 450 °C [Liu: ¶¶ 7, 24, 33, claims 3 and 14; i.e. 50 mTorr to 500 mTorr].
15. (Previously Presented) The method according to claim 9, wherein the metal target includes at least one of Hf, Zr or W [Liu: ¶ 33].
16. (Currently Amended) The method according to claim 9, wherein the chemical reaction is performed at a temperature that falls within a range of from 18 °C to 300 °C [Liu: ¶ 40; i.e. 20 ℃ to 400 ℃].
Thus the claimed range falls within the range disclosed in Liu. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
This is all of the limitations of claims 9-16.
IV. Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21 reads,
21. (New) The method according to claim 1, further comprising: before depositing metal sputtered from a metal target on the semiconductor structure, depositing a dielectric layer on the semiconductor structure.
Chang does not teach some type of dielectric liner layer before depositing a dielectric fill to form the isolation. Nor does Liu teach depositing a dielectric liner layer in the semiconductor structure before sputter depositing the metal that is oxidized or nitridized to form the isolation structure. As such, the prior art does not reasonably teach or suggest—in the context of the claim—the limitation of claim 21.
V. Response to Arguments
Applicant’s arguments filed 06/17/2026 have been fully considered but are moot because the new grounds of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0115334 (“Liaw”) is cited for teaching a process similar to Chang as applicable to at least for claims 1 and 17. See Figs. 2A-2G and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
Prosecution Insights