DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1-2, 8-9, and 17 filed on 01/09/2026 have been fully considered for examination based on their merits. The original claims 3-7, 10-16, and 18-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-8, filed 01/09/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of YUN.
Applicant stated in the Remarks, page 7 that the claims 1-20 are rejected over ZHANG. The Examiner used ZHELUN to reject the aforementioned claims. This information is for clarification purpose only and no further action is needed.
Regarding Independent Claims 1, 9, and 17. Applicant argues that the amended features to claims 1, 9 and 17 are novel, distinct and patentable over the references of record. The Examiner considered the arguments and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned above. YUN teaches the amended limitations to claims 1, and 17, for instance, “an isolation cap…wherein the isolation cap…source and drain regions.” Similarly, YUN further teaches the amended limitations of claim 9 now recites, “wherein the second contact…first contact…opposite sides of the silicide layer…drain regions.”.
The claims 2-8, 9-16, and 18-20 depends on the independent claims 1, 9, and 17. Therefore, these depend claims follows similar arguments and are further rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang Zhelun et al, (hereinafter ZHELUN), CN 113224055 A, (reference used in previous Office action, OA), in view of Seungchan Yun et al, (hereinafter YUN), US 20210193834 A1, and further in view of Peter Baars et al, (hereinafter BAARS), US 20190148245 A1, (reference used in previous Office action, OA).
Regarding Claim 1, ZHELUN teaches in Figure 25, a semiconductor device (Fig. 25, 100, integrated circuit structure), comprising:
semiconductor channel sheets (124, channel layer), arranged in parallel and spaced apart from one another (annotated Figure 25);
source (190S, source epitaxial structure) and drain (190D, drain epitaxial structure) regions disposed beside the semiconductor channel sheets (124, channel layer);
a gate structure (220, metal gate structure) disposed around and surrounding the semiconductor channel sheets (124, channel layer);
a silicide layer (280, source silicide regions) disposed on the source region (190S, source epitaxial layer) or the drain region (190D, drain epitaxial structure); and
a contact structure (292, backside via) disposed on the silicide layer (280, source silicide regions) on the source region (190S, source epitaxial layer) or the drain region (190D, drain epitaxial structure),
wherein the contact structure (292, backside via) includes a metal contact (305, backside metal lines).
PNG
media_image1.png
1017
769
media_image1.png
Greyscale
ZHELUN does not explicitly disclose a semiconductor device, comprising: an isolation cap disposed on the gate structure, wherein the isolation cap is separate from the source and drain regions.
YUN teaches a semiconductor device (Fig. 2A, 100), comprising: an isolation cap (Fig. 2A, 125, element isolation layer) disposed on the gate structure (Fig. 2A, 160A, first gate structure), wherein the isolation cap (Fig. 2A, 125, element isolation layer) is separate from the source and drain regions (Fig. 2A, 150A, first source/drain regions).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHELUN to incorporate the teachings of YUN such that a semiconductor device, comprising: an isolation cap disposed on the gate structure, wherein the isolation cap is separate from the source and drain regions, so that the element isolation layer (125) may be a layer electrically and physically isolating the first transistor in a lower portion of the semiconductor device (100) from the second transistor in an upper portion of the semiconductor device (YUN, Figure 2A, [0043]).
ZHELUN as modified by YUN does not explicitly disclose a semiconductor device, wherein the contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.
BAARS teaches a semiconductor device (Fig. 1A, [0037]), wherein the contact structure includes a metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) and a liner (Fig. 11B, 254, thin oxide liner), and the silicide layer (Fig. 11B, 253, NiSi layer) is in contact with the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]), and the liner (Fig. 11B, 254, thin oxide liner) is
separate from the silicide layer (Fig. 11B, 253, NiSi layer) by the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHELUN as modified by YUN to incorporate the teachings of BAARS such that a semiconductor device, wherein the contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact so that the absence of thin oxide liner through the process of etching, the liner enables to expose the NiSi material covering the source and drain contact silicide layers, 253 (BAARS, Fig. 9B, [0052]).
Regarding Claim 2, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 1.
YUN further teaches the semiconductor device (Fig. 2A, 100), wherein the isolation cap (Fig. 2B, 125, element isolation layer) is separate from the metal contact (Fig. 2B, 180B, third contact plug) through the liner located there-between (Fig. 2B, 107, semiconductor layer).
Regarding Claim 3, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 2.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), wherein the isolation cap (Figs. 2/3, 910/912/914, mask or isolation region) includes a filling layer (Fig. 16, 226, first metal layer) and the liner (Fig. 16, 224, work function metal layer) is in contact with the filling layer (Fig. 16, 226, first metal layer) of the isolation cap (Figs. 2/3, 910/912/914, mask or isolation region).
Regarding Claim 4, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 1.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) includes an extended portion (annotated Figure 11B) disposed directly on the silicide layer (Fig. 11B, 253, NiSi layer).
Regarding Claim 5, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 4.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) is laterally surrounded (annotated Figure 11B) by the liner (Fig. 11B, 254, thin oxide liner) except for the extended portion (annotated Figure 11B).
PNG
media_image2.png
716
886
media_image2.png
Greyscale
Regarding Claim 6, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 4.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the extended portion (annotated Figure 11B) physically contacts the silicide layer (Fig. 11B, 253, NiSi layer) without the liner (Fig. 11B, 254, thin oxide liner) there-between.
PNG
media_image3.png
656
863
media_image3.png
Greyscale
Regarding Claim 7, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 1.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), wherein the source region (Fig. 11, 190S, source epitaxial layer) or the drain region (Fig. 11, 190D, drain epitaxial structure) includes an epitaxial layer (Fig. 1A, M1, S101/S111).
Regarding Claim 8, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 7.
YUN further teaches the semiconductor device (Fig. 2A, 100), further comprising an epitaxial material layer (Fig. 2A, 120, intermediate semiconductor layer, may be an epitaxial layer, [0042]) and an isolation layer (Fig. 2A, 125, element isolation layer) adjacent to the epitaxial layer (Fig. 2A, 150B, second source/drain region) of the source region or the drain region (Fig. 2A, 150B, second source/drain region), and the isolation layer (Fig. 2A, 125, element isolation layer) being sandwiched between the epitaxial layer (Fig. 2A, 120, intermediate semiconductor layer, may be an epitaxial layer, [0042]) and the epitaxial layer of the source region or the drain region (Fig. 2A, 150B, second source/drain region).
Regarding Claim 9, ZHELUN teaches in Figure 25, a semiconductor device (Fig. 25, 100, integrated circuit structure), comprising:
semiconductor channel sheets (124, channel layer), spaced apart from one another (annotated Figure 25);
source (190S, source epitaxial structure) and drain (190D, drain epitaxial structure) regions disposed beside the semiconductor channel sheets (124, channel layer);
a gate structure (220, metal gate structure) disposed around and surrounding the semiconductor channel sheets (124, channel layer);
first contact structures (292, backside via, annotated Figure 25) disposed on the source (280, source silicide regions) and drain regions (190D, drain epitaxial structure);
a silicide layer (280, source silicide regions) disposed on the source (190S, source epitaxial layer) region or the drain region (190D, drain epitaxial structure); and
a second contact structure (292, backside via, annotated Figure 25) disposed on the silicide layer (280, source silicide regions) on the source region (190S, source epitaxial layer) or the drain region (190D, drain epitaxial structure),
wherein the second contact structure (292, backside via, annotated Figure 25) includes a metal contact (305, backside metal lines).
PNG
media_image4.png
1013
787
media_image4.png
Greyscale
ZHELUN does not explicitly disclose a semiconductor device, comprising: wherein the second contact structure and one first contact structure are located at opposite sides of the silicide layer on the source region or the drain region.
YUN teaches a semiconductor device (Fig. 2A, 100), comprising: wherein the second contact structure (Fig. 1, 170B, first contact plugs) and one first contact structure (Fig. 1, 170A, first contact plugs) are located at opposite sides of the silicide layer (Fig. 1, 185, fourth contact plug, may include a barrier layer in an outermost region and/or a metal-semiconductor layer such as a silicide layer disposed on an end, [0052]) on the source region or the drain region (Fig. 1, 150A/150B, first source/drain regions).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHELUN to incorporate the teachings of YUN such that a semiconductor device, comprising: wherein the second contact structure and one first contact structure are located at opposite sides of the silicide layer on the source region or the drain region, so that a semiconductor device with high integration density of a semiconductor patterns have been achieved that have a high performance, high speed with increase multifunctionality (YUN, [0003], [0054]).
ZHELUN as modified by YUN does not explicitly disclose a semiconductor device, wherein the contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.
BAARS teaches a semiconductor device (Fig. 1A, [0037]), wherein the contact structure includes a metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) and a liner (Fig. 11B, 254, thin oxide liner), and the silicide layer (Fig. 11B, 253, NiSi layer) is in contact with the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]), and the liner (Fig. 11B, 254, thin oxide liner) is separate from the silicide layer (Fig. 11B, 253, NiSi layer) by the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHELUN as modified by YUN to incorporate the teachings of BAARS such that a semiconductor device, wherein the contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact so that the absence of thin oxide liner through the process of etching the liner enables to expose the NiSi material covering the source and drain contact silicide layers, 253 (BAARS, Fig. 9B, [0052]).
Regarding Claim 10, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), further comprising an isolation cap (Figs. 2/3, 910/912/914, mask or isolation region) disposed on the gate structure (Figs. 5A/11B, 150/220, dummy gate structure/metal gate structure), wherein the isolation cap (Figs. 2/3, 910/912/914, mask or isolation region) is separate from the metal contact (Fig. 16, 226, first metal layer) through the liner located (Fig. 16, 224, work function metal layer) there-between.
Regarding Claim 11, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), wherein the isolation cap (Figs. 2/3, 910/912/914, mask or isolation region) includes a filling layer (Fig. 16, 226, first metal layer) and the liner (Fig. 16, 224, work function metal layer) is in contact with the filling layer (Fig. 16, 226, first metal layer) of the isolation cap (Figs. 2/3, 910/912/914, mask or isolation region).
Regarding Claim 12, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) includes an extended portion (annotated Figure 11B) disposed directly on the silicide layer (Fig. 11B, 253, NiSi layer).
PNG
media_image5.png
656
863
media_image5.png
Greyscale
Regarding Claim 13, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the metal contact (Fig. 11B, 274, contact vias filled with conductive material, [0052]) laterally surrounded (annotated Figure 11B) by the liner (Fig. 11B, 254, thin oxide liner) except for the extended portion (annotated Figure 11B).
PNG
media_image2.png
716
886
media_image2.png
Greyscale
Regarding Claim 14, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the extended portion (annotated Figure 11B) physically contacts the silicide layer (Fig. 11B, 253, NiSi layer) without the liner there-between (Fig. 11B, 254, thin oxide liner).
PNG
media_image3.png
656
863
media_image3.png
Greyscale
Regarding Claim 15, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), wherein the source region (Fig. 11, 190S, source epitaxial layer) or the drain region (Fig. 11, 190D, drain epitaxial structure) includes an epitaxial layer (Fig. 11, 192/194, first/second epitaxial layer).
Regarding Claim 16, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 9.
ZHELUN further teaches the semiconductor device (100, integrated circuit structure), ZHELUN further teaches the semiconductor device (100, integrated circuit structure) an isolation layer (Fig. 8A, 140, STI) adjacent to the epitaxial layer (Fig. 11, 192/194, first/second epitaxial layer).
Regarding Claim 17, ZHELUN teaches, a method of forming (Figs. 1A-1C, M1) a semiconductor device (100, integrated circuit structure), comprising:
forming (Fig. 1B, S113) semiconductor channel sheets (124, channel layer) over a substrate (110);
forming (Fig. 1B, S111) source (Fig. 11, 190S, source epitaxial structure) and drain (Fig. 11, 190D, drain epitaxial structure) regions beside the semiconductor channel sheets (Fig. 11, 124, channel layer);
forming (Fig. 1B, S114) a gate structure (Fig. 14A, 220, metal gate structure) over and surrounding the semiconductor channel sheets (Fig. 14A, 124, channel layer);
thinning (Fig. 1B, S118) the substrate (110);
forming a hard mask layer (Figs. 2/3, 910, HM layer) on the isolation cap (Fig. 3, 912/914, mask or isolation region);
patterning (Fig. 9, P1) the hard mask layer (Figs. 2/3, 910, HM layer) and partially removing (Figs. 3/4, formation and removal of 910) a portion (Figs. 2/3, 910, HM layer) of the isolation cap (Figs. 2/3, 912/914, mask or isolation region) to form openings (Fig. 9, R1, recesses) exposing the source (Fig. 11, 190S, source epitaxial structure) and drain regions (Fig. 11, 190D, drain epitaxial structure);
forming (Fig. 1B, S115) a silicide layer (Fig. 23, 280, source silicide regions) respectively on the exposed (Fig. 23, 190S, source epitaxial structure) source and drain (Fig. 23, 190D, drain epitaxial structure) regions;
ZHELUN does not explicitly disclose a method of forming a semiconductor device, comprising: forming an isolation cap on the gate and separate from the source and drain regions;
YUN teaches a method of forming a semiconductor device (Fig. 2A, 100, [0021]), comprising: forming an isolation cap (Fig. 2A, 125, element isolation layer) on the gate structure (Fig. 2A, 160A, first gate structure), and separate from the source and drain regions (Fig. 2A, 150A, first source/drain regions).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZHELUN to incorporate the teachings of YUN such that a semiconductor device, comprising: an isolation cap disposed on the gate structure, wherein the isolation cap is separate from the source and drain regions, so that the element isolation layer (125) may be a layer electrically and physically isolating the first transistor in a lower portion of the semiconductor device (100) from the second transistor in an upper portion of the semiconductor device (YUN, Figure 2A, [0043]).
ZHELUN as modified by YUB does not explicitly disclose a semiconductor device, wherein a method of manufacturing of forming a semiconductor device comprising: forming a shielding layer on the silicide layer; forming a liner layer over the patterned hard mask layer and over the openings and on the isolation cap; removing the shielding layer; and forming metal contacts in the openings, wherein the metal contacts contact the silicide layers without the liner layer there-between.
BAARS teaches a semiconductor device, wherein the method of manufacturing of forming a semiconductor device (Fig. 1A, [0007], [0037]) comprising:
forming a shielding layer (Fig. 3B, 260, interlayer dielectric stack, [0008], [0041]) on the silicide layer (Fig. 3B, 253, NiSi layer);
forming a liner layer (Fig. 7B, 254, protective oxide liner) over the patterned hard mask layer (Fig. 6B, 368, spin-on hard mask (SOH)) and over the openings (Figs. 10A/10B, CA1/CA2/CB, vias for contacts) and on the isolation cap (Fig. 7B, 210, isolation region);
removing (Fig. 1C, S121, Fig. 5B, with no 260, interlayer dielectric layer) the shielding layer (Figs. 3B-5B, 260, interlayer dielectric stack, [0008], [0041], [0059]); and
forming metal contacts (Fig. 11B, 274, contact vias filled with conductive material, [0052]) in the openings (Figs. 10A/10B, CA1/CA2/CB, vias for contacts),
wherein the metal contacts (Fig. 11B, 274, contact vias filled with conductive material, [0052]) contact the silicide layers (Fig. 11B, 253, NiSi layer) without the liner layer (Fig. 7B, protective oxide liner) there-between.
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHELUN as modified by YUN to incorporate the teachings of BAARS such that a method of manufacturing of forming a semiconductor device comprising: forming a shielding layer on the silicide layer; forming a liner layer over the patterned hard mask layer and over the openings and on the isolation cap; removing the shielding layer; and forming metal contacts in the openings, wherein the metal contacts contact the silicide layers without the liner layer there-between, so that the absence of protective oxide liner through the process of etching the liner enables to expose the NiSi material covering the source and drain contact silicide layers, 253 (BAARS, Fig. 9B, [0052]).
Regarding Claim 18, ZHELUN as modified by YUN and BAARS teaches the semiconductor device (Fig. 1A, [0007], [0037]) of claim 17.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein forming metal contacts (Fig. 11B, 274, contact vias filled with conductive material, [0052]) in the openings (Figs. 10A/10B, CA1/CA2/CB, vias for contacts) includes forming a metal layer (tungsten, [0052]) on the liner layer (Ti/TiN barrier or liner, [0052]) and filling up the openings (Figs. 10A/10B, CA1/CA2/CB, vias for contacts), and remove the metal layer (tungsten, [0052]) and the liner layer (Ti/TiN barrier or liner, [0052]) above the patterned hard mask layer (Fig. 6B, 368, spin-on hard mask (SOH)).
Regarding Claim 19, ZHELUN as modified by YUN and BAARS teaches the semiconductor device (Fig. 1A, [0007], [0037]) of claim 17.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein the liner layer (Fig. 11B, 254, thin oxide liner) is formed over the openings (Figs. 10A/10B, CA1/CA2/CB, vias for contacts) covering the isolation cap (Figs. 2/3, 912/914, mask or isolation region) without covering the shielding layer (Fig. 11BB, 260, interlayer dielectric stack, [0008], [0041]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over ZHELUN, in view of YUN, further in view of BAARS, and further in view of Robert Clark, (hereinafter CLARK), US 20190295905 A1.
Regarding Claim 20, ZHELUN as modified by YUN and BAARS teaches the semiconductor device of claim 17.
BAARS further teaches the semiconductor device (Fig. 1A, [0007], [0037]), wherein forming the shielding layer (Fig. 11BB, 260, interlayer dielectric stack, [0008], [0041]).
ZHELUN as modified by YUN and BAARS does not explicitly disclose the semiconductor device wherein the shielding layer includes forming self- assembled monolayers of an organic material.
CLARK teaches in Figure 2D, the semiconductor device (11, the ASD workpiece) wherein the shielding layer (44, barrier layer/SAM/self-assembled monolayer) includes forming self- assembled monolayers ([0063]) of an organic material ([0054]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZHELUN as modified by YUN and BAARS to incorporate the teachings of BAARS such that the semiconductor device wherein the shielding layer includes forming self- assembled monolayers of an organic material so that the self-assembled monolayer (SAM) for an exemplified barrier layer and deposit selectively on any target surface (CLARK, [0063-0056]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20040150071 A1 – Figure 1
STATEMENT of RELEVANCE – Prospective view showing the structure of a fin-type transistor,
US 20200266271 A1 – Figures 1-2
STATEMENT of RELEVANCE – Flow chart representing a method for forming a multi-gate semiconductor structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights