Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to the office action dated 03/11/2026, the amendments made to independent claims 1 and 10 overcome the prior art rejection. Upon further search and consideration a new rejection with a new base reference is detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) in view of Ji et al (US 20200227429).
Sharma et al teaches
[claim 1] A transistor, comprising: a gate electrode; a ferroelectric layer disposed on the gate electrode (figure 1, paragraphs 0023-0024, where element 100 is a transistor [FET], element 12s0 is the ferroelectric layer disposed on the gate electrode [element 110]);
a source pattern and a drain pattern disposed over the ferroelectric layer (figure 1, paragraphs 0023-0024, where element 132 and 134 are the source and drain pattern disposed over the ferroelectric layer [element 120]);
and a channel layer having a base, wherein the base has a bottom surface and a top surface opposite to the bottom surface, the bottom surface of the base is in contact with the ferroelectric layer (figure 1, paragraphs 0023-0024, where element 136 is the channel layer and has a base [element 136] wherein the base has a bottom surface in contact with the ferroelectric layer [bottom surface of element 136 touches the ferroelectric layer [element 120], and a top surface which is the top surface of element 136).
However, Sharma et al does not specifically disclose
[claim 1] fins connected to the base, the fins protrude upward from the top surface of the base, and the fins are located between the source pattern and the drain pattern.
However, Ji et al does teach
[claim 1] fins protruding from connected to the base, the fins protrude upward from the top surface of the base, and the fins are located between the source pattern and the drain pattern (figure 1 below, figure 2 of Ji et al, paragraph 0052, where element 232 is the channel layer and replaces the channel layer of Sharma et al as well as the insulation layers, element 165 of Sharma et al, is replaced by the channel layer of Ji et al [element 232] with the base layer [as shown below] in place of element 136 of Sharma et al, and the fins [as shown below] are in place of the insulation layers of Sharma et al, and the channel layer of Ji et al is located between the source and drain patterns [elements 252 and 254]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al to incorporate the teachings of Ji et al to change the structure of the channel layer to have fins extending upward to force a higher breakdown voltage which allows for improved control over any connected circuit (paragraph 0024).
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Figure 1: Figure 2 of Ji et al.
Regarding claim 9, Sharma et al as modified does not specifically teach
[claim 9] wherein the fins extend from the base to beyond a top surface of the source pattern and a top surface of the drain pattern.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Sharma et al as modified to allow for the fins of the channel layer to extend above the source and drain layer as the only difference is a relative size of said channel layer, which even by error tolerances could be the case as two layers are not perfectly aligned in height if one measures with enough precision. Thus it would not be uncommon for the channel layer to extend above the source and drain layer in the disclosure of Sharma et al as modified.
Claim(s) 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) and Ji et al (US 20200227429) in view of Watakabe et al (US 20160149047 A1).
Sharma et al teaches all of the limitations of the parent claim, claim 1, however Sharma et al does not specifically disclose
[claim 2] further comprising a hydrogen blocking layer sandwiched between the source pattern and the ferroelectric layer and sandwiched between the drain pattern and the ferroelectric layer.
[claim 5] wherein a bottom surface of the base is coplanar with a bottom surface of the hydrogen blocking layer.
However, Watakabe et al does teach
[claim 2] further comprising a hydrogen blocking layer sandwiched between the source pattern and the ferroelectric layer and sandwiched between the drain pattern and the ferroelectric layer (paragraph 0016, figure 1, element 27 is the hydrogen blocking layer and is situated between the source [element 12s] and drain [element 12d]. When the transistor of Watakabe et al in figure 1 is supplanted with the same structure of Sharma et al, the hydrogen blocking layer would be on top of the ferroelectric layer and situated between the source and drain electrodes, thus being sandwiched between the ferroelectric layer and between the source and drain respectively).
[claim 5] wherein a bottom surface of the base is coplanar with a bottom surface of the hydrogen blocking layer (paragraph 0016, figure 1, element 27 is the hydrogen blocking layer and is situated between the source [element 12s] and drain [element 12d], thus is located on the bottom of the channel region and top portion of the ferroelectric layer of Watakabe, thus coplanar with bottom surface of the base of the channel layer according to figure 1 above).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Sharma et al as modified with the teachings of Watakabe et al in order to place a hydrogen barrier layer between the ferroelectric dielectric layer and the channel layer to improve efficiency of the channel layer by limiting hydrogen leakage into the channel.
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) and Ji et al (US 20200227429) in view of Cheng et al (US 20190181264 A1).
Sharma et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 6] further comprising a dielectric layer, wherein the dielectric layer is in contact with both sidewalls of each of the fins.
[claim 7] wherein the source pattern and the drain pattern are in contact with the fins.
[claim 8] wherein a bottom surface of the base is coplanar with a bottom surface of the source pattern and a bottom surface of the drain pattern.
However, Cheng et al does teach
[claim 6] further comprising a dielectric layer, wherein the dielectric layer is in contact with both sidewalls of each of the fins (figure 9, paragraphs 0044-0045, where the dielectric layer, element 104, due to its ferroelectric properties are in electrical contact with the sidewalls of the fins as the fins are part of the channel region and the dielectric layer enforces an effect onto the entire channel region, including the side walls).
[claim 7] wherein the source pattern and the drain pattern are in contact with the fins (figure 9, where elements 232 and 234 are the source and drain patterns respectively, and in contact with the fins as shown above in Figure 1).
[claim 8] wherein a bottom surface of the base is coplanar with a bottom surface of the source pattern and a bottom surface of the drain pattern (figure 9, where element 238 contains the base [as shown in figure 1 above] is coplanar with the bottoms of the source [element 232] and drain [element 234] patterns).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al as modified to incorporate the teachings of Cheng et al to incorporate a dielectric layer to allow for further electrical protection over the gate electrode to minimize any parasitic effects between the channel region and the gate electrode and/or the ferroelectric layer to improve efficiency of the device.
Claim(s) 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) and Ji et al (US 20200227429) and in further view of Or-Back et al (US 20210296155 A1).
Sharma et al teaches
[claim 10] A transistor, comprising: a gate electrode (figure 1, paragraphs 0023-0024, where element 100 is a transistor, and the gate electrode is element 110),
a ferroelectric layer disposed on the gate electrode (figure 1, paragraphs 0023-0024, where element 120 is the ferroelectric layer disposed on the gate electrode [element 110]),
a source pattern and a drain pattern disposed over the ferroelectric layer (figure 1, paragraphs 0023-0024, where elements 132 and 134 are the source and drain patterns disposed over the ferroelectric layer [element 120]);
and a channel layer disposed on the ferroelectric layer,
wherein the channel layer has a base, wherein the base has a bottom surface and a top surface opposite to the bottom surface, the bottom surface of the base is in contact with the ferroelectric layer (figure 1, paragraphs 0023-0024, where element 136 is the base channel layer where the bottom surface is the bottom surface of the base and is in contact of with the ferroelectric layer [element 120], and a top surface opposite the bottom surface).
However, Sharma et al does not specifically disclose
[claim 10] An integrated circuit, comprising: a substrate; a first transistor over the substrate; and an interconnect structure disposed on the substrate, comprising; dielectric layers; and a second transistor embedded in the dielectric layers, fins connected to the base, the fins protrude upward from the top surface of the base, and the fins are located between the source pattern and the drain pattern
However Ji et al does teach
[claim 10] fins connected to the base, the fins protrude upward from the top surface of the base, and the fins are located between the source pattern and the drain pattern figure 1 above, figure 2 of Ji et al, paragraph 0052, where element 232 is the channel layer and replaces the channel layer of Sharma et al as well as the insulation layers, element 165 of Sharma et al, is replaced by the channel layer of Ji et al [element 232] with the base layer [as shown below] in place of element 136 of Sharma et al, and the fins [as shown below] are in place of the insulation layers of Sharma et al, and the channel layer of Ji et al is located between the source and drain patterns [elements 252 and 254]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al to incorporate the teachings of Ji et al to change the structure of the channel layer to have fins extending upward to force a higher breakdown voltage which allows for improved control over any connected circuit (paragraph 0024).
However, Sharma et al as modified does not specifically disclose
[claim 10] An integrated circuit, comprising: a substrate; a first transistor over the substrate; and an interconnect structure disposed on the substrate, comprising; dielectric layers; and a second transistor embedded in the dielectric layers,
However, Or-Bach et al does teach
[claim 10] An integrated circuit, comprising: a substrate; a first transistor over the substrate (paragraph 0080, figure 10B, element 18310 is the substrate, with a first transistor, element 18312, over the substrate);
and an interconnect structure disposed on the substrate, comprising; dielectric layers; and a second transistor embedded in the dielectric layers (paragraph 0080, element 10B, element 18326 is the dielectric layer and situated in it is the interconnect layers [elements 18370, 18360, 18350] as well as the second transistor [element 18322], where the transistor of Sharma et al is in place of the second transistor).
It would be obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Sharma et al as modified to incorporate the teachings of Or-Bach et al in order to create a multi-transistor device and improve efficiency by putting the transistor with a ferroelectric dielectric layer in a device with another transistor to maximize spatial efficiency.
Regarding claim 15,
Sharma et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 15] wherein the source pattern and the drain pattern are in contact with the fins.
However, Ji et al further teaches
[claim 15] wherein the source pattern and the drain pattern are in contact with the fins (figure 2 and figure 1 above, where the channel layer is situated between the source and drain pattern [elements 252 and 254]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al as modified to incorporate the channel layer between the source and drain electrodes to allow adequate operation of the transistor device to have a source and drain on either side of the channel layer to allow current to flow from source and drain [basic function of a transistor]).
Claim(s) 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) and Ji et al (US 20200227429) and Or-Back et al (US 20210296155 A1) in further view of Watakabe et al (US 20160149047 A1).
Sharma et al as modified teaches all of the limitations of the parent claim, claim 10, however Sharma et al as modified does not specifically disclose
[claim 11] wherein the second transistor further comprises a hydrogen blocking layer sandwiched between the source pattern and the ferroelectric layer and sandwiched between the drain pattern and the ferroelectric layer.
However, Watakabe et al does teach
[claim 11] further comprising a hydrogen blocking layer sandwiched between the source pattern and the ferroelectric layer and sandwiched between the drain pattern and the ferroelectric layer (paragraph 0016, figure 1, element 27 is the hydrogen blocking layer and is situated between the source [element 12s] and drain [element 12d]. When the transistor of Watakabe et al in figure 1 is supplanted with the same structure of Sharma et al as modified, the hydrogen blocking layer would be on top of the ferroelectric layer and situated between the source and drain electrodes, thus being sandwiched between the ferroelectric layer and between the source and drain respectively).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Sharma et al as modified with the teachings of Watakabe et al in order to place a hydrogen barrier layer between the ferroelectric dielectric layer and the channel layer to improve efficiency of the channel layer by limiting hydrogen leakage into the channel.
Claim(s) 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457), Ji et al (US 20200227429),Or-Back et al (US 20210296155 A1), Watakabe et al (US 20160149047 A1) and in further view of Cheng et al (US 20190181264 A1).
Sharma et al as modified teaches all of the limitations of the parent claim, claim 11, but does not specifically disclose
[claim 13] The integrated circuit of claim 11, wherein a bottom surface of the channel layer is coplanar with a bottom surface of the hydrogen blocking layer.
However, Cheng et al does teach
[claim 13] wherein a bottom surface of the channel layer is coplanar with a bottom surface of the hydrogen blocking layer (figure 9, where element 238 of Cheng et al contains the base of the channel layer and is coplanar with the bottom of the source and drain which when read onto from Sharma et al as modified, since the hydrogen blocking layer is situated in such a position the channel layer is coplanar with the bottom surface fo the hydrogen blocking layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al as modified to incorporate the teachings of Cheng et al to make the channel layer and the hydrogen blocking layer coplanar to allow for greater protection of the channel layer and thus greater efficiency of the device.
Claim(s) 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al (US 20200176457) and Ji et al (US 20200227429) and Or-Back et al (US 20210296155 A1) and in further view of Cheng et al (US 20190181264 A1).
Sharma et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 14] further comprising a dielectric layer, wherein the dielectric layer is in contact with both sidewalls of each of the fins.
[claim 16] wherein a bottom surface of the base is coplanar with a bottom surface of the source pattern and a bottom surface of the drain pattern.
However, Cheng et al teaches
[claim 14] further comprising a dielectric layer, wherein the dielectric layer is in contact with both sidewalls of each of the fins (figure 9, paragraphs 0044-0045, where the dielectric layer, element 104, due to its ferroelectric properties are in electrical contact with the sidewalls of the fins as the fins are part of the channel region and the dielectric layer enforces an effect onto the entire channel region, including the side walls).
[claim 16] wherein a bottom surface of the base is coplanar with a bottom surface of the source pattern and a bottom surface of the drain pattern (figure 9, where element 238 contains the base [as shown in figure 1 above] is coplanar with the bottoms of the source [element 232] and drain [element 234] patterns).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Sharma et al as modified to incorporate the teachings of Cheng et al to allow for the dielectric layer and coplanar source and drain electrode with the channel layer to allow for greater resistance against parasitic effects and thus greater device efficiency.
Allowable Subject Matter
Claims 3-4, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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