Prosecution Insights
Last updated: August 18, 2026
Application No. 17/887,530

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §103
Filed
Aug 15, 2022
Priority
Jul 13, 2022 — TW 111126286
Examiner
CULLEN, PATRICK LAWRENCE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
6 (Final)
82%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+14.4% vs TC avg
Strong +30% interview lift
Without
With
+30.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
33 currently pending
Career history
73
Total Applications
across all art units

Statute-Specific Performance

§103
73.5%
+33.5% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 Claims 1 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yui (PGPub No. 20210351342) in further view of Braganca (PGPub No. 20170117323), Lin (PGPub No. 20230354719), Wang (PGPub No. 20210343786), Tsubata (US Patent No. 10388855), and Liu (PGPub No. 20220013715). Regarding claim 1, Yui teaches a method for fabricating semiconductor device, comprising: forming a spin orbit torque (SOT) layer on a substrate (Fig. 5B, [0042], and [0044] point to a SOT-MRAM device comprising a SOT layer 504 formed on a base such as a substrate (not shown).); and forming a magnetic tunneling junction (MTJ) stack on the SOT layer, wherein forming the MTJ stack comprises: forming a free layer on the SOT layer; forming a barrier layer on the free layer (Fig. 5B and [0044] point to an MTJ stack 506 formed on the SOT layer 504, said stack 506 comprising a free layer 508 formed on the SOT layer 504 and a tunnel barrier layer 510 formed on the free layer 508.). Yui fails to teach wherein the SOT layer comprises nitrogen atoms or oxygen atoms; forming a reference layer on the barrier layer; forming a spacer on the reference layer; forming a pinned layer on the spacer; performing a first etching process to remove part of the pinned layer until exposing a top surface of the spacer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process that stops by detecting the nitrogen atoms or oxygen atoms of the SOT layer as an end point; performing a trimming process to remove the first residue and the second residue and trim a sidewall of the pinned layer, a sidewall of the spacer and a sidewall of the reference layer to form a continuous convex curve, and trim a sidewall of the free layer and the top surface of the SOT layer to form a continuous concave curve, and a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer. Braganca teaches wherein the SOT layer comprises nitrogen atoms or oxygen atoms (Figs. 5A, 442). Specifically, Braganca teaches a MRAM device, comprising a SOT layer 442 with portions doped with a dopant, such as nitrogen, to decrease electrical resistivity ([0034]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Braganca, such that the SOT layer comprises nitrogen in order to decrease electrical resistivity and ensure that more current flows through the MTJ. Yui et al. still fails to teach forming a reference layer on the barrier layer; forming a spacer on the reference layer; forming a pinned layer on the spacer; performing a first etching process to remove part of the pinned layer until exposing a top surface of the spacer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process that stops by detecting the nitrogen atoms or oxygen atoms of the SOT layer as an end point; performing a trimming process to remove the first residue and the second residue and trim a sidewall of the pinned layer, a sidewall of the spacer and a sidewall of the reference layer to form a continuous convex curve, and trim a sidewall of the free layer and the top surface of the SOT layer to form a continuous concave curve, and a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer. Lin teaches forming a reference layer on the barrier layer; forming a spacer on the reference layer; and forming a pinned layer on the spacer (Fig. 2 points to a MTJ structure 130A comprising a reference layer 136a, a spacer 136c, and a magnetic pinned layer 136b.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Lin, such that a reference layer, spacer, and pinned layer are formed respectively in order to create a ferromagnetic layer with a locked magnetic field orientation which controls the amount of current flowing through the overall MTJ structure based on its alignment with the magnetic field orientation of the underlying layer(s). Yui et al. still fails to teach performing a first etching process to remove part of the pinned layer until exposing a top surface of the spacer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process that stops by detecting the nitrogen atoms or oxygen atoms of the SOT layer as an end point; performing a trimming process to remove the first residue and the second residue and trim a sidewall of the pinned layer, a sidewall of the spacer and a sidewall of the reference layer to form a continuous convex curve, and trim a sidewall of the free layer and the top surface of the SOT layer to form a continuous concave curve, and a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer. Wang teaches performing a first etching process to remove part of the pinned layer until exposing a top surface of the spacer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process that stops by detecting the nitrogen atoms or oxygen atoms of the SOT layer as an end point (Figs. 3-4 point to conducting one or more etching processes to remove parts of a MTJ stack 48 (barrier layer) and expose a channel layer 42 (SOT layer) to form a MTJ 58. [0029] further points to an alternative method of forming a MTJ comprising the use of a reactive ion etching (RIE) process (second etching process) and/or an ion beam etching (IBE) process (first etching process) in order to remove part of a MTJ stack 120 and form/pattern a MTJ 120. It is considered obvious that both a first residue and a second residue would also be formed as a natural byproduct of the IBE and RIE processes, respectively, and that said first residue would obviously act as a protective mask by preventing any subsequent etching(s) from directly contacting and interacting with the area. Furthermore, it is also considered obvious that one of ordinary skill in the art would configure a RIE process to stop upon detecting nitrogen or oxygen atoms since it is well known in the art that any interaction with nitrogen or oxygen atoms during the process would result in a detectable change in emission line intensity.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Wang, such that a portion of the top/pinned layer of the MTJ stack is first etched via an IBE process in order to take advantage of its low selectivity and precision, and then the underlying barrier layer and free layer of said stack are subsequently etched via a RIE process, which is known for being fast and ideal for multilayer processing. Yui et al. still fails to teach performing a trimming process to remove the first residue and the second residue and trim a sidewall of the pinned layer, a sidewall of the spacer and a sidewall of the reference layer to form a continuous convex curve, and trim a sidewall of the free layer and the top surface of the SOT layer to form a continuous concave curve, and a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer. Tsubata teaches performing a trimming process to remove the first residue and the second residue and trim a sidewall of the pinned layer, a sidewall of the spacer and a sidewall of the reference layer to form a continuous convex curve, and trim a sidewall of the free layer and the top surface of the SOT layer to form a continuous concave curve (Figs. 1 and 5 point to performing an IBE process (trimming process) on a stacked structure 20 (MTJ) to form an underlying region with a forward tapered shape (concave curve) and an upper region with a reverse tapered shape (convex curve) which meet at a tunnel barrier layer 23.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Wang, such that a continuous convex curve and a continuous concave curve are formed respectively in order to reduce the influence of the stray magnetic field applied from the vicinity of the edge of the upper reference layer to the region near the edge of the underlying storage/free layer. Yui et al. still fails to teach performing a trimming process on a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer. Liu teaches performing a trimming process on a sidewall of the barrier layer to form a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer (Fig. 6 points to MTJs 52 and 54, each comprising a pinned layer 40, a free layer 44, and a barrier layer 42 with a concave rough surface 58 (recess).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Liu, such that the sidewall of the barrier layer further comprises a concave recess in order to prevent metallic redeposition during patterning that could damage the barrier layer. Regarding claim 4, Yui teaches wherein the trimming process comprises: performing a first trimming process to remove the first residue and the second residue at a first angle within a first duration ([0053]); and performing a second trimming process to remove the first residue and the second residue at a second angle within a second duration (Id.). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls (first and second trimming processes) with desired slopes (first and second angles) as needed (Id.). The terms “first duration” and “second duration” are interpreted as inherent characteristics of the first and second trimming processes respectively. Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that trimming is performed on the MTJ stack in order to remove residue left behind from etching, with said trimming performed in two stages in order to minimize damage to the MTJ stack. Regarding claim 5, Yui teaches wherein the first angle is less than the second angle ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls with desired slopes as needed (the first angle is less than the second angle) (Id.). Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that the first angle created is less than the second angle created in order to reduce re-deposition and better control the electric field of the now trimmed MTJ. Regarding claim 6, Yui teaches wherein the first duration is less than the second duration ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls with desired slopes as needed (the first duration is less than the second duration) (Id.). Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that the trimming processes performed on the MTJ stack only last long enough to reduce re-deposition from specific areas of the MTJ without damaging the stack in order to allow for better control of the electric field. Regarding claim 7, Wang teaches wherein the trimming process comprises an ion beam etching (IBE) process. Specifically, Wang teaches a method for fabricating a semiconductor device comprising one or more etching processes (trimming process) to remove parts of the MTJ stack to form a MTJ, where an ion beam etching (IBE) process could be conducted to pattern the MTJ stack (Id.). Thus, it would have been obvious to combine the teachings of Yui with those of Wang, such that an additional IBE process is performed on the MTJ stack in order to effectively remove the residue(s) left behind by the first and second etching processes and further adjust the sidewall profile to improve structural integrity. Claim(s) 12, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yui et al. in further view of Hashemi (PGPub No. 20220199898). Regarding claim 12, Yui teaches a semiconductor device, comprising: a spin orbit torque (SOT) layer on a substrate (Fig. 5B, [0042], and [0044] point to a SOT-MRAM device comprising a SOT layer 504 formed on a base such as a substrate (not shown).); and a magnetic tunneling junction (MTJ) on the SOT layer, wherein the MTJ comprises: a free layer on the SOT layer; a barrier layer on the free layer (Fig. 5B and [0044] point to a MTJ stack 506 formed on the SOT layer 504, said stack 506 comprising a free layer 508 formed on the SOT layer 504, a tunnel barrier layer 510 formed on the free layer 508.); wherein a sidewall of the free layer comprises a first slope and a sidewall of the pinned layer comprises a second slope, the first slope is less than the second slope ([0053] points to the MTJ stack 506 (free layer; pinned layer) having tapered sidewalls or any suitable sidewall profiles with desired slopes (a first slope and a second slope) as needed. It is considered obvious that the formation of multiple slopes would require multiple etching processes to occur, with each process likely to exhibit the common phenomenon of undercut etching, or undercutting, which would result in differing slopes based on the specific etch process used and the specific material said process is performed on.). Yui fails to teach a reference layer on the barrier layer; a spacer on the reference layer; a pinned layer on the spacer, a top surface of the SOT layer adjacent to two sides of the MTJ is lower than a top surface of the SOT layer directly under the MTJ, and a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer, wherein the sidewall of the free layer and the top surface of the SOT layer form a continuous concave curve, wherein a sidewall of the reference layer, a sidewall of the spacer, and the sidewall of the pinner layer form a continuous convex curve. Lin teaches a reference layer on the barrier layer; a spacer on the reference layer; and a pinned layer on the spacer (Fig. 2 points to a MTJ structure 130A comprising a reference layer 136a, a spacer 136c, and a magnetic pinned layer 136b.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Lin, such that a reference layer, spacer, and pinned layer are formed respectively in order to create a ferromagnetic layer with a locked magnetic field orientation which controls the amount of current flowing through the overall MTJ structure based on its alignment with the magnetic field orientation of the underlying layer(s). Yui fails to teach a top surface of the SOT layer adjacent to two sides of the MTJ is lower than a top surface of the SOT layer directly under the MTJ, and a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer, wherein the sidewall of the free layer and the top surface of the SOT layer form a continuous concave curve, wherein a sidewall of the reference layer, a sidewall of the spacer, and the sidewall of the pinner layer form a continuous convex curve. Hashemi teaches a top surface of the SOT layer adjacent to two sides of the MTJ is lower than a top surface of the SOT layer directly under the MTJ (Fig. 3 points to a spin conducting layer 208 (SOT layer) underneath a second MTJ stack 210, where the top surface of said layer 208 underneath the MTJ stack 210 is higher than the top surface(s) adjacent to said stack 210.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui and Hashemi, such that the portion(s) of the SOT layer adjacent to the MTJ are positioned lower than the portion(s) directly underneath the MTJ in order to focus the switching current and reduce parasitic conduction paths. Yui et al. still fails to teach a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer, wherein the sidewall of the free layer and the top surface of the SOT layer form a continuous concave curve, wherein a sidewall of the reference layer, a sidewall of the spacer, and the sidewall of the pinner layer form a continuous convex curve. Liu teaches a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer (Fig. 6 points to MTJs 52 and 54, each comprising a pinned layer 40, a free layer 44, and a barrier layer 42 with a concave rough surface 58 (recess).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Liu, such that the sidewall of the barrier layer further comprises a concave recess in order to prevent metallic redeposition during patterning that could damage the barrier layer. Yui et al. still fails to teach wherein the sidewall of the free layer and the top surface of the SOT layer form a continuous concave curve, wherein a sidewall of the reference layer, a sidewall of the spacer, and the sidewall of the pinner layer form a continuous convex curve. Tsubata teaches wherein the sidewall of the free layer and the top surface of the SOT layer form a continuous concave curve, wherein a sidewall of the reference layer, a sidewall of the spacer, and the sidewall of the pinner layer form a continuous convex curve (Figs. 1 and 5 point to a stacked structure 20 (MTJ) comprising an underlying region with a forward tapered shape (concave curve) and an upper region with a reverse tapered shape (convex curve) which meet at a tunnel barrier layer 23.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Wang, such that a continuous convex curve and a continuous concave curve are formed respectively in order to reduce the influence of the stray magnetic field applied from the vicinity of the edge of the upper reference layer to the region near the edge of the underlying storage/free layer. Regarding claim 17, Yui teaches wherein a top surface of the SOT layer adjacent to the MTJ is lower than a top surface of the SOT layer under the MTJ ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 and SOT layer 504, which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have any suitable sidewall profiles with desired slopes (a top surface of the SOT layer adjacent to the MTJ is lower than a top surface of the SOT layer under the MTJ) as needed (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further follow the indirect teachings of Yui, such that the SOT layer comprises slopes which elevate the area of the layer under the MTJ higher than the adjacent area(s) in order to localize spin-orbit torque and minimize current leakage into surrounding regions. Regarding claim 18, Braganca teaches wherein the SOT layer comprises nitrogen (Figs. 5A, 442). Specifically, Braganca teaches a MRAM device, comprising a SOT layer 442 with portions doped with a dopant, such as nitrogen, to decrease electrical resistivity ([0034]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Braganca, such that the SOT layer comprises nitrogen in order to decrease electrical resistivity and ensure that more current flows through the MTJ. Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yui et al. in further view of Kim (PGPub No. 20210143323). Regarding claim 19, Kim teaches wherein the SOT layer comprises oxygen (Fig. 7, 606). Specifically, Kim teaches a method for forming a MTJ device structure, comprising a SOT layer comprising MgO ([0076]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Kim, such that the SOT layer comprises oxygen in order to enhance spin-orbit coupling and improve thermal stability. Response to Arguments Applicant’s arguments, see Remarks, filed 06/15/2026, with respect to the rejection of claim 16 under 35 U.S.C. §112(d) have been fully considered and are persuasive. The rejection of said claim is now considered moot and has been withdrawn. Applicant’s arguments, see Remarks, filed 06/15/2026, with respect to the rejection(s) of claim(s) 1 and 12 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yui et al. in further view of Lin (PGPub No. 20230354719) and Tsubata (US Patent No. 10388855). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Show 6 earlier events
Aug 14, 2025
Non-Final Rejection mailed — §103
Oct 30, 2025
Response Filed
Dec 16, 2025
Final Rejection mailed — §103
Jan 29, 2026
Request for Continued Examination
Feb 05, 2026
Response after Non-Final Action
Mar 20, 2026
Non-Final Rejection mailed — §103
Jun 15, 2026
Response Filed
Aug 06, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

7-8
Expected OA Rounds
82%
Grant Probability
99%
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