Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 16 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Specifically, claim 16 merely recites “a sidewall of the barrier layer comprises a recess”, while claim 12 (upon which claim 16 depends) discloses “a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer” (emphasis added). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
Claims 1 and 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yui (PGPub No. 20210351342) in further view of Wang (PGPub No. 20210343786).
Regarding claim 1, Yui teaches a method for fabricating semiconductor device, comprising: forming a spin orbit torque (SOT) layer on a substrate (Fig. 5B, [0042], and [0044] point to a SOT-MRAM device comprising a SOT layer 504 formed on a base such as a substrate (not shown).); and forming a magnetic tunneling junction (MTJ) stack on the SOT layer, wherein forming the MTJ stack comprises: forming a free layer on the SOT layer; forming a barrier layer on the free layer; forming a pinned layer on the barrier layer (Fig. 5B and [0044] point to an MTJ stack 506 formed on the SOT layer 504, said stack 506 comprising a free layer 508 formed on the SOT layer 504, a tunnel barrier layer 510 formed on the free layer 508, and a reference layer 512 (pinned layer) having a fixed or pinned magnetic moment formed on the tunnel barrier layer 510.).
Yui fails to teach performing a first etching process to remove part of the pinned layer until exposing a top surface of the barrier layer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process.
Wang teaches performing a first etching process to remove part of the pinned layer until exposing a top surface of the barrier layer and forming a first residue on a sidewall of the pinned layer, wherein the first etching process comprises an ion beam etching (IBE) process; and using the first residue as a mask to protect the sidewall of the pinned layer to perform a second etching process to remove part of the barrier layer and part of the free layer until exposing a surface of the SOT layer to form a MTJ and a second residue on the first residue and a sidewall of the MTJ, wherein the second etching process comprises a reactive ion etching (RIE) process (Figs. 3-4 point to conducting one or more etching processes to remove parts of a MTJ stack 48 (barrier layer) and expose a channel layer 42 (SOT layer) to form a MTJ 58. [0029] further points to an alternative method of forming a MTJ comprising the use of a reactive ion etching (RIE) process (second etching process) and/or an ion beam etching (IBE) process (first etching process) in order to remove part of a MTJ stack 120 and form/pattern a MTJ 120. It is considered obvious that both a first residue and a second residue would also be formed as a natural byproduct of the IBE and RIE processes, respectively. Furthermore, the residue created as a result of the first etching process would obviously act as a protective mask by preventing any subsequent etching(s) from directly contacting and interacting with the area.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yui and Wang, such that a portion of the top/pinned layer of the MTJ stack is first etched via an IBE process in order to take advantage of its low selectivity and precision, and then the underlying barrier layer and free layer of said stack are subsequently etched via a RIE process, which is known for being fast and ideal for multilayer processing.
Regarding claim 3, Yui teaches performing a trimming process to remove the first residue and the second residue ([0053] points to the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls (a trimming processes) with desired slopes as needed.).
Regarding claim 4, Yui teaches wherein the trimming process comprises: performing a first trimming process to remove the first residue and the second residue at a first angle within a first duration ([0053]); and performing a second trimming process to remove the first residue and the second residue at a second angle within a second duration (Id.). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls (first and second trimming processes) with desired slopes (first and second angles) as needed (Id.). The terms “first duration” and “second duration” are interpreted as inherent characteristics of the first and second trimming processes respectively. Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that trimming is performed on the MTJ stack in order to remove residue left behind from etching, with said trimming performed in two stages in order to minimize damage to the MTJ stack.
Regarding claim 5, Yui teaches wherein the first angle is less than the second angle ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls with desired slopes as needed (the first angle is less than the second angle) (Id.). Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that the first angle created is less than the second angle created in order to reduce re-deposition and better control the electric field of the now trimmed MTJ.
Regarding claim 6, Yui teaches wherein the first duration is less than the second duration ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have tapered sidewalls with desired slopes as needed (the first duration is less than the second duration) (Id.). Thus, it would have been obvious to a POSITA prior to the filling date to further follow the indirect teachings of Yui, such that the trimming processes performed on the MTJ stack only last long enough to reduce re-deposition from specific areas of the MTJ without damaging the stack in order to allow for better control of the electric field.
Regarding claim 7, Wang teaches wherein the trimming process comprises an ion beam etching (IBE) process. Specifically, Wang teaches a method for fabricating a semiconductor device comprising one or more etching processes (trimming process) to remove parts of the MTJ stack to form a MTJ, where an ion beam etching (IBE) process could be conducted to pattern the MTJ stack (Id.). Thus, it would have been obvious to combine the teachings of Yui with those of Wang, such that an additional IBE process is performed on the MTJ stack in order to effectively remove the residue(s) left behind by the first and second etching processes and further adjust the sidewall profile to improve structural integrity.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yui et al. in further view of Braganca (PGPub No. 20170117323).
Regarding claim 10, Braganca teaches wherein the SOT layer comprises nitrogen (Figs. 5A, 442). Specifically, Braganca teaches a MRAM device, comprising a SOT layer 442 with portions doped with a dopant, such as nitrogen, to decrease electrical resistivity ([0034]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Braganca, such that the SOT layer comprises nitrogen in order to decrease electrical resistivity and ensure that more current flows through the MTJ.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yui et al. in further view of Kim (PGPub No. 20210143323).
Regarding claim 11, Kim teaches wherein the SOT layer comprises oxygen (Fig. 7, 606). Specifically, Kim teaches a method for forming a MTJ device structure, comprising a SOT layer comprising MgO ([0076]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Kim, such that the SOT layer comprises oxygen in order to enhance spin-orbit coupling and improve thermal stability.
Claim(s) 12 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yui et al. in further view of Hashemi (PGPub No. 20220199898) and Liu (PGPub No. 20220013715).
Regarding claim 12, Yui teaches a semiconductor device, comprising: a spin orbit torque (SOT) layer on a substrate (Fig. 5B, [0042], and [0044] point to a SOT-MRAM device comprising a SOT layer 504 formed on a base such as a substrate (not shown).); and a magnetic tunneling junction (MTJ) on the SOT layer, wherein the MTJ comprises: a free layer on the SOT layer; a barrier layer on the free layer; and a pinned layer on the barrier layer (Fig. 5B and [0044] point to a MTJ stack 506 formed on the SOT layer 504, said stack 506 comprising a free layer 508 formed on the SOT layer 504, a tunnel barrier layer 510 formed on the free layer 508, and a reference layer 512 (pinned layer) having a fixed or pinned magnetic moment formed on the tunnel barrier layer 510.), wherein a sidewall of the free layer comprises a first slope and a sidewall of the pinned layer comprises a second slope, the first slope is less than the second slope ([0053] points to the MTJ stack 506 (free layer; pinned layer) having tapered sidewalls or any suitable sidewall profiles with desired slopes (a first slope and a second slope) as needed. It is considered obvious that the formation of multiple slopes would require multiple etching processes to occur, with each process likely to exhibit the common phenomenon of undercut etching, or undercutting, which would result in differing slopes based on the specific etch process used and the specific material said process is performed on.).
Yui fails to teach a top surface of the SOT layer adjacent to two sides of the MTJ is lower than a top surface of the SOT layer directly under the MTJ, and a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer.
Hashemi teaches a top surface of the SOT layer adjacent to two sides of the MTJ is lower than a top surface of the SOT layer directly under the MTJ (Fig. 3 points to a spin conducting layer 208 (SOT layer) underneath a second MTJ stack 210, where the top surface of said layer 208 underneath the MTJ stack 210 is higher than the top surface(s) adjacent to said stack 210.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui and Hashemi, such that the portion(s) of the SOT layer adjacent to the MTJ are positioned lower than the portion(s) directly underneath the MTJ in order to focus the switching current and reduce parasitic conduction paths.
Yui et al. still fails to teach a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer.
Liu teaches a sidewall of the barrier layer comprises a recess that is concave inward from the sidewall of the free layer and the sidewall of the pinned layer (Fig. 6 points to MTJs 52 and 54, each comprising a pinned layer 40, a free layer 44, and a barrier layer 42 with a concave rough surface 58 (recess).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Liu, such that the sidewall of the barrier layer further comprises a concave recess in order to prevent metallic redeposition during patterning that could damage the barrier layer.
Regarding claim 16, Yui teaches wherein a sidewall of barrier layer comprises a recess ([0053]). Specifically, Yui teaches a MTJ stack 506, a tunnel barrier layer 510 included within the stack, and the patterning of MTJ stack 506, which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have any suitable sidewall profiles (a recess) with desired slopes as needed (Fig. 5B; [0053]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further follow the indirect teachings of Yui, such that the barrier layer of the MTJ stack is recessed in order to lower the current density and improve energy efficiency.
Regarding claim 17, Yui teaches wherein a top surface of the SOT layer adjacent to the MTJ is lower than a top surface of the SOT layer under the MTJ ([0053]). Specifically, Yui teaches the patterning of MTJ stack 506 and SOT layer 504, which, although described and depicted as having a substantially vertical sidewall profile after patterning, may have any suitable sidewall profiles with desired slopes (a top surface of the SOT layer adjacent to the MTJ is lower than a top surface of the SOT layer under the MTJ) as needed (Id.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further follow the indirect teachings of Yui, such that the SOT layer comprises slopes which elevate the area of the layer under the MTJ higher than the adjacent area(s) in order to localize spin-orbit torque and minimize current leakage into surrounding regions.
Regarding claim 18, Braganca teaches wherein the SOT layer comprises nitrogen (Figs. 5A, 442). Specifically, Braganca teaches a MRAM device, comprising a SOT layer 442 with portions doped with a dopant, such as nitrogen, to decrease electrical resistivity ([0034]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Braganca, such that the SOT layer comprises nitrogen in order to decrease electrical resistivity and ensure that more current flows through the MTJ.
Regarding claim 19, Kim teaches wherein the SOT layer comprises oxygen (Fig. 7, 606). Specifically, Kim teaches a method for forming a MTJ device structure, comprising a SOT layer comprising MgO ([0076]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yui et al. and Kim, such that the SOT layer comprises oxygen in order to enhance spin-orbit coupling and improve thermal stability.
Response to Arguments
Applicant's arguments filed 01/29/2026 with regards to the rejection of claim 1 have been fully considered but they are not persuasive. Specifically, Applicant argues that the prior arts cited by Examiner fail to teach or suggest 1) the strategic control over the sequence and etching layers of IBE and RIE process, and 2) the intentional formation and utilization of the residue as a sidewall protection layer as recited in the amended claim 1.
In response to applicant's first argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the strategic control over the sequence and etching layers of IBE and RIE process) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Despite Applicant’s argument, the amended claim 1 of the present application only states the use of a first etching process (IBE) and a second etching process (RIE); nowhere does it state details that would indicate a “strategic control”, such as a specific recipe or parameters that are used during each process. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the rejection of claim 1.
In response to applicant's second argument that the first residue is intentionally formed and utilized as a sidewall protection layer, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. As discussed in the prior rejection and reiterated above, the IBE process comprising the first etching process is commonly known to leave behind residue(s) as a natural byproduct and by extension form an additional layer that covers the processed area (i.e., the barrier layer); it is considered obvious that the residue would provide some level of protection in the event of a second etching process, acting at the very least as a physical buffer layer that would prevent/mitigate etching of the underlying barrier layer. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the rejection of claim 1.
Applicant’s arguments, see Remarks, filed 01/29/2026, with respect to the rejection(s) of claim(s) 12 and 16-19 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yui et al. in further view of Liu (PGPub No. 20220013715).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899