DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant argues the pending claims are amended to clarify that the passivation liner in the pending claims comprises aluminum oxide or hafnium oxide, which is not taught by the references. However, this argument is moot as a new ground of rejection is presented herein.
Applicant further argues For the reasons to combine Kim to Hsu, the Examiner has cited paragraph [0019] of Hsu for teaching the BDTI structure 138 is arranged laterally between the photodetectors 120 according to a grid pattern to advantageously provide optical isolation between the photodetectors 120. However, the transparent characteristics of indium tin oxide (ITO) taught Kim would have frustrated the purpose of optical isolation provided by the Examiner. Therefore, the combining the TEL material taught by Kim to Hsu is a merely a hindsight of claimed subject matter.
However, BDTI 138 in Hsu is a trench isolation structure. Hsu further discloses a third conductive layer 1702 is formed filling the plug opening 1502 (see, e.g., FIG. 15) and, in some embodiments, the BDTI opening 1602 (see, e.g., FIG. 16), [0092] and the third conductive layer 1702 comprises a BDTI structure 138, [0092].
Kim teaches an isolation pattern 101 lining trenches filled by a transparent conductive material which improves a dark current property of the device while still providing isolation. As modified by Lee as discussed below, cross-talk phenomenon between photodetectors 120 would be suppressed. Accordingly, the combination of Hsu Kim, and Lee is motivated.
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 includes “wherein the isolation gride structure” which is considered to be a typographical error of “wherein the isolation grid structure.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20170229494A1 to Hsu et al. (hereinafter “Hsu”), in view of US20200077055A1 to Kim et al. (hereinafter “Kim”), further in view of US 20180061873 A1 to Lee et al. (hereinafter “Lee”).
RE: Claim 16, Hsu discloses A method of manufacturing an image sensor device (method for manufacturing a BSI image sensor in FIGs. 6-22, [0071]), comprising:
receiving a device substrate (108, [0090], FIG. 22), the device substrate having a frontside and a backside (top of 108) opposite the frontside, and a plurality of image-sensing elements (120, [0090], FIG. 22) arranged within the device substrate;
forming an isolation grid structure (138, [0011], [0092], FIGs. 16-17) extending into the device substrate from the backside and made up of a plurality of isolation grid segments that surround outer perimeters of the plurality of image-sensing elements (FIG. 17 shows segments of 138 surrounding outer perimeters of 120), wherein forming the isolation grid structure comprises:
forming a trench (1602 in FIG. 16, [0090]) in the device substrate;
forming a conductive layer (130 in FIG. 20, [0096]) over the backside of the device substrate; and
patterning the conductive layer (134, 130 in FIG. 21, [0099]) to form a light blocking grid (134) over the isolation grid structure (138) and a bias pad layer (130), wherein the bias pad layer extends from a conductive bonding pad (132, plug structure 132 extends from the conductive layer 130, [0030], [0092]; so 130 also extends from 132) formed in the device substrate to the isolation grid structure, the bias pad layer electrically couples the conductive bonding pad with the isolation grid structure (ground structure 136 and/or a BDTI structure 138 are arranged under and electrically coupled to the conductive layer 130, [0019]; conductive layer 130 is arranged over the pad structure 124, in the dielectric region 126, and is electrically coupled to the pad structure 124 by a plug structure 132, [0018]), and the light blocking grid is made up of a plurality of metal grid segments that surround outer perimeters of the plurality of image-sensing elements (134 is a backside shield structure made of metal segments, [0018]; backside shield structure laterally surrounds photodetector, [0013]; The conductive layer 130 and the plug structure 132 are metal, [0030]; etch is performed through the fifth dielectric layer 240, the fourth conductive layer 130, and the second dielectric layer 226. The ninth etch is performed to form grid segment openings 2102 exposing the first dielectric layer 222, and to further form a backside shield structure 134 arranged laterally between the grid segment openings 2102 according to a grid pattern, [0099]; accordingly, since 130 is etched to form 134, 134 is metal also), wherein the plurality of metal grid segments overlie the plurality of image-sensing elements (FIG. 22 shows 134 lying over 120).
Hsu does not explicitly disclose that forming the isolation grid structure 138 comprises: depositing a passivation liner along surfaces of the trench; and depositing an indium-tin-oxide (ITO) fill material on the passivation liner.
However, Hsu identifies BDTI is backside deep trench isolation (BDTI), [0003] and discloses The BDTI structure 138 is further arranged laterally between the photodetectors 120 according to a grid pattern to advantageously provide optical isolation between the photodetectors 120, [0019].
Hsu further discloses a third conductive layer 1702 is formed filling the plug opening 1502 (see, e.g., FIG. 15) and, in some embodiments, the BDTI opening 1602 (see, e.g., FIG. 16), [0092] and the third conductive layer 1702 comprises a BDTI structure 138, [0092].
In a similar field of endeavor, Kim discloses The first device isolation pattern 101 may be provided to conformally and partially fill the trench TR. The conductive pattern 105 may fill the entire portion of the trench TR, except the first device isolation pattern 101. A top surface of the conductive pattern 105 and a top surface of the first device isolation pattern 101 may be coplanar with the second surface 100 b of the semiconductor substrate 100. A bottom surface of the conductive pattern 105 and a bottom surface of the first device isolation pattern 101 may be coplanar with the first surface 100 a of the semiconductor substrate 100, [0080]. For example, the first device isolation pattern 101 may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, [0042], see FIG. 4A.
Kim further discloses The transparent conductive layer TEL may be provided on the first device isolation pattern 101, [0055]. The transparent conductive layer TEL may include a horizontal portion HP and a vertical portion VP, [0060]. The vertical portion VP may be vertically extended from the second surface 100 b of the semiconductor substrate 100 toward the first surface 100 a, [0061]. As an example, the transparent conductive layer TEL may be formed of or include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or organic transparent conductive materials, [0055]. The conductive pattern 105 may include the same material as the transparent conductive layer TEL, [0094].
Kim further discloses The light-blocking layer GR and the transparent conductive layer TEL may be in direct contact with each other and may be electrically connected to each other. The negative voltage may be applied to the transparent conductive layer TEL through the pad PAD and the light-blocking layer GR. Positive charges, which are produced in the unit pixels PX, may be discharged through the transparent conductive layer TEL surrounding the unit pixels PX. Thus, it may be possible to improve a dark current property of an image sensor, [0062].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to partially fill the trench 1602 in Hsu with the isolation pattern 101 deposited along surfaces thereof as taught by Kim to provide better isolation between photodetectors 120.As a result, the isolation pattern would correspond to the claimed passivation liner of the isolation grid structure.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the trench 1602 with transparent conductive indium tin oxide on the isolation pattern as further taught by Kim to improve a dark current property of the device while still providing trench isolation between photodetectors 120 in Hsu.
Modified Hsu does not explicitly disclose that the isolation pattern 101 comprises aluminum oxide or hafnium oxide.
However, Kim discloses The first device isolation pattern 101 may include an insulating material whose refractive index is lower than that of the semiconductor substrate 100 (e.g., made of silicon), [0042].
In the same field of endeavor, Lee discloses The device isolation pattern 200 may include an insulating pattern 210 and a conductive pattern 220. The insulating pattern 210 may be provided along a side surface of the trench 201. The insulating pattern 210 may be formed of or include, for example, at least one of silicon-containing materials (e.g., silicon nitride, silicon oxide, and/or silicon oxynitride) and/or high-k dielectric materials (e.g., hafnium oxide and/or aluminum oxide). The insulating pattern 210 may have a refractive index lower than that of the substrate 100 or a doping layer 150. This may make it possible to prevent or suppress a cross-talk phenomenon from occurring between the pixels Px, [0034], see FIG. 2B.
Lee further discloses The substrate 100 may be, for example, a semiconductor substrate (e.g., a silicon wafer, [0029].
Hsu discloses The first and second semiconductor substrates 220, 108 may be, for example, bulk substrates of silicon, [0024].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use hafnium oxide and/or aluminum oxide for the material in the isolation pattern 101 as taught by Lee which would have a refractive index lower than that of the silicon substrate 108 in order to prevent or suppress a cross-talk phenomenon between photodetectors 120 as further taught by Lee.
RE: Claim 17, modified Hsu discloses The method of claim 16, further comprising:
filling a plurality of first openings (128, [0017], FIG. 22 of Hsu) with an oxide material (242; 242 is silicon dioxide, [0100]);
forming a plurality of color filters over the oxide material, wherein each color filter is formed over a corresponding image-sensing element (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22).
Hsu does not explicitly disclose forming an array of micro-lenses over the plurality of color filters with each micro- lens of the array of micro-lenses aligned with a color filter.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063], see FIG. 4A.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters with each micro lens aligned with a color filter as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
RE: Claim 18, modified Hsu discloses The method of claim 16, further comprising:
forming color filters in a plurality of first openings (128, FIG. 22 of Hsu, [0100]), wherein each color filter is formed over a corresponding image-sensing element (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22).
Hsu does not explicitly disclose forming a plurality of micro-lenses over the color filters with each micro-lens is aligned with a color filter.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
RE: Claim 19, modified Hsu discloses The method of claim 16, wherein a bottom surface of the light blocking grid contacts a top surface of the isolation grid structure (In FIGs. 20-22 of Hsu, bottom surface of 134 contacts top surface of 138).
RE: Claim 20, modified Hsu discloses The method of claim 16, further comprising exposing the backside of the device substrate to an etching process to form a plurality of topographical features in the backside of the device substrate prior to forming the isolation grid structure (a seventh etch is performed through the first and second dielectric layers 222, 226, into the second semiconductor substrate 108, to form a BDTI opening 1602 and a ground opening 1604, [0090]; BDTI opening 1602 is shown before 138 is formed in FIG. 17 of Hsu; here unetched portions of 108 are considered to correspond to topographical features).
Claim(s) 21-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, in view of US20190165026A1 to Kuo et al. (hereinafter “Kuo”), further in view of Kim, further in view of Lee.
RE: Claim 21, Hsu discloses A method (method for manufacturing a BSI image sensor in FIGs. 6-22, [0071]), comprising:
forming a plurality of image-sensing elements (120, [0090], FIGs. 6-22) within a device substrate (108, [0090], FIG. 22);
forming an isolation grid structure (138, [0011], [0092], FIGs. 16-17) extending into the device substrate ( FIG. 17 shows 138 extending into 108), wherein the isolation gride structure comprises a plurality of isolation grid segments that surround outer perimeters of the plurality of image-sensing elements (FIG. 17 shows segments of 138 surrounding outer perimeters of 120), and
forming a light blocking grid (134, [0099]) overlying the device substrate, wherein the light blocking grid comprises a plurality of metal grid segments that surround the outer perimeters of the plurality of image-sensing elements (134 is a backside shield structure made of metal segments, [0018]; backside shield structure laterally surrounds photodetector, [0013]; The conductive layer 130 and the plug structure 132 are metal, [0030]; a ninth etch is performed through the fifth dielectric layer 240, the fourth conductive layer 130, and the second dielectric layer 226. The ninth etch is performed to form grid segment openings 2102 exposing the first dielectric layer 222, and to further form a backside shield structure 134 arranged laterally between the grid segment openings 2102 according to a grid pattern, [0099]; Accordingly, since 130 is etched to form 134, 134 is metal also, see FIGs. 20-21), wherein the plurality of metal grid segments overlie the plurality of image-sensing elements (FIG. 22 shows 134 lying over 120).
Hsu does not explicitly disclose depositing a light transmission layer over the plurality of image-sensing elements, wherein the light transmission layer comprises a backside, a frontside opposite the backside, the frontside of the light transmission layer adjacent to the backside of the device substrate;
forming the isolation grid structure extending into the light transmission layer.
However, in the same field of endeavor, Kuo discloses that one or more etchants remove parts of the substrate 102 to define a plurality of recesses 124 arranged between a plurality of protrusions 118 extending outward from the substrate 102, [0055], FIG. 9.
Kuo further discloses that The angled sidewalls of the protrusions 118 may further act to reduce an angle of incidence α2 for incident radiation 138 b having a steep angle with respect to a top surface of the one or more absorption enhancement layers 304-306, thereby preventing the incident radiation 138 b from reflecting away from the substrate 102, [0035].
Kuo further discloses that One or more absorption enhancement layers 304-306 are arranged along the back-side 102 b of the substrate 102 within the plurality of recesses 124 and within the DTI structures 130. The plurality of protrusions 118 and the one or more absorption enhancement layers 304-306 are configured to increase absorption of radiation by the image sensing element 106 by providing for a low reflection of radiation from the substrate 102, [0035].
Kuo further discloses that One of the one or more absorption enhancement layers 126 contacts the substrate 102 along the non-planar surface to define an absorption enhancement structure with a topography that increases absorption of radiation by the substrate 102 (e.g., by reducing a reflection of radiation from the non-planar surface). Increasing absorption of radiation by the substrate 102 increases a quantum efficiency (QE) of the image sensing element 106, and thereby improves performance of the image sensor integrated chip 100, [0022].
Kuo further discloses that An anti-reflective layer 304 and a layer of dielectric material 306 are arranged along the back-side 102 b of the substrate 102 and may be arranged lining the trenches within the plurality of DTI structures 130, [0044].
Kuo further discloses a third etching process is performed to remove the layer of dielectric material 306 from within the trenches 1008, [0061], FIGs. 12-13.
FIG. 4 in Kuo shows 136 extending through absorption enhancement layers 304, 306. Kuo further discloses the DTI structures 130 may also comprise a reflective element 136, [0026]. Accordingly, 136 is a DTI structure extending through absorption enhancement layers 304, 306.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form angled sidewalls by forming recesses as taught by Kuo in the substrate 108 of Hsu to reduce an angle of incidence and prevent incident radiation from reflecting away from the substrate as taught by Kuo.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form absorption enhancement layers 304, 306 as taught by Kuo within the recesses of the substrate 108 and the isolation structure / trench 1602 in FIG. 16 of Hsu, [0090] and to remove 306 from the trench 1602 as taught by Kuo to increase absorption of radiation by the photodetectors 120 in Hsu. In Kuo, as the absorption enhancement layers 304, 306 reduce reflection from the substrate, they are considered to be light transmission layers since in order for light to be reflected from the substrate at a reduced amount, light would have to at least partially pass through layers 304, 306 and reach the substrate. As modified, the modified DTI structure including the conductive indium tin oxide of Kim and the isolation pattern of Lee extends through absorption enhancement layers 304, 306.
Hsu does not explicitly disclose wherein the backside deep trench isolation structure 138 comprises: a passivation liner; and a conductive layer in contact with the passivation liner.
However, Hsu identifies BDTI is backside deep trench isolation (BDTI), [0003] and discloses The BDTI structure 138 is further arranged laterally between the photodetectors 120 according to a grid pattern to advantageously provide optical isolation between the photodetectors 120, [0019].
Hsu further discloses a third conductive layer 1702 is formed filling the plug opening 1502 (see, e.g., FIG. 15) and, in some embodiments, the BDTI opening 1602 (see, e.g., FIG. 16), [0092] and the third conductive layer 1702 comprises a BDTI structure 138, [0092].
In a similar field of endeavor, Kim discloses The first device isolation pattern 101 may be provided to conformally and partially fill the trench TR. The conductive pattern 105 may fill the entire portion of the trench TR, except the first device isolation pattern 101. A top surface of the conductive pattern 105 and a top surface of the first device isolation pattern 101 may be coplanar with the second surface 100 b of the semiconductor substrate 100. A bottom surface of the conductive pattern 105 and a bottom surface of the first device isolation pattern 101 may be coplanar with the first surface 100 a of the semiconductor substrate 100, [0080]. For example, the first device isolation pattern 101 may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, [0042] see FIG. 4A.
Kim further discloses The transparent conductive layer TEL may be provided on the first device isolation pattern 101, [0055]. The transparent conductive layer TEL may include a horizontal portion HP and a vertical portion VP, [0060]. The vertical portion VP may be vertically extended from the second surface 100 b of the semiconductor substrate 100 toward the first surface 100 a, [0061]. As an example, the transparent conductive layer TEL may be formed of or include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or organic transparent conductive materials, [0055]. The conductive pattern 105 may include the same material as the transparent conductive layer TEL, [0094]. FIG. 4A shows TEL in contact with 101.
Kim further discloses The light-blocking layer GR and the transparent conductive layer TEL may be in direct contact with each other and may be electrically connected to each other. The negative voltage may be applied to the transparent conductive layer TEL through the pad PAD and the light-blocking layer GR. Positive charges, which are produced in the unit pixels PX, may be discharged through the transparent conductive layer TEL surrounding the unit pixels PX. Thus, it may be possible to improve a dark current property of an image sensor, [0062].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to partially fill the trench 1602 in Hsu with the isolation pattern 101 deposited along surfaces thereof as taught by Kim to provide better isolation between photodetectors 120.As a result, the isolation pattern would correspond to the claimed passivation liner of the isolation grid structure.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the trench 1602 with transparent conductive indium tin oxide in contact with the isolation pattern as further taught by Kim to improve a dark current property of the device while still providing trench isolation between photodetectors 120 in Hsu.
Modified Hsu does not explicitly disclose that the isolation pattern 101 comprises aluminum oxide or hafnium oxide.
However, Kim discloses The first device isolation pattern 101 may include an insulating material whose refractive index is lower than that of the semiconductor substrate 100 (e.g., made of silicon), [0042].
In the same field of endeavor, Lee discloses The device isolation pattern 200 may include an insulating pattern 210 and a conductive pattern 220. The insulating pattern 210 may be provided along a side surface of the trench 201. The insulating pattern 210 may be formed of or include, for example, at least one of silicon-containing materials (e.g., silicon nitride, silicon oxide, and/or silicon oxynitride) and/or high-k dielectric materials (e.g., hafnium oxide and/or aluminum oxide). The insulating pattern 210 may have a refractive index lower than that of the substrate 100 or a doping layer 150. This may make it possible to prevent or suppress a cross-talk phenomenon from occurring between the pixels Px, [0034], see FIG. 2B.
Lee further discloses The substrate 100 may be, for example, a semiconductor substrate (e.g., a silicon wafer, [0029].
Hsu discloses The first and second semiconductor substrates 220, 108 may be, for example, bulk substrates of silicon, [0024].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use hafnium oxide and/or aluminum oxide for the material in the isolation pattern 101 as taught by Lee which would have a refractive index lower than that of the silicon substrate 108 in order to prevent or suppress a cross-talk phenomenon between photodetectors 120 as further taught by Lee.
RE: Claim 22, modified Hsu discloses The method of claim 21, wherein the conductive layer comprises an ITO (indium tin oxide) material (as modified above, the conductive layer in the trenches 1602 is transparent conductive indium tin oxide).
RE: Claim 23, modified Hsu discloses The method of claim 22, wherein a top surface of the ITO material, a top surface of the passivation liner, and the backside of the light transmission layer are substantially co-planar (Kim discloses the top surface of the conductive pattern 105 and a top surface of the first device isolation pattern 101 may be coplanar, [0080]; Kuo shows in FIG. 4 the top surface of BDTI 136 is coplanar with the top surface of 306; Accordingly, the top surface of the isolation pattern / hafnium oxide and/or aluminum oxide from Lee, the top surface of the conductive indium tin oxide from Kim, and the top surface of 306 from Kuo be coplanar).
RE: Claim 24, modified Hsu discloses The method of claim 22, wherein the ITO material and the passivation liner extend above the backside of the device substrate (As modified, the substrate would be etched to form recesses, the ITO material and isolation 101 would extend above the substrate 108 in Hsu as 138 extends above the substrate 108).
RE: Claim 25, modified Hsu discloses The method of claim 21, further comprising:
forming a plurality of topographical features in the backside of the device substrate, wherein the topographical features comprise a plurality of recesses arranged between a plurality of protrusions the plurality of recesses and the plurality of protrusions separated by interior surfaces of the device substrate (As modified for claim 21, recesses are formed in the substrate with protrusions separated by interior surfaces of the substrate); and
forming a passivation layer over the backside of the device substrate in between the plurality of topographical features and the light transmission layer (As modified for claim 21, layer 304 from Kuo would be formed over the recesses, and 306 would be formed over 304). Layer 304 would correspond to the claimed passivation layer.
RE: Claim 26, modified Hsu discloses The method of claim 25, wherein the light transmission layer fills the plurality of recesses defined by interior surfaces of the device substrate and the light transmission layer extends above the backside of the device substrate (As modified, 306 from Kuo would fill the recesses of the substrate and 306 would extend above the substrate).
RE: Claim 27, modified Hsu discloses The method of claim 21, further comprising:
filling a plurality of first openings (128, [0031], FIG. 22 in Hsu) defined by the light blocking grid with an oxide material (242 is silicon oxide, [0031]);
forming a plurality of color filters over the oxide material, wherein each color filter is formed over a corresponding image-sensing element (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22),
wherein a bottom surface of the light blocking grid contacts a top surface of the isolation grid structure (in FIGs. 20-22, bottom surface of 134 contacts top surface of 138).
Modified Hsu does not explicitly disclose forming an array of micro-lenses over the plurality of color filters with each micro- lens of the array of micro-lenses aligned with a color filter.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
RE: Claim 28, modified Hsu discloses The method of claim 21, further comprising: forming a color filter layer in a plurality of first openings (128 in FIG. 22 in Hsu, [0100]) defined by the light blocking grid (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22),
wherein a bottom surface of the light blocking grid contacts a top surface of the isolation grid structure (in FIGs. 20-22, bottom surface of 134 contacts top surface of 138).
Modified Hsu does not explicitly disclose forming an array of micro-lenses over the color filter layer.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
Claim(s) 29-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Kim and further in view of Lee.
RE: Claim 29, Hsu discloses A method (method for manufacturing a BSI image sensor in FIGs. 6-22, [0071]), comprising:
forming an image sensor device (image sensor in FIG. 22, [0071]) comprising:
a pixel array region (backside deep trench isolation (BDTI) structure and/or a backside shield structure are arranged on the upper side of the semiconductor structure, and are arranged laterally between the pixel sensors, [0011]; 120 are considered pixel sensors, [0017]]; the left region of FIG. 22 that includes 120 is therefore considered a pixel array region), comprising:
a device substrate (108, [0090], FIG. 22) having a frontside and a backside opposite the frontside;
a plurality of image-sensing elements (120, [0017]) arranged within the device substrate; and
an isolation grid structure (138, [0011], [0092], FIGs. 16-17) extending into the device substrate and made up of a plurality of isolation grid segments that surround the outer perimeters of the plurality of image-sensing elements (FIG. 17 shows segments of 138 surrounding outer perimeters of 120);
a black level correction (BLC) region (middle region of FIG. 22 including middle portion of 130, [0018]; the conductive layer 130 comprises a backside shield structure 134 arranged over the photodetectors 120 and laterally between the photodetectors 120 and/or the color filter openings 128 according to a grid pattern. The grid pattern advantageously provides optical isolation, [0018]; accordingly, conductive layer 130 would also provide optical isolation to regions underneath 130; the middle region of FIG. 22 that includes 130 is therefore considered to be a black level region for blocking or correcting the intensity of incoming light) adjacent to the pixel array region;
a bonding pad region (right side region of FIG. 22 that includes 124, [0017]) adjacent to the BLC region, comprising:
a conductive bonding pad (1702, [0092]) arranged within the device substrate; and a bias pad layer (130, [0096]) extending from the conductive bonding pad, through the BLC region, and contacting the isolation grid structure,
wherein the bias pad layer electrically couples the conductive bonding pad with the isolation grid structure (FIG. 22 shows 130 electrically couples 1702 with 138 as 130 extends from 1702 to 138 and 130 is conductive).
Hsu does not explicitly disclose that 138 includes a passivation liner disposed on a surface of trenches formed in the device substrate; and an-indium-tin-oxide (ITO) material disposed on the passivation liner.
However, Hsu identifies BDTI is backside deep trench isolation (BDTI), [0003] and discloses The BDTI structure 138 is further arranged laterally between the photodetectors 120 according to a grid pattern to advantageously provide optical isolation between the photodetectors 120, [0019].
Hsu further discloses a third conductive layer 1702 is formed filling the plug opening 1502 (see, e.g., FIG. 15) and, in some embodiments, the BDTI opening 1602 (see, e.g., FIG. 16), [0092] and the third conductive layer 1702 comprises a BDTI structure 138, [0092].
In a similar field of endeavor, Kim discloses The first device isolation pattern 101 may be provided to conformally and partially fill the trench TR. The conductive pattern 105 may fill the entire portion of the trench TR, except the first device isolation pattern 101. A top surface of the conductive pattern 105 and a top surface of the first device isolation pattern 101 may be coplanar with the second surface 100 b of the semiconductor substrate 100. A bottom surface of the conductive pattern 105 and a bottom surface of the first device isolation pattern 101 may be coplanar with the first surface 100 a of the semiconductor substrate 100, [0080]. For example, the first device isolation pattern 101 may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, [0042], see FIG. 4A.
Kim further discloses The transparent conductive layer TEL may be provided on the first device isolation pattern 101, [0055]. The transparent conductive layer TEL may include a horizontal portion HP and a vertical portion VP, [0060]. The vertical portion VP may be vertically extended from the second surface 100 b of the semiconductor substrate 100 toward the first surface 100 a, [0061]. As an example, the transparent conductive layer TEL may be formed of or include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or organic transparent conductive materials, [0055]. The conductive pattern 105 may include the same material as the transparent conductive layer TEL, [0094].
Kim further discloses The light-blocking layer GR and the transparent conductive layer TEL may be in direct contact with each other and may be electrically connected to each other. The negative voltage may be applied to the transparent conductive layer TEL through the pad PAD and the light-blocking layer GR. Positive charges, which are produced in the unit pixels PX, may be discharged through the transparent conductive layer TEL surrounding the unit pixels PX. Thus, it may be possible to improve a dark current property of an image sensor, [0062].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to partially fill the trench 1602 in Hsu with the isolation pattern 101 deposited along surfaces thereof as taught by Kim to provide better isolation between photodetectors 120.As a result, the isolation pattern would correspond to the claimed passivation liner of the isolation grid structure.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the trench 1602 with transparent conductive indium tin oxide on the isolation pattern as further taught by Kim to improve a dark current property of the device while still providing trench isolation between photodetectors 120 in Hsu.
Modified Hsu does not explicitly disclose that the isolation pattern 101 comprises aluminum oxide or hafnium oxide.
However, Kim discloses The first device isolation pattern 101 may include an insulating material whose refractive index is lower than that of the semiconductor substrate 100 (e.g., made of silicon), [0042].
In the same field of endeavor, Lee discloses The device isolation pattern 200 may include an insulating pattern 210 and a conductive pattern 220. The insulating pattern 210 may be provided along a side surface of the trench 201. The insulating pattern 210 may be formed of or include, for example, at least one of silicon-containing materials (e.g., silicon nitride, silicon oxide, and/or silicon oxynitride) and/or high-k dielectric materials (e.g., hafnium oxide and/or aluminum oxide). The insulating pattern 210 may have a refractive index lower than that of the substrate 100 or a doping layer 150. This may make it possible to prevent or suppress a cross-talk phenomenon from occurring between the pixels Px, [0034], see FIG. 2B.
Lee further discloses The substrate 100 may be, for example, a semiconductor substrate (e.g., a silicon wafer, [0029].
Hsu discloses The first and second semiconductor substrates 220, 108 may be, for example, bulk substrates of silicon, [0024].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use hafnium oxide and/or aluminum oxide for the material in the isolation pattern 101 as taught by Lee which would have a refractive index lower than that of the silicon substrate 108 in order to prevent or suppress a cross-talk phenomenon between photodetectors 120 as further taught by Lee.
RE: Claim 30, modified Hsu discloses The method of claim 29, wherein the image sensor device further comprises:
a light blocking grid (134, [0099]) overlying the device substrate and surrounding outer perimeters of the plurality of image-sensing elements (134 is a backside shield structure made of metal segments, [0018]; backside shield structure laterally surrounds photodetector, [0013]), such that a plurality of first openings defined by the plurality of metal grid segments overlie the plurality of image- sensing elements (In FIG. 22, openings between 138 overlie 120), wherein the bias pad layer and the light blocking grid comprise the same metal material (a ninth etch is performed through the fifth dielectric layer 240, the fourth conductive layer 130, and the second dielectric layer 226. The ninth etch is performed to form grid segment openings 2102 exposing the first dielectric layer 222, and to further form a backside shield structure 134 arranged laterally between the grid segment openings 2102 according to a grid pattern, [0099], FIGs. 20-21; 134 is an unetched portion of 130, and so 130 and 134 are made of the same material).
RE: Claim 31, modified Hsu discloses The method of claim 29, wherein the bias pad layer contacts a buffer oxide layer (228, FIG. 20; 228 is formed of silicon dioxide, [0083]) and a dielectric fill material (238, FIG. 20, [0088]) in the bonding pad region.
RE: Claim 32, modified Hsu discloses The method of claim 29, wherein a top surface of the ITO material and a top surface of the passivation liner are substantially co-planar (Kim discloses the top surface of the conductive pattern 105 and a top surface of the first device isolation pattern 101 may be coplanar, [0080]; Kuo shows in FIG. 4 the top surface of BDTI 136 is coplanar with the top surface of 306; Accordingly, the top surface of the hafnium oxide and/or aluminum oxide from Lee, the top surface of the conductive indium tin oxide from Kim, and the top surface of 306 from Kuo be coplanar).
RE: Claim 33, modified Hsu discloses The method of claim 29, wherein the ITO material is in contact with the passivation liner (As modified, the ITO material from Kim would contact the isolation pattern 101 as it would be formed directly over 101 as shown in FIG. 4A in Kim).
RE: Claim 34, modified Hsu discloses The method of claim 30, wherein the image sensor device further comprises:
an oxide material (242 is silicon oxide, [0031]) filling the plurality of first openings (128, [0031], FIG. 22 in Hsu) defined by the light blocking grid;
a plurality of color filters formed over the oxide material, wherein each color filter is formed over a corresponding image-sensing element (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22),
wherein a bottom surface of the light blocking grid contacts a top surface of the isolation grid structure (in FIGs. 20-22, bottom surface of 134 contacts top surface of 138).
Modified Hsu does not explicitly disclose an array of micro-lenses formed over the plurality of color filters with each micro-lens of the array of micro-lenses aligned with a color filter.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
RE: Claim 35, modified Hsu discloses The method of claim 30, wherein the image sensor device further comprises:
a color filter layer formed in the plurality of first openings defined by the light blocking grid (an array of color filter openings 128 are arranged over respective ones of the photodetectors 120 and configured to accommodate respective color filters (not shown), [0017]; accordingly, color filters would be in the color filter openings 128, over 242, and over respective photodetectors 120 in FIG. 22); and
wherein a bottom surface of the light blocking grid contacts a top surface of the isolation grid structure (in FIGs. 20-22, bottom surface of 134 contacts top surface of 138).
Hsu does not explicitly disclose an array of micro-lenses formed over the color filter layer.
However, Kim discloses The micro lenses 307 may be provided on the first to third color filters 303 a, 303 b, and 303 c, respectively, [0063].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form micro lenses over respective color filters as taught by Kim to focus incoming light. See attached Merriam-Webster’s dictionary definition for “lens” accessed at <https://www.merriam-webster.com/dictionary/lens> on April 2, 2025, definition 1 on pg. 1 which states that lenses can be combined with an optical instrument for forming an image by focusing rays of light. Here, the micro-lenses are considered to be lenses.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899