DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/11/2025 has been entered.
Response to Arguments
Applicant's arguments filed 11/11/2025 have been fully considered but they are not persuasive. Applicant argues that the combination of Lin with Shimote cannot properly be combined to teach the amendment limitation because of Lin’s grinding process, which would be needed before the grinding. However, Lin alone teaches this limitation: after mounting the wiring substrate (170) over the first surface of the redistribution circuit structure (124), forming an insulating encapsulation (346) between the redistribution circuit structure (124) and the wiring substrate (170) to laterally encapsulate the conductive pillar (424) (Figure 21), as set forth in the rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Publication No. 2016/0118333) in view of Shimote et al. (US Publication No. 2016/0233189).
Regarding claim 14, Lin discloses a method for fabricating a package structure, comprising:
providing a redistribution circuit structure (124) having a first surface (facing down) and a second surface (facing up) opposite to the first surface, wherein the redistribution circuit structure (124) comprises a first contact pad (116 contacting solder ball 432) at the first surface
forming a conductive pillar (424) over the first contact pad (116), wherein the conductive pillar (424) is electrically connected to the first contact pad (116)
mounting a wiring substrate (170) over the first surface of the redistribution circuit structure (124)
after mounting the wiring substrate (170) over the first surface of the redistribution circuit structure (124), forming an insulating encapsulation (346) between the redistribution circuit structure (124) and the wiring substrate (170) to laterally encapsulate the conductive pillar (424) (Figure 21)
Lin does not disclose disposing a solder material on the second contact pad of the wiring substrate, placing the wiring substrate onto the first surface of the redistribution circuit structure such that the conductive pillar protrudes into the solder material, and performing a reflow process. However, Shimote discloses disposing a solder material (SD1) on the second contact pad (2BF) of the wiring substrate, placing the wiring substrate (3) onto the first surface of the redistribution circuit structure (2BF) such that the conductive pillar (3BP) protrudes into the solder material (SD1), and performing a reflow process (paragraph 88). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Line to include the steps as taught by Shimote, since can provide a strong bond at the connection terminals (paragraph 88).
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Regarding claim 15, Shimote discloses the wiring substrate is provided having an insulating layer (GC) formed thereon, the insulating layer comprising an opening (Sk1) revealing a portion of the second contact pad (2BF), and the solder material (SD1) is disposed in the opening (Sk1) and on a portion of the second contact pad (2BF) (Figure 31). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Lin in view of Shimote.
Regarding claim 16, Lin discloses the conductive pillar (424) is formed over the first contact pad by stencil printing (paragraph 145 shows a screen printing process for conductive material that can be formed into pillars 424).
Regarding claim 17, Lin/Shimote discloses the limitations as discussed in the rejection of claim 14 above. Lin does not disclose disposing a solder cap over the first contact pad before forming the conductive pillar over the first contact pad. However, an embodiment of Lin (Figure 16A) includes forming solder (166) over a contact pad (162) before placing the pillar (120). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date to form solder on the first contact pad to improve alignment for testing the redistribution circuit, thereby avoiding defective interconnect structures (paragraphs 117 and 82; Figure 4D).
Regarding claim 18, Lin discloses the solder cap (166) is disposed over the first contact pad by stencil printing (paragraph 66 describes solder bump processing can be formed by a screen printing process, which is a more refined method of stencil printing).
Regarding claim 19, Lin discloses mounting a semiconductor device (84) over the first surface of the redistribution circuit structure (124) before mounting the wiring substrate (170) (Figure 16A).
Regarding claim 20, Lin discloses the redistribution circuit structure (124) is provided over a carrier (134), and the second surface is in contact with the carrier (134) (Figure 5C).
Regarding claim 21, Lin discloses de-bonding the redistribution circuit structure (124) from the carrier (134) to reveal the second surface of the redistribution circuit structure (124).
Regarding claim 22, Lin discloses forming a first conductive terminal (334) over a third contact pad (336) at the second surface of the redistribution circuit structure (124) after de-bonding the redistribution structure (124) from the carrier (134).
Regarding claim 23, Lin discloses forming a second conductive terminal (306) electrically connected to the second contact pad of the wiring substrate (170) (Figure 21B).
Regarding claim 24, Lin discloses a method, comprising:
forming a redistribution circuit structure (124) comprising first contact pads (116 contacting solder ball 432)
forming conductive pillars (424) over the first contact pads (116) of the redistribution circuit structure (124)
filling the space between the redistribution circuit structure (124) and the wiring substrate (170) with an insulating encapsulation (346) to encapsulate the conductive pillars (424)
Lin does not disclose disposing a solder material on the second contact pad of the wiring substrate, and pressing the conductive pillars into the solder material and reflowing the solder material such that a space is formed between the redistribution circuit structure and the wiring substrate. However, Shimote discloses disposing a solder material (SD1) on the second contact pad (2BF) of the wiring substrate, placing the wiring substrate (3) onto the first surface of the redistribution circuit structure (2BF) such that the conductive pillar (3BP) protrudes into the solder material (SD1), and performing a reflow process (paragraph 88). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Lin to include the steps as taught by Shimote, since can provide a strong bond at the connection terminals (paragraph 88).
Regarding claim 25, Lin discloses providing a carrier (134) having a release layer (112) formed thereon, wherein the release layer (112) is between the redistribution circuit structure (124) and the carrier (134).
Regarding claim 26, Lin discloses forming a dielectric layer (114) over the release layer (112) before forming the redistribution circuit structure, wherein the first contact pads (116) of the redistribution circuit structure are formed to be in contact with the dielectric layer (114).
Regarding claim 27, Lin discloses after filling the space between the redistribution circuit structure (124) and the wiring substrate (154/160) with the insulating encapsulation (211), performing a de-bonding process to de-bond the dielectric layer (114) from the release layer (112).
Regarding claim 28, Lin discloses after performing the de-bonding process, patterning the dielectric layer (114) to reveal the first contact pads (116) of the redistribution circuit structure (116/118); and forming first conductive terminals (334) electrically connected to the first contact pads (336/334) of the redistribution circuit structure (116) (Figure 19).
Regarding claim 29, Lin discloses forming second conductive terminal (306) electrically connected to the second contact pads of the wiring substrate (170) (Figure 21B).
Regarding claim 30, Lin discloses a method, comprising:
forming a redistribution circuit structure (124) comprising first contact pads (116 contacting solder ball 432)
forming conductive pillars (424) and a semiconductor device (84) over the first contact pads (116) of the redistribution circuit structure (124)
after bonding the conductive pillars (424) with the solder material, forming an insulating encapsulation (346) between the redistribution circuit structure (124) and the wiring substrate (170), wherein the insulating encapsulation encapsulates the conductive pillars (424)
Lin does not disclose forming a solder material on second contact pads of a wiring substrate, forming a solder resist on the wiring substrate, placing the wiring substrate onto the redistribution circuit structure and pressing the conductive pillars into the solder material, and bonding the redistribution circuit structure and the wiring substrate through the joint of the conductive pillars and the solder material, wherein the solder resist laterally surrounds the solder material and the conductive pillars. However, Shimote discloses disposing a solder material (SD1) on the second contact pad (2BF) of the wiring substrate, forming a solder resist (SR1) on the wiring substrate, placing the wiring substrate (3) onto the first surface of the redistribution circuit structure (2BF) such that the joint of the conductive pillar (3BP) protrudes into the solder material (SD1), and performing a reflow process (paragraph 88). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Lin to include the steps as taught by Shimote, since can provide a strong bond at the connection terminals (paragraph 88).
Regarding claim 31, Lin discloses forming conductive terminals (334) electrically connected to the redistribution circuit structure (124).
Regarding claim 32, Lin discloses providing a chip package (84) over the redistribution circuit structure (124), wherein the chip package is electrically connected to the redistribution circuit structure (124).
Regarding claim 33, Lin discloses a solder cap over the first contact pads before forming the conductive pillars over the first contact pads (paragraph 66).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 2/10/2026 Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897