8Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-7, 11, and 21-29 are rejected under 35 U.S.C. 103 as being unpatentable over Eid (PGPub No. 20210043544) in further view of Fukuoka (PGPub No. 20220223544) and Kao (PGPub No. 20200411636).
Regarding claim 1, Eid teaches a semiconductor package, comprising: a package substrate (Fig. 1 and [0025] point to an IC package 100 comprising a package substrate 102.); a semiconductor die having a first surface attached to the package substrate and a second surface (Id. points to a temperature-sensitive (TS) component 106 (semiconductor die).); a heat sink coupled to the second surface of the semiconductor die (Fig. 1 and [0033] point to a heat sink 118.); and a heat dissipation layer interposed between the heat sink and the semiconductor die (Fig. 14 and [0047] point to an alternative embodiment of an IC package 100 comprising a heat spreader 114 (heat dissipation layer) located proximate to the top face of the TS component 106 (semiconductor die).); wherein the heat dissipation layer comprises one or more high-k dielectric materials (Figs. 1 & 14 and [0031] point to a heat spreader 114 (heat dissipation layer) which may include ceramics including diamond, silicon carbide, aluminum nitride, or any combination of the materials (high-k dielectric materials).).
Eid fails to teach wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink; and wherein the semiconductor die comprises: a first substrate having a first bonding layer disposed thereon, the first bonding layer comprising a first plurality of bonding structures; and a second substrate having a second bonding layer disposed thereon, the second bonding layer comprising a second plurality of bonding structures in contact with the first plurality of bonding structures.
Fukuoka teaches wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink ([0078] points to a heatsink 40 and a plating film (heat dissipation layer) of Ni, Au, or the like on the surface.).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Eid and Fukuoka, such that the heat dissipation layer directly contacts the heat sink in order to improve heat dissipation by providing the shortest thermal path possible.
Eid et al. still fails to teach wherein the semiconductor die comprises: a first substrate having a first bonding layer disposed thereon, the first bonding layer comprising a first plurality of bonding structures; and a second substrate having a second bonding layer disposed thereon, the second bonding layer comprising a second plurality of bonding structures in contact with the first plurality of bonding structures.
Kao teaches wherein the semiconductor die comprises: a first substrate having a first bonding layer disposed thereon, the first bonding layer comprising a first plurality of bonding structures; and a second substrate having a second bonding layer disposed thereon, the second bonding layer comprising a second plurality of bonding structures in contact with the first plurality of bonding structures (Fig. 3 and [0032] point to a semiconductor structure 300 comprising a first frontside bonding structure 342 (first bonding layer) disposed on the first frontside of a first semiconductor substrate 302 and bonded to a second frontside bonding structure 345 (second bonding layer) disposed over the second semiconductor substrate 304, both bonding structures comprising dummy structures 382 (first plurality of bonding structures; second plurality of bonding structures).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Kao, such that the semiconductor die comprises a first substrate, first bonding layer, a second substrate, and a second bonding layer in order to create a vertically stacked interconnect structure with a relatively small footprint.
Regarding claim 2, Eid teaches wherein the heat dissipation layer includes a plurality of structures formed of the one or more high-k dielectric materials and penetrating through the heat dissipation layer (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures).).
Regarding claim 3, Eid teaches wherein, when viewed from the top, the plurality of structures form a checkboard pattern (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures). In light of [0031] as well as the checkboard pattern shown in the heat sink 118 of Fig. 1, it is considered obvious that one of ordinary skill in the art could also arrange the heat spreader 114 (heat dissipation layer) in a similar checkboard pattern.).
Regarding claims 4-7, Eid teaches Eid teaches wherein, when viewed from the top, the plurality of structures form a two-dimensional array scattered across the heat dissipation layer, a single pillar at a center of the heat dissipation layer, a number of pillars arranged in parallel and extending across the heat dissipation layer, or a ring surrounding the heat dissipation layer, respectively (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures). In light of [0031], it is considered obvious that the features of the heat spreader 114 (plurality of structures) may be arranged according to a wide range of possible variations, such that one of ordinary skill in the art could form any one of the patterns disclosed by claims 4-7.).
Regarding claim 11, Eid teaches wherein the heat dissipation layer further comprises a material selected from a group consisting of: water; silicon; carbon nanotubes; diamond; boron nitride (BxNy), titanium nitride (TixNy), titanium oxide (TiOx), silicon carbide (SixCy), aluminum nitride (AlxNy); aluminum; copper; gallium; germanium; gold; iron; magnesium; nickel; platina; silver; titanium; tungsten; zinc; and combinations thereof (Figs. 1 & 14 and [0031] point to a heat spreader 114 (heat dissipation layer) which may include ceramics including diamond, silicon carbide, aluminum nitride, or any combination of the materials (high-k dielectric materials).).
Regarding claim 21, Eid teaches a semiconductor package, comprising: a package substrate (Fig. 1 points to an IC package 100 comprising a package substrate 102.); a first semiconductor die and a second semiconductor die bonded to each other, which are disposed over the package substrate (Fig. 1 and [0025] point to a temperature-sensitive (TS) component 106 which may be a single memory die or a stack of multiple memory devices (first semiconductor die; second semiconductor die).); a heat dissipation layer disposed over the bonded first and second semiconductor dies (Fig. 14 and [0047] point to an alternative embodiment of an IC package 100 comprising a heat spreader 114 (heat dissipation layer) located proximate to the top face of the TS component 106 (first and second semiconductor dies).); and a heat sink coupled to the bonded first and second semiconductor dies through the heat dissipation layer (Fig. 1 and [0033] point to a heat sink 118.); wherein the heat dissipation layer comprises one or more high-k dielectric materials ([0031] points to a heat spreader 114 (heat dissipation layer) which may include ceramics including diamond, silicon carbide, aluminum nitride, or any combination of the materials (high-k dielectric materials).); and wherein the first semiconductor die is disposed between the second semiconductor die and the package substrate (Fig. 1 and [0025] point to the TS component 106, which comprises a vertical stack of memory dies arranged such that the bottommost portion of the stack (first semiconductor die) is disposed between the topmost portion (second semiconductor die) and the package substrate 102.).
Eid fails to teach wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink; and wherein a metallization layer is disposed between the first semiconductor die and the second semiconductor die.
Fukuoka teaches wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink ([0078] points to a heatsink 40 and a plating film (heat dissipation layer) of Ni, Au, or the like on the surface.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid and Fukuoka, such that the heat dissipation layer directly contacts the heat sink in order to improve heat dissipation by providing the shortest thermal path possible.
Kao teaches wherein a metallization layer is disposed between the first semiconductor die and the second semiconductor die (Fig. 3 points to an interconnect structure 322 comprising a plurality of metal lines and vias.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Kao, such that a metallization layer is disposed between the first semiconductor die and the second semiconductor die in order to create an interconnect structure that operably couples/allows communication between the first and second dies.
Regarding claim 22, Eid teaches wherein the heat dissipation layer includes a plurality of structures formed of the one or more high-k dielectric materials and penetrating through the heat dissipation layer (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures).).
Regarding claim 23, Eid teaches wherein, when viewed from the top, the plurality of structures form a checkboard pattern (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures). In light of [0031] as well as the checkboard pattern shown in the heat sink 118 of Fig. 1, it is considered obvious that one of ordinary skill in the art could also arrange the heat spreader 114 (heat dissipation layer) in a similar checkboard pattern.).
Regarding claims 24-27, Eid teaches Eid teaches wherein, when viewed from the top, the plurality of structures form a two-dimensional array scattered across the heat dissipation layer, a single pillar at a center of the heat dissipation layer, a number of pillars arranged in parallel and extending across the heat dissipation layer, or a ring surrounding the heat dissipation layer, respectively (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures). In light of [0031], it is considered obvious that the features of the heat spreader 114 (plurality of structures) may be arranged according to a wide range of possible variations, such that one of ordinary skill in the art could form any one of the patterns disclosed by claims 24-27.).
Regarding claim 28, Eid teaches A semiconductor package, comprising: a package substrate (Fig. 1 points to an IC package 100 comprising a package substrate 102.); a first semiconductor die and a second semiconductor die bonded to each other, which are disposed over the package substrate (Fig. 1 and [0025] point to a temperature-sensitive (TS) component 106 which may be a single memory die or a stack of multiple memory devices (first semiconductor die; second semiconductor die).); a heat dissipation layer disposed over the bonded first and second semiconductor dies; and a heat sink coupled to the bonded first and second semiconductor dies through the heat dissipation layer (Fig. 14 and [0047] point to an alternative embodiment of an IC package 100 comprising a heat spreader 114 (heat dissipation layer) located proximate to the top face of the TS component 106 (first and second semiconductor dies).); and a redistribution structure disposed between the package substrate and the bonded first and second semiconductor dies (Fig. 1 points to a conductive pathway (redistribution structure) comprising solder bumps 144 and conductive contacts 140 and 142.); wherein the heat dissipation layer comprises one or more high-k dielectric materials, and further comprises a material selected from a group consisting of: water; silicon; carbon nanotubes; diamond; boron nitride (BxNy), titanium nitride (TixNy), titanium oxide (TiOx), silicon carbide (SixCy), aluminum nitride (AlxNy); aluminum; copper; gallium; germanium; gold; iron; magnesium; nickel; platina; silver; titanium; tungsten; zinc; and combinations thereof (Fig. 1 and [0033] point to a heat sink 118.); and wherein the heat dissipation layer comprises one or more high-k dielectric materials ([0031] points to a heat spreader 114 (heat dissipation layer) which may include ceramics including diamond, silicon carbide, aluminum nitride, or any combination of the materials (high-k dielectric materials).).
Eid fails to teach wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink; and a metallization layer disposed between the second semiconductor die and the redistribution structure, wherein the metallization layer comprises a plurality of conductive lines and a plurality of conductive vias.
Fukuoka teaches wherein the heat dissipation layer comprises a layer surface in physical contact with the heat sink ([0078] points to a heatsink 40 and a plating film (heat dissipation layer) of Ni, Au, or the like on the surface.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid and Fukuoka, such that the heat dissipation layer directly contacts the heat sink in order to improve heat dissipation by providing the shortest thermal path possible.
Kao teaches a metallization layer disposed between the second semiconductor die and the redistribution structure, wherein the metallization layer comprises a plurality of conductive lines and a plurality of conductive vias (Fig. 3 points to an interconnect structure 322 comprising a plurality of metal lines and vias.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Kao, such that a metallization layer is disposed between the first semiconductor die and the second semiconductor die in order to create an interconnect structure that operably couples/allows communication between the first and second dies.
Regarding claim 29, Eid teaches wherein the heat dissipation layer includes a plurality of structures formed of the one or more high-k dielectric materials and penetrating through the heat dissipation layer (Figs. 1, 3, & 21, and [0031] point to a heat spreader 114 (heat dissipation layer) which may include leg portions and/or pedestals, ribs, or other three-dimensional features (plurality of structures).).
Claim(s) 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al. in further view of Tsutsui (PGPub No. 20200402888).
Regarding claim 8, Tsutsui teaches wherein the heat dissipation layer further comprises a fluid tunnel with an inlet and an outlet (Figs. 9-10 and [0155-156] point to an interposer 420 (heat dissipation layer) comprising a heat pipe 500 (fluid tunnel) inserted into a groove 424 and extending from the one end 423 (inlet) to the other end 429 (outlet).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Tsutsui, such that the heat dissipation layer comprises a fluid tunnel in order to better transfer heat via liquid cooling.
Regarding claim 9, Tsutsui teaches wherein the inlet and outlet are formed on opposite sides of the heat dissipation layer, respectively (Figs. 9-10 and [0155-156] point to an interposer 420 (heat dissipation layer) comprising a heat pipe 500 (fluid tunnel) inserted into a groove 424 and extending from the one end 423 (inlet) to the other end 429 (outlet). It is considered obvious that one of ordinary skill in the art could form said inlet and outlet on opposite sides in an attempt to, for example, avoid hot spots and/or ensure even flow by creating a unidirectional flow path.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Tsutsui, such that the heat dissipation layer comprises a fluid tunnel with an inlet and outlet positioned on opposite sides to better optimize the flow of coolant and by extension improve heat dissipation.
Regarding claim 10, Tsutsui teaches wherein the inlet and outlet are formed on a same side of the heat dissipation layer (Figs. 9-10 and [0155-156] point to an interposer 420 (heat dissipation layer) comprising a heat pipe 500 (fluid tunnel) inserted into a groove 424 and extending from the one end 423 (inlet) to the other end 429 (outlet).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Eid et al. and Tsutsui, such that the heat dissipation layer comprises a fluid tunnel with an inlet and outlet positioned on the same side to better optimize the flow of coolant and by extension improve heat dissipation.
Response to Arguments
Applicant’s arguments, see Remarks, filed 04/06/2026, with respect to the rejection of claim 1 under 35 U.S.C. §112(a) have been fully considered and are persuasive. The rejection of said claim has been withdrawn.
Applicant’s arguments, see Remarks, filed 04/06/2026, with respect to the rejection(s) of claim(s) 1, 21, and 28 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Eid et al. in further view of Kao (PGPub No. 20200411636).
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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