DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-16, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114883196 (Wu et al), US 20230140738 (Bae), and US 20200303269 (Okumura). For convenience the examiner cites to a machine-translation by Espacenet of Wu provided in a previous office action.
As to Claim 1, Wu teaches a package substrate, comprising:
a substrate component (Wu Fig 1, component 130A) laterally covered by an insulating encapsulation (encapsulation 190 laterally around 130A);
a redistribution structure disposed over the substrate component and the insulating encapsulation (layer 120 above 130A and 190) and electrically connected with the substrate component at a first side of the redistribution structure (contacts 180 between 120 and 130A), wherein the redistribution structure comprises:
a dielectric layer at a second side opposite to the first side (details of redistribution structure shown in Fig 13; dielectric layer 1220 opposite to top of 120);
at least one conductive pad disposed in the dielectric layer (details of redistribution structure shown in Fig 20; pad 1214), wherein a portion of the at least one conductive pad is exposed by the dielectric layer (1214 exposed through layer 1210, labeled on included Annotated Wu Fig 1); and
PNG
media_image1.png
732
1317
media_image1.png
Greyscale
at least one conductive pattern in contact with the portion of the at least one conductive pad (conductive pattern 1012 shown on Fig 12 and included in annotated Fig 1 below), where the at least one conductive pad is closer to the substrate component than the at least one conductive pattern (1214 closer to substrate than 1012).
Wu does not explicitly teach a probe head electrically connected with the at least one conductive pattern and the at least one conductive pad. Rather, Wu discloses an IC package (110) electrically connected with the at least one conductive pattern and the at least one conductive pad. Additionally, Wu does not motivate a hardness of the at least one conductive pattern being greater than a hardness of the at least one conductive pad, though examiner notes Wu discloses those elements being of materials which could satisfy this property, e.g., 1012 and 1214 may each comprise “copper, titanium, tungsten, aluminum, or the like”; ¶0041 and ¶0043. i.e., 1214 may comprise gold and 1012 comprise copper, where copper inherently has a hardness greater than that of gold.
Bae teaches a package similar to that of Wu, and explicitly teaches a substrate component (Bae Fig 16, 500), a redistribution structure thereon (layers 101-105 on 500), and a probe head electrically connected with a conductive pattern and a conductive pad (probe head 620 contacting pads on top of layer 105 and thereby connected to conductive patterns in 101-105). It would have been obvious to one of ordinary skill in the art at the time of filing to combine the package structure taught by Wu with the use of a probe head on the redistribution structure taught by Bae in order to test the connections formed within the package substrate.
Still, the combination of Wu and Bae does not explicitly teach wherein a hardness of the at least one conductive pattern is greater than a hardness of the at least one conductive pad.
Okumura teaches a package similar to that of Wu and Bae, and explicitly teaches a conductive pattern having a hardness greater than that of a conductive pad below it (Okumura Fig 4, 31 harder than 11 ¶0091).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the relative hardnesses of a conductive pattern and conductive pad taught by Okumura with the package taught by Wu and Bae in order to protect the electrode from damage during the testing process (Okumura ¶0091).
As to Claim 2, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches wherein the at least one conductive pattern is protruded from the dielectric layer (Annotated Fig 1, 1012 protrudes from layer 1220).
As to Claim 3, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches wherein the portion of the at least one conductive pad is a surface of the at least one conductive pad facing away from the substrate component (upper surface of 1214 faces away from substrate). Bae, as applied to claim 1, then teaches this surface facing away from the substrate also faces towards the probe head.
As to Claim 4, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches the conductive pad including a surface of the at least one conductive pad facing away from the substrate and a sidewall contacting that surface (pad 1214 has top surface facing away and sidewalls). Bae, as applied to claim 1, then teaches this surface facing away from the substrate also faces towards the probe head.
As to Claim 6, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches wherein a surface of the at least one conductive pattern faces away from the core structure has a surface at a level height higher than that of a surface of the dielectric layer facing away from the substrate. (Annotated Fig 1, pad 1214 higher than dielectric layer 1220). Bae, as applied to claim 1, then teaches this surface facing away from the substrate also faces towards the probe head.
As to Claim 7, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu teaches the structure further comprises a circuit board electrically connected with the substrate component (Fig 23B, PCB 2710 connected to substrate component above via contacts 150), wherein the substrate component is located between the circuit board and the redistribution structure (Fig 1 shows contacts 150 on bottom side of substrate component. i.e., Fig 23B shows substrate component between circuit board below and redistribution structure above).
As to Claim 8, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches wherein the substrate component (130A) comprises:
a core layer (annotated Fig 1, core portion 132);
a first build-up structure and a second build-up structure disposed on opposing sides of the core layer (136A and 136B on top and bottom of 132, respectively), wherein the first build-up structure is located nearer to the redistribution structure than the second build-up structure (136A closer to 120 than 136B is to 120); and
through core vias penetrating through the core layer and coupled to the first and second build-up structures (core vias 134 connect both sides of core 132; ¶0027) .
As to Claim 9, the combination of Wu, Bae, and Okumura teaches the package structure of claim 1. Wu further teaches a material of the at least one conductive pattern comprises titanium (Wu ¶0041)
As to Claim 10, Wu teaches a package structure, comprising:
a substrate component (Wu Fig 1, 130A) comprising a core layer (132), a first build-up structure and a second build-up structure disposed on opposite sides of the core layer (136A and 136B on top and bottom sides of 132, respectively) and electrically coupled to each other by through core vias penetrating through the core layer (core vias 134 electrically connect top and bottom sides of 132 ¶0027);
a redistribution structure (120) comprising a first portion (Fig 13 shows detailed layer structure of 120. First portion comprising layers 1210, 1220, and metal features therein), a second portion (comprising layer 1230) and a third portion (comprising layer 1240. These three portions are also labeled in annotated Fig 1), the third portion disposed over and electrically coupled to the first build-up structure of the substrate component (1230 over 136A and electrically coupled via metallization layers between them), the first portion stacked on the third portion along a first direction and electrically coupled to the third portion (1210+1220 above 1240 along the vertical axis in Fig 1, and electrically coupled via metallization layers between them), and the second portion disposed between and electrically coupled to the third portion and the first portion (1230 between 1240 and 1210+1220), wherein the first portion comprises:
a dielectric layer (comprising dielectric layers 1210+1220);
at least one conductive pad (1012) laterally covered by the dielectric layer along a second direction perpendicular to the first direction (1012 laterally covered by layer 1210 along left-right direction of Fig 1), wherein a portion of the at least one conductive pad is exposed by the dielectric layer (top of 1012 exposed through layer 1210); and
at least one conductive pattern in contact with the portion of the at least one conductive pad (pattern 1012 in contact with pad 1214; see annotated Fig 1), and at the at least one conductive pad is closer to the substrate component than the at least one conductive pattern (1214 below 1012).
Wu does not explicitly teach a probe head electrically connected with the at least one conductive pattern and the at least one conductive pad. Rather, Wu discloses an IC package (110) electrically connected with the at least one conductive pattern and the at least one conductive pad.
Bae teaches a package similar to that of Wu, and explicitly teaches a substrate component (Fig 16, 500), a redistribution structure thereon (layers 101-105 on 500), and a probe head electrically connected with a conductive pad and the dielectric layer surrounding it (probe head 620 contacting pads on top of layer 105 and thereby connected to conductive patterns in 101-105).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the package structure taught by Wu with the use of a probe head on the redistribution structure taught by Bae in order to test the connections formed within the package substrate.
Still, Wu and Bae fail to teach wherein a hardness of the conductive pattern is greater than a hardness of the conductive pad.
Okumura, with the same mapping and for the same reasons as applied to the claim 1 rejection above, teaches this further limitation.
As to Claim 11, the combination of Wu, Bae, and Okumura teaches the package structure of claim 10. Bae, as applied to claim 9, further teaches wherein the probe head is in direct contact with the at least one conductive pattern. (probe head 620, when incorporated into Wu Fig 1, necessarily makes direct contact with 1012)
As to Claim 12, the combination of Wu, Bae, and Okumura teaches the package structure of claim 10. Wu further teaches wherein the portion of the at least one conductive pad is a surface exposed by the dielectric layer facing away from the core structure (top surface of 1214 exposed through dielectric layer 1220). Bae, as applied to claim 10, then teaches this surface facing away from the core structure also faces towards the probe head.
As to Claim 13, the combination of Wu, Bae, and Okumura teaches the package structure of claim 12. Wu further teaches wherein the surface of the at least one conductive pad is coplanar with a surface of the dielectric layer facing toward the probe head. (Fig 1, top of 1214 coplanar with a layer of 1210 which is at the same height as top of 1214)
As to Claim 14, the combination of Wu, Bae, and Okumura teaches the package structure of claim 12. Wu further teaches wherein the surface of the at least one conductive pad is lower than a surface of the dielectric layer facing away from the core structure (pad 1214 above the top surface of dielectric layer 1220, where top surface of 1220 faces away from core structure). Bae, as applied to claim 12, then teaches this surface facing away from the core structure also faces towards the probe head.
(Examiner notes for additional clarity that the element mapping of the “surface of the dielectric layer” in Claim 14 is different than that mapped in Claim 13.)
As to Claim 15, the combination of Wu, Bae, and Okumura teaches the package structure of claim 10. Wu further teaches wherein the portion of the at least one conductive pad exposed by the dielectric layer includes a surface of the at least one conductive pad facing away from the core structure and a sidewall of the at least one conductive pad contacting with the surface of the at least one conductive pad (top surface of 1214 faces up in Fig 1. Pad 1214 has sidewalls in contact with its top surface). Bae, as applied to claim 10, then teaches this surface facing away from the core structure also faces towards the probe head.
As to Claim 16, the combination of Wu and Bae teaches the package structure of claim 10. Wu further teaches wherein the first portion further comprises at least one conductive via embedded in the dielectric layer (conductive via connecting to a pad 1016 is embedded in dielectric layer 1210) and in contact with the at least one conductive pad, and the at least one conductive via is tapered from the third portion toward the first portion (Fig 12 shows more detail of layered structure, where taper of via connected to pad 1012 is visible. Width of via changes along direction normal to 902, i.e. is tapered along the direction from third portion to first portion when viewing complete structure in Fig 1).
As to Claim 21, the combination of Wu, Bae, and Okumura teaches the package structure of claim 4. Wu further teaches wherein the surface of the at least one conductive pad facing toward the probe head (1214 facing up which, when combined with Bae, is toward a probe head) is located at a level height higher than that of a surface of the dielectric layer facing toward the probe head (top of 1214 higher than surface between 1210 and 1220).
Response to Arguments
Applicant’s arguments, filed October 31 2025, with respect to the rejection(s) of claim(s) 1-16 under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new rejection has been made, namely by remapping the claimed conductive pads and conductive patterns, as well as with the inclusion of newly cited art Okumura.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights