Prosecution Insights
Last updated: October 01, 2026
Application No. 17/890,571

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

Non-Final OA §112
Filed
Aug 18, 2022
Priority
Apr 04, 2022 — provisional 63/327,324
Examiner
BOULGHASSOUL, YOUNES
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
467 granted / 529 resolved
+20.3% vs TC avg
Moderate +7% lift
Without
With
+7.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
26 currently pending
Career history
556
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
38.9%
-1.1% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
23.1%
-16.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 529 resolved cases

Office Action

§112
Attorney’s Docket Number: TSMC/P20214090US01 Filing Date: 08/18/2022 Continuity Data: RCE filed on 08/23/2026 Claimed Priority Date: 04/04/2022 (PRO 63/327,324) Applicants: Huang et al. Examiner: Younes Boulghassoul DETAILED ACTION This Office action responds to the Request for Continued Examination (RCE) filed on 08/23/2026. Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's amendment filed on 08/23/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 22-23 and 27, and added new claims 29-31. Accordingly, pending in this application are claims 1-14, 21, 24, and 28-31. Response to Amendment Applicant’s amendments to the Specification have overcome the objections to Drawings, as previously set forth in the Final Office action mailed on 06/03/2026. Accordingly, all previous objections to drawings are hereby withdrawn. Applicant’s amendments to the Claims have overcome the respective claim objections and claim rejections under 35 U.S.C. 112, 35 U.S.C. 102, and 35 U.S.C. 103, as previously set forth in the same Office action. Accordingly, all previous claim rejections are hereby also withdrawn. However, applicant’s amendments have introduced new issues, and new grounds of rejection are presented below, as necessitated by applicant’s amendments to the claims. Specification The disclosure is objected to because of the following informalities: - The amendment to the Specification filed on 08/04/2026 and reciting at Par. [0033], L.7-9 “The resulting sacrificial gate 222s, 222l have gate lengths GL1/GL2/GL3 and LGL1/LGL2/LGL3 at the levels LV1/LV2/LV3” is improper because the word “structures” is also newly added and should be clearly underlined as an amendment. Appropriate correction is required. Claim Objections Claims 1, 9, 21 and 28 are objected to because of the following informalities: - Claim 1, L. 19; Claim 9, L. 36; and Claim 28, L. 4-5: amend to -- a process temperature --, in accordance with the disclosure (see, e.g., Par. [0036]) Claim 21, L. 12-14: consider reciting the limitations “wherein a top surface of the first top conductive layer is lower than the first pair of sidewall spacers and is level with a top surface of the first gate dielectric layer” before reciting the limitation “a second semiconductor fin” at L. 12 for clarity, as the “wherein…” limitations are directed to features associated with the first gate structure, and not the second semiconductor fin. Appropriate corrections are required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 1-8 and 28-31 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 has been amended to recite the limitation “wherein etching the sacrificial gate electrode layer comprises: performing a first etch to etch back the sacrificial gate electrode layer to a top surface of the semiconductor fin; and performing a second etch to etch back the sacrificial gate electrode layer to adjacent to a top surface of the STI, and at least one of a ratio of processing gases, a process temperate, a bias voltage, and a duty cycle is adjusted from the first etch to the second etch;” at L. 13-20. However, claim 1 is devoid of any prior recitation of a “sacrificial gate electrode layer” feature, and of any prior recitation of a step of “etching the sacrificial gate electrode layer” for which the newly amended “wherein” clause would be further limiting. Additionally, the newly amended “wherein” clause is only supported in the original disclosure with respect to the step of adjusting the profile of the sacrificial gate electrode layer (see, e.g., Fig. 1, step 106). However, it has been recited between later steps of “removing the sacrificial gate electrode to form a gate cavity” (see, e.g., Fig. 1, step 114) and “etching back a portion of the sidewall spacers to a first level” (see, e.g., Fig. 1, step 116), thus adding further confusion as to the intended scope of the claimed invention, because the newly amended “wherein” clause is unrelated to the recited limiting step of “removing the sacrificial gate electrode to form a gate cavity”. Accordingly, the amendments to claim 1 raise both antecedent basis and clarity issues, thus rendering the claim indefinite. Claims 2-8 and 29-31 depend from claim 1 thus inherit the deficiencies identified supra. Claim 28 recites the limitation “performing a third etch to tune a sidewall profile of the sacrificial gate electrode” in L. 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting -- performing a third etch to tune a sidewall profile of the sacrificial gate electrode layer--, in accordance with the claim language introduced in amended claim 9 at L. 31-35: “performing a first etch to etch back the sacrificial gate electrode layer to a first level…; and performing a second etch to etch back the sacrificial gate electrode layer to a second level,…”, until further clarifications are provided by applicant. Claim 29 recites the limitation “wherein etching the sacrificial gate electrode layer further comprises” in L. 1-2. There is insufficient antecedent basis for this limitation in the claim. Also see comments stated above in Par. 10 with regards to Claim 1, which are considered repeated here. Claim 30 recites the limitation “wherein the work function layer has a U-shape cross section, and the conductive filling layer is inside the U-shape of the work function layer.” in L. 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the claim will be construed as reciting -- wherein the work function metal layer has a U-shape cross section, and the conductive filling layer is inside the U-shape of the work function metal layer.--, in accordance with the claim language introduced in amended claim 1 at L. 24: “forming a work function metal layer over the gate dielectric layer…”, until further clarifications are provided by applicant. Allowable Subject Matter Claims 9-14, 21, and 24 are allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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Prosecution Timeline

Aug 18, 2022
Application Filed
Sep 10, 2025
Non-Final Rejection mailed — §112
Feb 10, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §112
Aug 04, 2026
Response after Non-Final Action
Aug 23, 2026
Request for Continued Examination
Aug 27, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+7.0%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 529 resolved cases by this examiner. Grant probability derived from career allowance rate.

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