Attorney’s Docket Number: TSMC/P20214090US01
Filing Date: 08/18/2022
Claimed Priority Date: 04/04/2022 (PRO 63/327,324)
Applicants: Huang et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 02/10/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 02/10/2026, responding to the Office action mailed on 09/10/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 25-26 and added new claims 27-28. Accordingly, pending in this application are claims 1-14, 21-24, and 27-28.
Response to Amendment
Applicant’s amendments to the Specification and Drawings have overcome the objections to Specification and Drawings, as set forth in the Non-Final Office action mailed on 09/10/2025. Accordingly, all prior objections are hereby withdrawn. However, new objections to drawings are raised, as detailed below.
Applicant’s amendments to the Claims have overcome the claim rejections under 35 U.S.C. 112, 35 U.S.C. 102, and 35 U.S.C. 103, as previously formulated in the same office action. However, some of the previously presented prior art remains relevant, and new grounds of rejections are presented below, as necessitated by Applicant’s amendments to the claims.
Drawings
The drawings are objected to because of the following inconsistencies:
- Figs. 5B-5C and 6B-6C: all instances of reference character “212s” associated with sacrificial gate structure 222l should be changed to --212l--, in accordance with Par. [0033], L. 8: “The resulting sacrificial gate electrode 212s, 212l have gate lengths…”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 21 is objected to because of the following informalities:
- L. 12-14: consider reciting the limitations “wherein a top surface of the first top conductive layer is lower than the first pair of sidewall spacers and is level with a top surface of the first gate dielectric layer” before reciting the limitation “a second semiconductor fin” for clarity, as they are directed to features associated with the first semiconductor fin.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9-14 and 27-28 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 recites the limitation “recess etching the semiconductor fin on opposite sides of the first and second sacrificial gate structures” in L.19-20. There is insufficient antecedent basis for this limitation in the claim and it is unclear which one of the previously recited “plurality of semiconductor fins” is this limitation directed to, therefore rendering the claim indefinite. For the purpose of examination, the claim will be construed as reciting -- recess etching at least one of the plurality of semiconductor fins on opposite sides of the first and second sacrificial gate structures--, until further clarifications are provided by applicant.
Claims 10-14 and 27-28 depend from claim 9 thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US2021/0343851).
Regarding Claim 1, Wang (see, e.g., Figs. 1-22) shows all aspects of the instant invention, including a method for forming a semiconductor device, comprising:
- forming a semiconductor fin (e.g., fin structure 20) (see, e.g., Figs. 1-5)
- forming a sacrificial gate structure over the semiconductor fin (e.g., sacrificial gate structure 40), wherein the sacrificial gate structure comprises a sacrificial gate dielectric layer (e.g., sacrificial gate dielectric layer 42) and a sacrificial gate electrode (e.g., sacrificial gate electrode 44) (see, e.g., Figs. 6-7)
- forming sidewall spacers (e.g., sidewall spacers 45) on side surfaces of the sacrificial gate structure (see, e.g., Fig. 8)
- recess etching the semiconductor fin on opposing sides of the sacrificial gate structure (see, e.g., Fig. 9)
- forming source/drain regions (e.g., source/drain (S/D) epitaxial layers 50) on the opposing sides of the sacrificial gate structure (see, e.g., Fig. 10)
- depositing a CESL (contact etch stop layer) (e.g., insulating liner layer/etch stop layer 60) on the source/drain regions (see, e.g., Fig. 11)
- depositing an ILD (interlayer dielectric) layer (e.g., ILD layer 65) on the CESL (see, e.g., Fig. 11)
- removing the sacrificial gate electrode to form a gate cavity (e.g., gate space 49) (see, e.g., Fig. 12)
- etching back a portion of the sidewall spacers to a first level, wherein the CESL is exposed to the gate cavity (see, e.g., Par. [0063] and Fig. 17A-C: etch back by one or more dry and/or wet etching operations)
- depositing a gate dielectric layer (e.g., gate dielectric layer 82) on the CESL exposed to the gate cavity (see, e.g., Fig. 18A)
- forming a work function metal layer (e.g., WFM layers 84 or 85) over the gate dielectric layer (see, e.g., Figs. 18C-18E)
- etching back the work function metal layer to a second level (see, e.g., Par. [0071] and Fig. 19A: WFs 84 or 85 are etched back)
- forming a top conductive layer (e.g., contact metal layer 87) on the work function metal layer, wherein a top surface of the top conductive layer is lower than a top surface of the sidewall spacers (e.g., 45) (see, e.g., Fig. 19B)
- forming a SAC (self-aligned contact) layer (e.g., gate cap insulating layer 90) (see, e.g., Fig. 19C)
Furthermore, Wang (see, e.g., Figs. 19B and 22G, and Par. [0092]) discloses that a top surface of contact metal layer 87 can be formed to be substantially coplanar with a top surface of gate dielectric layer 82. Therefore, Wang also shows that a top surface of the top conductive layer (e.g., 87) is level with a top surface of the gate dielectric layer (e.g., 82).
Regarding Claim 2, Wang (see, e.g., Figs. 22A-G and Par. [0085]-[0092]) shows that his invention is adapted for the particular manufacturing of long channel FETs, comprising:
- depositing a conductive filling layer (e.g., conductive glue/barrier layer 86) on the work function metal layer (e.g., 85) (see, e.g., Fig. 22D)
- etching back the conductive filling layer to the second level (see, e.g., Fig. 22F: 86 etched-back to the same level as 85), wherein the top conductive layer (e.g., 87) is formed on the conductive filling layer and the work function metal layer (see, e.g., Fig. 22G).
Regarding Claim 3, Wang (see, e.g., Fig. 22E) shows depositing a dielectric filling layer (e.g., cap insulating layer 185) on the conductive filling layer, wherein the dielectric filling layer fills the gate cavity.
Regarding Claim 4, Wang (see, e.g., Fig. 22G and Par. [0092]) discloses forming a gate cap insulating layer 90 over contact metal layer 87, similar to Figs. 19B-C. Therefore, Wang shows a step wherein the SAC layer (e.g., 90) is deposited between the CESL (e.g., 60) (illustrated by top portion of dashed contour line) and the dielectric filling layer (e.g., 185).
Regarding Claim 5, Wang (see, e.g., Figs. 19B and Fig. 22G) shows that the second level (e.g., level of 85 or 86) is lower than the first level (e.g., level of recessed gate sidewalls 45, illustrated by step portion of dashed contour line).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US2021/0343851) in view of Kim et al. (US2018/0254338).
Regarding Claim 6, Wang (see, e.g., Fig. 7 and Par. [0041]-[0043]) discloses that a process of mask-assisted patterning a sacrificial gate dielectric layer 42 and a sacrificial gate electrode layer 44 results in a sacrificial gate structure 40 having substantially vertical sidewalls. Therefore, Wang is silent about having a step of adjusting a profile of the sacrificial gate electrode such that a lower portion of the sacrificial gate electrode adjacent to a top surface of the semiconductor fin is narrower than the sacrificial gate electrode near the first level.
Kim (see, e.g., Figs. 14-18 and Par. [0037]), on the other hand and in the same field of endeavor, teaches that adjusting the profile of a sacrificial gate electrode 135 to exhibits an inverted trapezoidal cross section wherein a width of the sacrificial gate electrode is narrowing from a top-most portion to a lower-most portion, including adjacent to a top surface of semiconductor fin 105, enables the formation of gate spacers 150 having thicker lower portions, thus preventing electrical short failure between later-formed replacement gates 140 and source/drain regions 110.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a step of adjusting a profile of the sacrificial gate electrode as claimed in the method of Wang, as taught by Kim, to enables the formation of gate spacers having thicker lower portions, and preventing electrical short failure between later-formed replacement gates and source/drain regions.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US2021/0343851) in view of Kim et al. (US2018/0254338), and in further view of Chen et al. (US2020/0006148).
Regarding Claim 7, Kim (see, e.g., Fig. 17 and Par. [0073]) discloses that gate mask patterns 136 are used as an etching mask to anisotropically etch the sacrificial gate electrode layer 135a and the sacrificial gate insulating layer 132a, so that slanted sacrificial gate patterns 135 and sacrificial gate insulating patterns 132 may be formed. However, Wang in view of Kim is silent about a step of adjusting a ratio of passivation gas and etching gas during formation of the sacrificial gate structure.
Chen (see, e.g., Figs. 12-14 and Par. [0039]-[0045]), on the other hand and in the same field of endeavor, teaches that plasma etching is a suitable anisotropic etching method for patterning a dummy gate electrode layer and a dummy gate dielectric layer to form gate stacks, due to its simplicity of controlling the plasmas, wherein many plasma parameters, such as gas pressure, chemistry, and the source/biased power can be varied or modified during the dry etch process to fine tune resulted gate stack sidewall profile. In particular, the plasma etchant 132 can be a gas mixture of Cl2 (etchant gas) and O2 (passivation gas), whose flow rates can be modulated to exhibit stronger lateral etching capability so as to tailor the dummy gate shape.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a step adjusting a ratio of passivation gas and etching gas during formation of the sacrificial gate structure in the method of Wang in view of Kim, as taught by Chen, to modulate the lateral etching capability of the gas plasma mixture so as to tailor the dummy gate shape.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US2021/0343851) in view of Lim et al. (US2020/0058553).
Regarding Claim 8, while Wang (see, e.g., Par. [0044]-[0045]) discloses that gate spacer 45 can be a dielectric of, e.g., SiN or SiON, he is silent about the sidewall spacers comprising a low-k dielectric material. Lim (see, e.g., Fig. 14 and Par. [0020],[0041]), on the other hand and in the same filed of endeavor, teaches that dielectric materials such as, e.g., silicon oxide, silicon nitride, silicon oxy-nitride, are suitable materials for forming gate spacers 152/342.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have silicon oxide as the material of the sidewall spacers in the method of Wang, because silicon oxide is a known suitable material for implementing a gate sidewall spacer in a FET device, as suggested by Lim, and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Therefore, Wang in view of Lim teaches that the sidewall spacers (e.g., 45) comprise a low-k dielectric material (e.g., silicon oxide).
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US2021/0343851) in view of Chen et al. (US2020/0006148).
Regarding Claim 9, Wang (see, e.g., Figs. 1-19) shows most aspects of the instant invention, including a method, comprising:
- forming a plurality of semiconductor fins along a first direction (e.g., fin structures 20 along direction X), wherein the plurality of semiconductor fins extend from a STI (shallow trench isolation) layer (e.g., STI 30) (see, e.g., Figs. 1-5)
- depositing a sacrificial gate dielectric layer (e.g., sacrificial gate dielectric layer 42) over the plurality of semiconductor fins and the STI layer (see, e.g., Fig. 6)
- depositing a sacrificial gate electrode layer on the sacrificial gate dielectric layer (see, e.g., Par. [0041]: a sacrificial gate electrode layer is blanket deposited on the sacrificial gate dielectric layer and over the fin structures)
- forming a first gate mask along a second direction on the sacrificial gate electrode layer (e.g., mask layer 48 along direction Y), wherein the first gate mask has a first gate length along the first direction,
- etching the sacrificial gate electrode layer using the first gate mask to form a first sacrificial gate structure (e.g., sacrificial gate structure 40 comprising sacrificial gate dielectric layer 42 and sacrificial gate electrode 44) (see, e.g., Fig. 7)
- forming sidewall spacers (e.g., sidewall spacers 45) on side surfaces of the first sacrificial gate structure (see, e.g., Fig. 8)
- recess etching the semiconductor fin on opposite sides of the first sacrificial gate structure (see, e.g., Fig. 9)
- forming source/drain regions (e.g., source/drain (S/D) epitaxial layers 50) on opposing sides of the first sacrificial gate structure (see, e.g., Fig. 10)
- depositing a CESL (contact etch stop layer) (e.g., insulating liner layer/etch stop layer 60) on the source/drain regions (see, e.g., Fig. 11)
- depositing an ILD (interlayer dielectric) layer (e.g., ILD layer 65) on the CESL (see, e.g., Fig. 11)
- removing the first sacrificial gate structure electrode layer to form a first gate cavity (e.g., gate space 49) (see, e.g., Fig. 12)
- etching back a portion of the sidewall spacers (see, e.g., Par. [0063] and Fig. 17A-C: etch back by one or more dry and/or wet etching operations)
- forming a first replacement gate structure after etching back the sidewall spacers (see, e.g., Par. [0064]-[0077] and Figs. 18-19: formation of gate dielectric layer 82, WF layers 84-85, conductive glue/barrier layer 86, and contact metal layer 87)
Additionally, Wang (see, e.g., Figs. 22A-G and Par. [0085]-[0092]) teaches that his invention can be readily adapted to the manufacture of metal gate structures for both narrow channel FinFETs (e.g., PMOS1, PMOS2, and NMOS1) and a long channel FinFET (e.g., NMOS2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the steps directed to manufacturing the first/narrow channel FinFET also be applied to the manufacture of a second/long channel FinFET in the method of Wang, because such steps are known in the semiconductor art for manufacturing a plurality of metal gate structures having different channel lengths, as taught by Wang himself, and applying known method steps for their conventional purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Therefore, Wang (see, e.g., Figs. 1-22) also teaches the limitations directed to the manufacturing of a second/long channel FinFET, comprising:
- forming a first gate mask (e.g., first gate mask 48 associated with the manufacturing of narrow channel FinFET) and a second gate mask (e.g., second gate mask 48 associated with the manufacturing of long channel FinFET) along a second direction on the sacrificial gate electrode layer, wherein the first gate mask has a first gate length along the first direction, the second gate mask has a second gate length along the first direction, and the first gate mask is shorter than the second gate mask
- etching the sacrificial gate electrode layer using the first gate mask and the second gate mask to form a first sacrificial gate structure (e.g., first sacrificial gate structure 40 associated with the manufacturing of narrow channel FinFET) and a second sacrificial gate structure (e.g., second sacrificial gate structure 40 associated with the manufacturing of long channel FinFET)
- forming sidewall spacers on side surfaces of the first and second sacrificial gate structures
- recess etching the semiconductor fin on opposite sides of the first and second sacrificial gate structures
- forming source/drain regions on opposing sides of the first and second sacrificial gate structures
- removing the first and second sacrificial gate structures electrode layer to form a first gate cavity (e.g., first cavity 49 associated with the manufacturing of narrow channel FinFET) and a second gate cavity (e.g., second cavity 49 associated with the manufacturing of long channel FinFET)
- forming a first replacement gate structure (e.g., first replacement metal gate associated with the manufacturing of narrow channel FinFET) and a second replacement gate structure (e.g., second replacement metal gate associated with the manufacturing of long channel FinFET) after etching back the sidewall spacers (see, e.g., Fig. 22G).
However, while Wang (see, e.g., Fig. 7 and Par. [0041]-[0043]) discloses that a process of mask-assisted patterning a sacrificial gate dielectric layer 42 and a sacrificial gate electrode layer 44 results in a sacrificial gate structure 40 having substantially vertical sidewalls, he is silent about wherein etching the sacrificial gate electrode layer comprises: generating a plasma from an etching gas and a passivation gas; and adjusting a ratio of the etching gas and the passivation gas to adjust a profile of the first and second sacrificial gate structure.
Chen (see, e.g., Figs. 12-13 and Par. [0039]-[0045]), on the other hand and in the same field of endeavor, teaches that plasma etching is a suitable anisotropic etching method for patterning a dummy gate electrode layer and a dummy gate dielectric layer to form gate stacks, due to its simplicity of controlling the plasmas, wherein many plasma parameters, such as gas pressure, chemistry, and the source/biased power can be varied or modified during the dry etch process to fine tune resulted gate stack sidewall profile. In particular, the plasma etchant 132 can be a gas mixture of Cl2 (etchant gas) and O2 (passivation gas), whose flow rates can be modulated to exhibit desired lateral etching capability so as to tailor the shape of dummy gate material 112.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the step of etching the sacrificial gate electrode layer comprising the steps of generating a plasma from an etching gas and a passivation gas and adjusting a ratio of said gases to adjust a profile of the first and second sacrificial gate structure in the method of Wang, as taught by Chen, to modulate the lateral etching capability of the gas plasma mixture so as to tailor the dummy gate shape.
Regarding Claim 10, Chen (see, e.g., Figs. 10-13 and Par. [0039]-[0045]) teaches a step of plasma etching 132 wherein etching the dummy gate stack 112 comprises adjusting the mixture of the etching gas (e.g., Cl2) and the passivation gas (e.g., O2) to generate a straight profile (see, e.g., Figs. 13A-B). Therefore, Wand in view of Chen teaches that etching the sacrificial gate electrode layer comprises adjusting the ratio of the etching gas and the passivation gas to generate a straight profile.
Regarding Claim 11, Chen (see, e.g., Figs. 10-13 and Par. [0039]-[0045]) teaches a step of plasma etching 132 wherein etching the dummy gate stack 112 comprises adjusting an RF power and a bias voltage in the plasma etch reactor to generate a straight profile (see, e.g., Figs. 13A-B). Therefore, Wand in view of Chen teaches that etching the sacrificial gate electrode layer comprises adjusting a plasma power level and/or a bias power level to generate a straight profile.
Regarding Claim 12, Wang (see, e.g., Figs. 22A-G and Par. [0085]-[0092]) teaches that the first replacement gate structure (e.g., one of PMOS1, PMOS2, and NMOS1) comprises:
- a gate dielectric layer (e.g., gate dielectric layer 82)
- a work function metal layer (e.g., WF layer 84 and/or 85) formed on the gate dielectric layer
- a top conductive layer (e.g., contact metal layer 87) formed on the work function metal layer.
Regarding Claim 13, Wang (see, e.g., Figs. 22A-G and Par. [0085]-[0092]) teaches that the second replacement gate structure (e.g., NMOS2) comprises:
- a gate dielectric layer (e.g., gate dielectric layer 82)
- a work function metal layer (e.g., WF layer 85) formed on the gate dielectric layer
- a conductive filling (e.g., conductive glue/barrier layer 86) layer formed on the work function metal layer
- a top conductive layer (e.g., contact metal layer 87) formed on the work function metal layer and conductive filling layer.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US2021/0343851).
Regarding Claim 21, Wang (see, e.g., Figs. 1-19) shows most aspects of the instant invention, including a method, comprising:
- forming a semiconductor device (see, e.g., Figs. 19) comprising:
a first semiconductor fin (e.g., fin structure 20)
a first gate structure formed over the semiconductor fin, wherein the first gate structure comprises:
first pair of sidewall spacers (e.g., spacers 45)
a first gate dielectric layer (e.g., gate dielectric layer 82) on the first pair of sidewall spacers and the first semiconductor fin
a first work function metal layer (e.g., WF layer 84 or 85) formed on the first gate dielectric layer
a first top conductive layer (e.g., contact metal layer 87) on the first work function metal layer
wherein a top surface of the first top conductive layer (e.g., 87) is lower than the first pair of sidewall spacers (e.g., 45).
Furthermore, Wang (see, e.g., Figs. 19B and 22G, and Par. [0092]) discloses that a top surface of contact metal layer 87 can be formed to be substantially coplanar with a top surface of gate dielectric layer 82. Therefore, Wang also shows that a top surface of the top conductive layer (e.g., 87) is level with a top surface of the gate dielectric layer (e.g., 82).
Additionally, Wang (see, e.g., Figs. 22A-G and Par. [0085]-[0092]) teaches that his invention can be readily adapted to the manufacture of metal gate structures for both narrow channel FinFETs (e.g., PMOS1, PMOS2, and NMOS1) and a long channel FinFET (e.g., NMOS2). Also, see comments stated above in Par. 37 with regards to Claim 9, which are considered repeated here.
Therefore, Wang (see, e.g., Fig. 22G and Par. [0085]-[0092]) further teaches:
a second semiconductor fin (e.g., second fin 20 associated with the manufacturing of long channel FinFET)
a second gate structure formed over the second semiconductor fin, wherein the second gate structure comprises:
second pair of sidewall spacers (e.g., second spacers 45 associated with the manufacturing of long channel FinFET)
a second gate dielectric layer on the second pair of sidewall spacers and second semiconductor fin (e.g., second gate dielectric layer 82 associated with the manufacturing of long channel FinFET)
a second work function metal layer on the second gate dielectric layer (e.g., second WF layer 85 associated with the manufacturing of long channel FinFET)
a conductive filling layer on the second work function metal layer (e.g., conductive glue/barrier layer 86 associated with the manufacturing of long channel FinFET)
a second top conductive layer on the second work function metal layer and the conductive filling layer (e.g., second contact metal layer 87 associated with the manufacturing of long channel FinFET).
Regarding Claim 22, Wang (see, e.g., Fig. 22G) teaches that the second work function layer (e.g., 85) has a U-shape cross section, the conductive filling layer (e.g., 86) is inside the U- shape of the second work function layer.
Allowable Subject Matter
Claims 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14 and 27-28 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 02/10/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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