DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The rejections of claims 13-15 under 35 USC 112(b) have been overcome by amendment and the rejections are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sircar (WO 2021/1154641, IDS 05/09/2023) in view of DeVilliers (US 2018/0068861) and Bangar (US 2017/0097576).
Regarding Claims 1 and 2, Sircar discloses localized stresses can be modulated in a film deposited on a bowed semiconductor substrate by selectively and locally curing the film by ultraviolet radiation (abstract). Sircar discloses a method comprising receiving a wafer having a working surface (Fig. 1A, paragraph [0026]) for one or more devices to be fabricated thereon, and a backside surface (Fig. 1B) opposite to the working surface (step 210, Fig. 2A, paragraph [0030]). Sircar discloses receiving a stress map of a semiconductor indicating levels of asymmetric bowing in one or more areas of the substrate (step 260, Fig. 2B). Sircar discloses forming UV-curable film 310 deposited on the front side or backside of the bowed substrate, wherein selectively UV-curing the film mitigates the substrate bowing (paragraph [0036-0040]). By selectively exposing certain regions of the UV-curable film to UV light of appropriate wavelengths and locally modulating stress on the UV-curable film, local stresses on the bowed semiconductor can be tuned to achieve local warpage topography (paragraph [0028]). The film 310 is exposed to a pattern of UV light to undergo significant changes in stress value after UV treatment (paragraph [0040], Fig. 3B).
Sircar further discloses that a second pre-patterned mask may be used to selectively cure one or more second regions of the UV-curable film (paragraph [0050]). Application of the second pre-patterned mask allows varying degrees of localized stress modulation for different regions across the UV-curable film, and selectively curing the one or more second regions occurs under different conditions than selectively curing the one or more first regions (paragraph [0050]).
Sircar is silent to a applying a second stress-modification film and exposing the second stress-modification film to a second wavelength of patterned light.
However, DeVilliers teaches forming a photoresist on the backside surface of a substrate opposite the working surface (paragraph [0033] and [0074]). The method involves location-specific tuning of internal stresses at specific locations where the intensities of change are independent of other locations to achieve a substrate with a modified bow (paragraph [0030]). The photoresist is exposed to a pattern of radiation to form a pattern (paragraph [0074]). A subsequent developing and etching process into the substrate modifies the bowing of the substrate (paragraph [0075]). Furthermore, deVilliers discloses that a localized heating or exposure of a film resulting in crosslinking at specific locations causes internal stresses resulting in bow modification without the use of a development and etching step (paragraph [0064]). deVilliers also discloses that one or more films can be deposited on the backside surface of the substrate (paragraph [0073]). Using a direct-write exposure tool or other localized area-specific heating mechanism, the plastic film can be cross-linked at specific locations (regions) where an exposure tool has caused cross-linking to occur (paragraph [0064]). This localized heating or exposure creates internal stresses at those specific locations, which stresses in turn cause bow modification to thereby correct wafer overlay (paragraph [0064]). Since the localized heating or exposure of a film does not need a development or etching step, the film will remain planar without any material removed from development or etching steps.
Sircar discloses that the backside UV-curable film may be subject to a second pattern with a different wavelength and DeVilliers discloses a wafer bow correction step that may use one or more applied to the backside surface that are subject to patterning using a direct write exposure tool.
Sircar and DeVilliers do not show a specific example of a method using a second film deposited on the backside surface to mitigate wafer bowing. Sircar and DeVilliers do not show using different wavelengths of light on different films for the tuning. However, Bangar teaches correcting overlay errors, which are caused by stress non-uniformities [0026], such as bowing [0028] by treating them with different wavelengths of light [0029, 0049].
Therefore, it would have been obvious at the time the invention was made to have used multiple films to control the stress, as suggested by DeVilliers and Bangar and to have tuned the stresses using different wavelengths as suggested by Bangar with a reasonable expectation of success as alternate suitable methods of controlling the bowing of substrates.
Regarding Claim 3, the discussion of Claim 1 is relied upon as above. Sircar further discloses receiving a stress map of a semiconductor indicating levels of asymmetric bowing in one or more areas of the substrate (step 260, Fig. 2B). Sircar discloses as layers of films are stacked on top of each other during fabrication, more stress is introduced to the semiconductor wafer which can cause bowing (paragraph [0021]).
Sircar is silent to additional times where the bow measurement of the wafer may be determined for modification.
However, DeVilliers discloses that internal stress modification can include increasing or relaxing internal stresses on the working surface or on the backside surface of the substrate; the action of physically modifying internal stresses on the substrate can occur multiple times during fabrication of an integrated circuit on the working surface of the substrate (paragraph [0064]). For example, as substrates become bowed to a point at which overlay error is outside of tolerance, the affected substrate can be ported to system 100 and then overlay correction techniques herein can be executed (paragraph [0064]). Such internal stress tuning can include using one or more treatment processes; for example, processing includes location-specific particle implantation, location-specific etching, location-specific cross-linking, location-specific temperature differential curing, location-specific differential deposition, and so forth (paragraph [0064]). For example, a particular plastic material can be deposited, coated, or otherwise applied to the backside surface (paragraph [0064]).
Thus, DeVilliers discloses that over the course of the device fabrication process with layers being applied to either side of the semiconductor substrate, the substrate bowing and overlay error is measured to determine if the overlay error it outside of the tolerances; if the overlay errors are outside the tolerances, the semiconductor substrate would then undergo further internal stress tuning and modification to the backside layers. Additionally, the tuning process may further include material being deposited, coated, or otherwise applied to the backside surface.
Sircar and DeVilliers do not show a specific example of a method measuring the wafer to identify bow measurement of the wafer is performed subsequent to forming a first-stress modification film. However, it is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious to one of ordinary skill in the art to obtain a method wherein the bow measurement is measured subsequent to applying the stress-modification film and at any other step of the device fabrication process through routine experimentation since DeVilliers discusses the action of modifying internal stresses on the substrate can occur multiple times during device fabrication particularly if the overlay error is outside the designated tolerances.
Regarding Claim 4, the discussion of Claim 1 is relied upon as above. Sircar is silent to forming a protective layer on a working surface of the substrate.
However, DeVilliers further discloses methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers using location-specific tuning of stress (abstract). Furthermore, deVilliers discloses that a localized heating or exposure of a film resulting in crosslinking at specific locations causes internal stresses resulting in bow modification without the use of a development and etching step (paragraph [0064]). Using a direct-write exposure tool or other localized area-specific heating mechanism, the plastic film can be cross-linked at specific locations (regions) where an exposure tool has caused cross-linking to occur (paragraph [0064]). This localized heating or exposure creates internal stresses at those specific locations, which stresses in turn cause bow modification to thereby correct wafer overlay (paragraph [0064]). DeVilliers discloses for embodiments that flip a substrate so that the working surface is facing downward and held by a conventional substrate holder, a protection film may be added to the working surface to protect the working surface (paragraph [0058]).
Sircar and DeVilliers disclose similar methods of patterning the backside layer applied onto a semiconductor substrate for the purpose of applying stresses to modify the substrate bowing. It would have been obvious for one of ordinary skill in the art to have modified the working surface of Sircar with the protective film of DeVilliers. One of ordinary skill would have been motivated to make this modification to protect the working surface as suggested by DeVilliers.
Regarding Claims 5-7, the discussion of Claim 4 is relied upon as above.
Sircar further discloses receiving a stress map of a semiconductor indicating levels of asymmetric bowing in one or more areas of the substrate (step 260, Fig. 2B). Sircar discloses as layers of films are stacked on top of each other during fabrication, more stress is introduced to the semiconductor wafer which can cause bowing (paragraph [0021]).
Sircar is silent to additional instances where the bow measurement of the wafer may be determined for modification.
DeVilliers further discloses that internal stress modification can include increasing or relaxing internal stresses on the working surface or on the backside surface of the substrate; the action of physically modifying internal stresses on the substrate can occur multiple times during fabrication of an integrated circuit on the working surface of the substrate (paragraph [0064]). For example, as substrates become bowed to a point at which overlay error is outside of tolerance, the affected substrate can be ported to system 100 and then overlay correction techniques herein can be executed (paragraph [0064]). Such internal stress tuning can include using one or more treatment processes; for example processing includes location-specific particle implantation, location-specific etching, location-specific cross-linking, location-specific temperature differential curing, location-specific differential deposition, and so forth (paragraph [0064]). For example, a particular plastic material can be deposited, coated, or otherwise applied to the backside surface (paragraph [0064]).
DeVilliers further discloses that during backside processing, the working surface is typically clamped or chucked to substrate holders (paragraph [0031]). Additionally, in Fig. 14 the working surface of the semiconductor device is in contact with chuck pins 181; the backside surface is facing upward and may exposed to the stress-modification film (paragraph [0075]) (Claim 7).
Thus, DeVilliers discloses that over the course of the device fabrication process with layers being applied to either side of the semiconductor substrate, the substrate bowing and overlay error is measured to determine if the overlay error it outside of the tolerances; if the overlay errors are outside the tolerances, the semiconductor substrate would then undergo further internal stress tuning and modification to the backside layers. Additionally, the tuning process may further include material being deposited, coated, or otherwise applied to the backside surface.
Sircar and DeVilliers do not show a specific example of a method measuring the wafer to identify bow measurement of the wafer is performed before or after forming a protection layer. However, it is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious to one of ordinary skill in the art to obtain a method wherein the bow measurement is measured subsequent to or after applying the protection layer and at any other step of the device fabrication process through routine experimentation since DeVilliers discusses the action of modifying internal stresses on the substrate can occur multiple times during device fabrication particularly if the overlay error is outside the designated tolerances.
Regarding Claim 8, the discussion of Claim 1 is relied upon as above. Sircar further discloses in some implementations, the semiconductor substrate includes a patterned 3D-NAND structure and one or more etched trenches in the substrate; and the semiconductor substrate may be bowed (paragraph [0031]).
Regarding Claim 9, the discussion of Claim 8 is relied upon as above. Sircar is silent to removing the first-stress modification film after the lithographic patterning processes are executed.
However, DeVilliers further discloses methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers using location-specific tuning of stress (abstract). Furthermore, deVilliers discloses that a localized heating or exposure of a film resulting in crosslinking at specific locations causes internal stresses resulting in bow modification without the use of a development and etching step (paragraph [0064]). Using a direct-write exposure tool or other localized area-specific heating mechanism, the plastic film can be cross-linked at specific locations (regions) where an exposure tool has caused cross-linking to occur (paragraph [0064]). This localized heating or exposure creates internal stresses at those specific locations, which stresses in turn cause bow modification to thereby correct wafer overlay (paragraph [0064]). After the relief pattern is utilized, it may be stripped, ashed, or burned off using a stripping module after an etching operation (paragraph [0057]).
Sircar and DeVilliers do not show a specific example of a method removing the stress-modification film after the lithographic patterning processes are executed. However, it is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious to one of ordinary skill in the art to have removed the stress-modification film after etching using an ashing, burning, or stripping method through routine experimentation.
Regarding Claim 10, Sircar further discloses in some embodiments the pedestal 508 may include wafer holders to hold a wafer by the edges and a bottom showerhead for delivering gases to the backside of a wafer (paragraph [0065]).
Regarding Claim 12, the discussion of Claim 11 is relied upon as above. Sircar further discloses receiving a stress map of a semiconductor indicating levels of asymmetric bowing in one or more areas of the substrate (step 260, Fig. 2B). Sircar discloses as layers of films are stacked on top of each other during fabrication, more stress is introduced to the semiconductor wafer which can cause bowing (paragraph [0021]).
Sircar is silent to additional times where the bow measurement of the wafer may be determined for modification.
However, DeVilliers discloses that internal stress modification can include increasing or relaxing internal stresses on the working surface or on the backside surface of the substrate; the action of physically modifying internal stresses on the substrate can occur multiple times during fabrication of an integrated circuit on the working surface of the substrate (paragraph [0064]). For example, as substrates become bowed to a point at which overlay error is outside of tolerance, the affected substrate can be ported to system 100 and then overlay correction techniques herein can be executed (paragraph [0064]). Such internal stress tuning can include using one or more treatment processes; for example processing includes location-specific particle implantation, location-specific etching, location-specific cross-linking, location-specific temperature differential curing, location-specific differential deposition, and so forth (paragraph [0064]). For example, a particular plastic material can be deposited, coated, or otherwise applied to the backside surface (paragraph [0064]).
Thus, DeVilliers discloses that over the course of the device fabrication process with layers being applied to either side of the semiconductor substrate, the substrate bowing and overlay error is measured to determine if the overlay error it outside of the tolerances; if the overlay errors are outside the tolerances, the semiconductor substrate would then undergo further internal stress tuning and modification to the backside layers. Additionally, the tuning process may further include material being deposited, coated, or otherwise applied to the backside surface.
Sircar and DeVilliers do not show a specific example of a method measuring the wafer to identify bow measurement of the wafer is performed subsequent to forming a second stress-modification film. However, it is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious to one of ordinary skill in the art to obtain a method wherein the bow measurement is measured subsequent to applying the stress-modification film and at any other step of the device fabrication process through routine experimentation since DeVilliers discusses the action of modifying internal stresses on the substrate can occur multiple times during device fabrication particularly if the overlay error is outside the designated tolerances.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sircar (WO 2021/1154641, IDS 05/09/2023) in view of DeVilliers (US 2018/0068861) and Bangar (US 2017/0097576), as applied to Claim 1 in view of Jain (US 2021/0320036).
Regarding Claim 13, the discussion of Claim 1 is relied upon as above. Sircar further discloses in some examples, the UV-curable film includes silicon nitride (paragraph [0037]).
Sircar is silent to forming a stress film on the backside surface of the wafer where the first stress modification film is on the stress film.
However, Jain teaches a first stress layer disposed on and in contact with a backside of the semiconductor wafer and a second stress layer on and in contact with the first stress layer (abstract). The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer, and the second stress layer exerts a stress that is opposite nature to the first stress (paragraph [0003]). In one embodiment the first film comprises a high tensile stress material (paragraph [0034]). The first film is applied to pull the outer edges of the wafer down and bows the center point of the wafer above the reference plane line (paragraph [0035] Fig 3, 3A). A second film is also applied having an opposing stress such as silicon nitride (paragraph [0037]).
Sircar discloses a UV-curable film that modifies wafer warpage and Jain discloses applying stress layers to modify the wafer warpage; the two methods rely on applying layers to the backside of the semiconductor wafer and are complementary to one another to achieve the same goal. It is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious for one of ordinary skill in the art to have modified the wafer correcting method of Sircar to add the complementary first stress or first and second stress layer of Jain through routine experimentation. One of ordinary skill would have further been motivated to make this modification to pull the outer edges of the wafer down below the center point of the wafer above the reference plane line as suggested by Jain.
Regarding Claims 14 and 15, the discussion of Claim 13 is relied upon as above. Jain further discloses tuning the stress of the wafer such that the wafer stress and warpage is able to be kept in neutral through the fabrication by thinning and/or removing portions of the backside stress layers (paragraph [0031]). To do this, Jain relies on a wafer stress manager that performs operations to determine the amount to reduce the thickness of one or more backside stress films (paragraph [0045]). One advantage of the present invention is that one or more of the backside stress films can be gradually etched away or thinned during fabrication to maintain a desired neutral stress without affecting the front side processing (paragraph [0057]). The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer, and the second stress layer exerts a stress that is opposite nature to the first stress (paragraph [0003]) (Claim 15).
Jain is not explicit to a particular embodiment comprising removing a portion of the stress film and replacing the removed portion with a stress layer. However, Jain does disclose the first and second stress films may be etched or thinned during fabrication to maintain a desired neutral stress. It is prima facie obvious to combine two methods each of which is taught by the prior art to be useful for the same purpose, in order to form a third method to be used for the very same purpose…[T]he idea of combining them flows logically from their having been individually taught in the prior art. In re Kerkhoven, 205 USPQ 1069 1072. In the instant case, it would have been obvious for one of ordinary skill in the art to have modified the wafer correcting method of Sircar and Jain disclosed above by thinning or etching portions of the stress film to keep a neutral stress on the substrate through routine experimentation. Furthermore, one of ordinary skill would have been motivated to make this modification to keep the wafer warpage as close to neutral as suggested by Jain.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7, 10-13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 10, 11, and 20 of copending Application No. 17/703,072 in view of deVilliers (US 2018/0068861) and Weber (US 2005/0147918).
Regarding Claims 1 and 13, Claims 1, 10, 11, and 20 of the copending application cover substantially similar subject matter except Claim 1, 10, 11, and 20 of the copending application further limit wherein the bow modification stress film remains planar during and after the exposure, without forming a relied structure or undergoing a development step, the bow modification stress film configured to release the stress modifying agent along the exposed pattern, or where the material of the bow modification stress film is at least one selected from the group consisting of epoxy acrylate and epoxy Novolak. The films are exposed to different wavelengths.
However, deVilliers discloses that a localized heating or exposure of a film resulting in crosslinking at specific locations causes internal stresses resulting in bow modification without the use of a development and etching step (paragraph [0064]).
Weber discloses photoresist compositions comprising an epoxide-substituted resin, a photoacid generator and a solvent (abstract). Further, Weber discloses the inventive SU-8-based compositions discloses have shrinkage-induced stress when the material undergoes polymerization and is manifested in substrate bowing, where the shrinkage of the coating induces bending of the substrate (paragraph [0013]). The resin component (I) has at least two or more epoxy groups in one molecule including the general group comprising epoxy-novolac resins (paragraph [0029]). Synthesis Example 1 and the structure of Formula 1A are shown below (paragraph [0065-0068]). Weber discloses the photoresist formulations (paragraph [0080], Table 1 page 13). The patterning process involves applying the photoresist formulation to a substrate and drying to form a film, exposing the photoresist to ultraviolet light using a negative photomask, applying a post-exposure bake for 10 minutes at 95 oC, developing in aqueous tetramethylammonium hydroxide, and further heating for 5 minutes at 100 oC to harden the resist (paragraph [0080]).
deVilliers discloses a method comprising a patternable photoresist applied to the backside of a substrate that is able to induce stress on a substrate to warp or bend the substrate, and Weber discloses patternable epoxy-novolac-based photoresists capable of shrinkage-induced stress after polymerization of the material. Therefore, it would have been obvious for one of ordinary skill in the art to modify the copending application Claim 1 to locally expose the film resulting in crosslinking at specific locations to modify the substrate bow without development or etching step of deVilliers through routine experimentation. One of ordinary skill would reasonably expect substituting one method to tune stress for another to result in a similar bow modification method. Furthermore, it would have been obvious for one of ordinary skill in the art to have modified the copending application Claim 1 with the epoxy-novolac photoresist polymers disclosed in Weber. One of ordinary skill would reasonably expect this modification would reliably form a photoresist layer capable of inducing a warping or bowing stress to a substrate after patterning exposure.
Regarding Claims 2-7 and 12, the discussion of Claim 1 is relied upon as above. DeVilliers further discloses for embodiments that flip a substrate so that the working surface is facing downward and held by a conventional substrate holder, a protection film may be added to the working surface to protect the working surface (paragraph [0058]). DeVilliers discloses that internal stress modification can include increasing or relaxing internal stresses on the working surface or on the backside surface of the substrate; the action of physically modifying internal stresses on the substrate can occur multiple times during fabrication of an integrated circuit on the working surface of the substrate (paragraph [0064]). For example, as substrates become bowed to a point at which overlay error is outside of tolerance, the affected substrate can be ported to system 100 and then overlay correction techniques herein can be executed (paragraph [0064]). Such internal stress tuning can include using one or more treatment processes; for example processing includes location-specific particle implantation, location-specific etching, location-specific cross-linking, location-specific temperature differential curing, location-specific differential deposition, and so forth (paragraph [0064]). For example, a particular plastic material can be deposited, coated, or otherwise applied to the backside surface (paragraph [0064]). deVilliers also discloses that one or more films can be deposited on the backside surface of the substrate (paragraph [0073]) (Claim 11).
Thus, DeVilliers discloses that over the course of the device fabrication process with layers being applied to either side of the semiconductor substrate, the substrate bowing and overlay error is measured to determine if the overlay error it outside of the tolerances (Claims 2, 3, 5, 6, 12); if the overlay errors are outside the tolerances, the semiconductor substrate would then undergo further internal stress tuning and modification to the backside layers. Additionally, the tuning process may further include material being deposited, coated, or otherwise applied to the backside surface.
Regarding Claims 11 and 12, the discussion of Claim 1 is relied upon as above. deVilliers also discloses that one or more films can be deposited on the backside surface of the substrate (paragraph [0073]).
This is a provisional nonstatutory double patenting rejection.
Claims 8-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 10, 11, and 20 of copending Application No. 17/703,072 in view of deVilliers (US 2018/0068861) and Weber (US 2005/0147918) applied to Claim 1 further in view of Sircar (WO 2021/1154641, IDS 05/09/2023).
Regarding Claims 8-10, the copending application 17/703,072 is silent to measuring the wafer to identify bow measurement, executing one or more lithographic patterning processes on the working surfaces and removing the stress-modification film.
However, Sircar discloses localized stresses can be modulated in a film deposited on a bowed semiconductor substrate by selectively and locally curing the film by ultraviolet radiation (abstract). Sircar discloses a method comprising receiving a wafer having a working surface (Fig. 1A, paragraph [0026]) for one or more devices to be fabricated thereon, and a backside surface (Fig. 1B) opposite to the working surface (step 210, Fig. 2A, paragraph [0030]). Sircar discloses receiving a stress map of a semiconductor indicating levels of asymmetric bowing in one or more areas of the substrate (step 260, Fig. 2B). Sircar discloses forming UV-curable film 310 deposited on the front side or backside of the bowed substrate, wherein selectively UV-curing the film mitigates the substrate bowing (paragraph [0036-0040]). By selectively exposing certain regions of the UV-curable film to UV light of appropriate wavelengths and locally modulating stress on the UV-curable film, local stresses on the bowed semiconductor can be tuned to achieve local warpage topography (paragraph [0028]). The film 310 is exposed to a pattern of UV light to undergo significant changes in stress value after UV treatment (paragraph [0040], Fig. 3B). Sircar further discloses in some implementations, the semiconductor substrate includes a patterned 3D-NAND structure and one or more etched trenches in the substrate; and the semiconductor substrate may be bowed (paragraph [0031]) (Claim 8). Sircar further discloses in some embodiments the pedestal 508 may include wafer holders to hold a wafer by the edges and a bottom showerhead for delivering gases to the backside of a wafer (paragraph [0065]) (Claim 10).
DeVilliers further discloses after the relief pattern is utilized, it may be stripped, ashed, or burned off using a stripping module after an etching operation (paragraph [0057]) (Claim 9).
Sircar discloses methods relating to modifying wafer bowing. It would have been obvious for one of ordinary skill in the art to have modified the copending application with the teachings of Sircar since both the copending application and Sircar relate to methods of reducing wafer internal stresses through routine experimentation. One of ordinary skill would reasonably expect these modifications to result in the wafer modification methos as instant claimed.
This is a provisional nonstatutory double patenting rejection.
Response to Arguments
Applicant’s arguments, see pp. 5-7, filed 10/8/25, with respect to the rejection(s) of claim(s) 1-11 and 13-15 under 35 USC 102 and 103 have been fully considered and are persuasive in view of the amendments to claim 1. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly cited Bangar, which teaches treating different films at different wavelengths to correct errors such as bowing.
It is noted that Applicant does not make arguments as to the ODP rejections. Claim 20 of the ‘072 application claims treating the films with different wavelengths of light. Therefore, the ODP rejections are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cutler (US 2022/0336226, the publication of ODP reference 17/703072) is cited of interest as having a teaching of treating stress modification films with different wavelengths of light.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B CLEVELAND whose telephone number is (571)272-1418. The examiner can normally be reached Monday-Friday; 9:00 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexa Neckel can be reached at 571-272-2450. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL B. CLEVELAND
Supervisory Patent Examiner
Art Unit 1712
/MICHAEL B CLEVELAND/Supervisory Patent Examiner, Art Unit 1712
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