Prosecution Insights
Last updated: April 19, 2026
Application No. 17/891,348

SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF

Final Rejection §102§103
Filed
Aug 19, 2022
Examiner
HATFIELD, MARSHALL MU-NUO
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
64 granted / 68 resolved
+26.1% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
34 currently pending
Career history
102
Total Applications
across all art units

Statute-Specific Performance

§103
50.6%
+10.6% vs TC avg
§102
33.1%
-6.9% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 68 resolved cases

Office Action

§102 §103
Detailed Action Multiple attempts were made to reach the attorney of record, Paul Bendemire in regards to a proposed examiner’s amendment, but they could not be reached. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, See page 8, paragraphs 2-3 of applicant’s arguments, filed 11/12/2025 with respect to the rejection(s) of claims 6 and 23 under 35 U.S.C. 112(b) has been fully considered and are persuasive. The corresponding rejections have been withdrawn in view of the amended limitation. Applicant's arguments, See page 9, first paragraph of applicant’s arguments, filed 11/12/2025 with respect to the rejection(s) of claim 1 and dependent claims under 35 U.S.C. 102(a)(1) over Ando(US 20190280107 A1, hereafter Ando) have been fully considered but they do not place the application in the conditions for allowance. The amended limitation, “forming a thinned intermixed layer by partially removing material of the intermixed layer”, is still read upon by the prior art of Ando if instead of strictly defining the intermixed layer as Fig. 4 16, the intermixed layer is defined as both Fig. 4 16 and the remaining portion of Fig. 3 15 as mentioned in Paragraph 0061 of Ando, wherein the remaining portion of Fig. 3 15 that has not reacted is then etched away. In practice, the reaction occurring is the migration of Ge atoms into the nanosheets of Fig. 3 10a, wherein a particular threshold of Ge content of Fig. 3 15 that remains is considered unreacted while the remainder is considered reacted. In this way, the limitation of forming a thinned intermixed layer is satisfied. Furthermore, the amended limitation of claim 10, “prior to forming the thinned intermixed layer” does not place the application in the conditions for allowance as under this new interpretation, the prior art of Glass(US 20140175543 A1, hereafter Glass) discloses a capping layer prior to an anneal(See paragraphs 0048-0049 of Glass) in order to preserve a shape and compositional integrity of the cladding layer. New rejections are below. Applicant’s arguments, see Page 10, paragraphs 1-2, filed 11/12/2025, with respect to the rejection(s) of claims 21 and dependent claims under 35 U.S.C. 102(a)(1) over Ando have been fully considered and are persuasive. The rejection of the claims has been withdrawn. The amendment of “forming a second intermixed layer by increasing an atomic percentage of the material in the exposed portions of the well portion via the cladding layer” overcomes the prior art of Ando. Applicant’s arguments, see Page 10, Paragraphs 3-4 of applicant’s arguments, filed 11/12/2025, with respect to the rejection(s) of claim 26 and dependent claims under 35 U.S.C. 102(a)(1) in view of Ando have been fully considered and are persuasive. The rejection of the claims has been withdrawn. The amendment of “forming a capping on the cladding layer, a first concentration of the germanium of the cladding layer adjacent a first interface between the capping layer and the cladding layer being less than a second concentration of the germanium adjacent a second interface between the cladding layer and the first semiconductor layer” overcomes the prior art rejection in view of Ando. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando. Regarding Claim 1, Ando discloses: A method for forming a semiconductor structure(Figs. 1-7) comprising: Forming a fin structure(Fig. 1A [11a/11b]) having first semiconductor layers(Fig. 1A [10a]) and second semiconductor layers(Fig. 1A [10b]) alternatingly stacked thereover; Forming a sacrificial gate structure(See paragraph 0028, “sacrificial gate structure”) over a portion of the fin structure(Fig. 1A [11a/11b]); Removing portions of the sacrificial gate structure(See paragraph 0028, “removal of a sacrificial gate structure”) to expose the first(Fig. 1A [10a]) and second(Fig. 1A [10b]) semiconductor layers; Removing portions of the second semiconductor layers(Fig. 1A [10b]) to expose portions of each of the first semiconductor layers(Fig. 2 [10a]); Surrounding the exposed portions of each of the first semiconductor layers(Fig. 3 [10a]) with a cladding layer(Fig. 3 [15]), wherein the cladding layer(Fig. 3 [15]) is formed of a material chemically different(Fig. 3 [10a] is Si, See paragraph 0032, while Fig. 3 [15] is SiGe, See paragraph 0025) from the first semiconductor layers(Fig. 3 [10a]), and the cladding layer(Fig. 3 [15]) has a first atomic percentage of germanium(greater than 40 wt%, See paragraph 0055); Performing a thermal treatment(See paragraph 0060) so that germanium atoms of the cladding layer(Fig. 3 [15]) are diffused into and reacted with the first semiconductor layer(Fig. 3 [10a]) to form an intermixed layer(Fig. 4 [16]); Forming a thinned intermixed layer(See paragraph 0061) by partially removing material of the intermixed layer(Fig. 4 [16]); and Forming a gate electrode layer(Fig. 7 [19a]) to surround each of the thinned intermixed layer(See paragraph 0061). Ando does not explicitly teach or disclose that the resulting intermixed layer has a second atomic percentage of germanium that is less than the first atomic percentage of germanium. However, this is an inevitable result of the process disclaimed by Ando for the following reason. The anneal reaction disclosed by Ando can be represented by the equation below: Sia + Si0.6Ge0.4 ⇌ SiyGez wherein the right side of the equation represents the silicon channel layer(Fig. 3 [10a], represented by Sia) and the cladding layer(Fig. 3 [15], represented by Si0.6Ge0.4), and the left side of the equation represents the resulting intermixed layer(Fig. 4 [16], represented by SiyGez). When the annealing process occurs, the germanium atoms can diffuse from the cladding layer into the intermixed layer, but in a case where, for example, the intermixed layer were for whatever reason having a higher Ge content than the cladding layer, the diffusion would happen in the opposite direction. The ratio of Ge on the left side must be lower than 0.4 due to the fact that a set amount of silicon is essentially being added to a set amount of SiGe to create the resulting intermixed layer. For this reason, it would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations, due to the limitation being a necessary reality as a result of the disclosed chemical process of Ando. Adding this limitation would have generated a predictable result due to the fact that the expected result of this annealing process in view of Ando is known due to knowledge of chemical equilibrium in the art. Regarding Claim 2, Ando further discloses: The first semiconductor layer(Fig. 3 [10a]) comprises silicon(Fig. 3 [10a] is Si, See paragraph 0032) and the cladding layer(Fig. 3 [15]) comprises silicon germanium(Fig. 3 [15] is SiGe, See paragraph 0025). Regarding Claim 3, Ando further discloses: The first atomic percentage of germanium is in a range of about 20 at. % to about 100 at. %(greater than 40 wt. %, that equates to greater than 20.44 at. %, based on molar masses of silicon and germanium respectively). Ando does not explicitly teach or disclose the second atomic percentage of germanium is in a range of about 5 atomic percent to about 50 atomic percent. However, given that it was established in the rejection of claim 1 that the resulting percentage of germanium in the intermixed layers is necessarily lower than the atomic percentage of germanium in the cladding layer, this provides a range by which one of ordinary skill in the art could have achieved the claimed range via routine experimentation, specifically by changing the duration or the temperature of Ando’s anneal process. Therefore, it would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce ando’s device in such a way as to satisfy the claimed range. Producing Ando’s device in this way would have generated a predictable result in the creation of the intermixed layer with a lower germanium concentration than the cladding layer it was generated from. Regarding Claim 7, Ando further discloses: The cladding layer has a first thickness(0.5 to 3 nm, See paragraph 0059) and the first semiconductor layer has a second thickness(5 to 20 nm, See paragraph 0035), and a ratio of the first thickness to the second thickness is in a range of about 1:5 to about 1:30. Taking a lower bound of each thickness given by Ando provides a range of 1:10 to about 1:7, both of which lie within the claimed range. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-5, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ando in view of Glass et al.(US 20140175543 A1, hereafter Glass). Regarding Claim 4, Ando discloses a cladding layer(Fig. 3 [15]). Ando does not teach or disclose the cladding layer as being a pure germanium layer. In the same field of endeavor, Glass discloses a cladding layer(Fig. 3d [314]) comprising pure Ge(See paragraph 0047). It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the method as disclosed by Ando along the lines of Glass. One might have been motivated to use a pure Ge layer as to drive a larger amount of Ge into the channel layers of Ando, or to drive the same amount of Ge into the channel layers in a shorter anneal time. In addition, one might have been motivated to use pure Ge as to better facilitate the selective removal of the cladding layer, which Ando discloses(See paragraph 0023, “removing the sacrificial germanium containing semiconductor materials”). Performing this modification would have generated a predictable result in the creation of Ando’s process with a Ge layer instead of an SiGe cladding layer. Regarding Claim 5, Ando discloses an intermixed layer(Fig. 4 [16]). Ando does not teach or disclose the germanium atoms are evenly distributed throughout the intermixed layer. In the same field of endeavor, Glass discloses the germanium atoms as evenly distributed throughout the intermixed layer(See Fig. 8 [T3]). It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the process as disclosed by Ando along the lines of Glass. One might have been motivated to make the composition profile of Ge in the intermixed layer evenly distributed as to avoid unwanted changes in the work function, as an uneven Ge composition with respect to position would cause unwanted changes in the work function at points near the surface of the intermixed layer versus deeper within it. Performing this modification would have generated a predictable result in the creation of a method for creating Ando’s device with an even distribution of the germanium atoms within the intermixed layer. Regarding Claim 8, Ando discloses a method in accordance with most of the limitations of claim 1(See above rejection). Ando does not teach or disclose prior to the thermal treatment, forming a capping layer on the cladding layer. In the same field of endeavor, Glass discloses a formation of a capping layer(Fig. 3e [316]) prior to an annealing treatment(See claim 1) on the cladding layer(Fig. 3e [314]). Glass discloses that the capping layer preserves the shape and compositional integrity of the cladding layer prior to and during the anneal, in which without the capping layer the Ge may flow and result in an Inconsistent concentrations of Ge in the channel after annealing(See paragraph 0048). It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the method disclosed by Ando along the lines of Glass. One might have been motivated to add a capping layer as to preserve the shape and the diffusion of the Ge during the annealing process. Performing this modification would have generated a predictable result in the creation of Ando’s process with an additional capping layer on the cladding layer. Regarding Claim 9, Claim 8 is rejected under 35 U.S.C. 103(see above rejection). Ando does not teach or disclose a capping layer comprising an oxide. In the same field of endeavor, Glass discloses a cladding layer(Fig. 3e [316]) comprising an oxide(See paragraph 0051). It would have been obvious to one of ordinary skill in the art to further modify the method disclosed by Ando along the lines of Glass. One might have been motivated to comprise the capping layer out of an oxide to facilitate its removal after the anneal(See paragraph 0051 of Glass). Performing this modification would have generated a predictable result in the creation of Ando’s process with an additional capping layer on the cladding layer. Regarding Claim 10, Ando discloses performing a trimming process to remove a portion of the intermixed layer(See paragraph 0072). Ando does not teach or disclose prior to forming the thinned intermixed layer, removing the capping layer. In the same field of endeavor, Glass discloses the removal of the capping layer(See paragraph 0051) prior to forming an intermixed layer(See Fig. 3f [304a]). It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the method disclosed by Ando further along the lines of Glass. One might have been motivated to add and remove the capping layer as to maintain the resulting device obtained from Ando’s method while keeping the benefits disclosed by Glass regarding the capping layer. Furthermore, as one of ordinary skill in the art would be applying the teaching of adding and removing the capping layer disclosed by Glass, the most obvious choice would be to use the capping layer in accordance with Glass’s recommendation, and to not retain the capping layer after the capping layer serves its function. Performing this modification would have generated a predictable result in the device produced by Ando’s method while retaining the benefits of a capping layer as disclosed by Glass. Allowable Subject Matter Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 6, the prior art of Ando discloses forming a first capping layer(Fig. 6 [17a]). The prior art of record does not appear to teach or disclose forming a capping layer on the cladding layer, wherein a first concentration of germanium atoms at and/or near an interface between the capping layer and the cladding layer is less than a second concentration of the germanium atoms at and/or near an interface between the cladding layer and the first semiconductor layers. Claims 21-30 are in the conditions for allowance. Regarding Claim 21, the closest prior art of Ando discloses A method for forming a semiconductor structure(Figs. 1-7) comprising: Forming a stack(Fig. 1A [11a/11b]) comprising alternating first semiconductor layers(Fig. 1A [10a]) and second semiconductor layers(Fig. 1A [10b]); Removing portions of the second semiconductor layers(Fig. 1A [10b]) to expose portions of each of the first semiconductor layers(Fig. 2 [10a]); Forming a cladding layer(Fig. 3 [15]) on the exposed portions of the first semiconductor layers(Fig. 3 [10a]), the cladding layer(Fig. 3 [15]) including a material chemically different(Fig. 3 [10a] is Si, See paragraph 0032, while Fig. 3 [15] is SiGe, See paragraph 0025) from the first semiconductor layers(Fig. 3 [10a]), Forming an intermixed layer(Fig. 4 [16]) by increasing(see paragraph 0023, “diffuse the work germanium containing work function adjusting elements into the nanosheets”) atomic percentage of the material in the exposed portions via the cladding layer(Fig. 3 [15]), the intermixed layer(Fig. 4 [16]) having a second atomic percentage, Forming a gate electrode layer(Fig. 7 [19a]) on the intermixed layers(Fig. 7 [16]). Ando does not explicitly teach or disclose that the resulting intermixed layer has a second atomic percentage of germanium that is less than the first atomic percentage of germanium of the cladding layer. However, this is an inevitable result of the process disclaimed by Ando for the following reason. The anneal reaction disclosed by Ando can be represented by the equation below: Sia + Si0.6Ge0.4 ⇌ SiyGez wherein the right side of the equation represents the silicon channel layer(Fig. 3 [10a], represented by Sia) and the cladding layer(Fig. 3 [15], represented by Si0.6Ge0.4), and the left side of the equation represents the resulting intermixed layer(Fig. 4 [16], represented by SiyGez). When the annealing process occurs, the germanium atoms can diffuse from the cladding layer into the intermixed layer, but in a case where, for example, the intermixed layer were for whatever reason having a higher Ge content than the cladding layer, the diffusion would happen in the opposite direction. The ratio of Ge on the left side must be lower than 0.4 due to the fact that a set amount of silicon is essentially being added to a set amount of SiGe to create the resulting intermixed layer. For this reason, it would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations, due to the limitation being a necessary reality as a result of the disclosed chemical process of Ando. Adding this limitation would have generated a predictable result due to the fact that the expected result of this annealing process in view of Ando is known due to knowledge of chemical equilibrium in the art. However, the prior art of record does not appear to teach or disclose the stack overlying a well portion extending above an isolation region or forming a second intermixed layer by increasing an atomic percentage of the material in the exposed portions of the well portion via the cladding layer. Claims 22-25 are also in the conditions for allowance due to their dependence upon claim 21. Regarding Claim 26, the closest prior art of Ando discloses: A method for forming a semiconductor structure(Figs. 1-7) comprising: Forming a first stack(Fig. 1A [11a]) and a second stack(Fig. 1A [11b]), each comprising alternating first semiconductor layers(Fig. 1A [10a]) and second semiconductor layers(Fig. 1A [10b]); Forming a sacrificial gate structure(See paragraph 0028, “sacrificial gate structure”) over respective portions of the first stack(Fig. 1A [11a]) and the second stack(Fig. 1A [11b]); Removing portions of the second semiconductor layers(Fig. 1A [10b]) to expose portions of each of the first semiconductor layers(Fig. 2 [10a]); Forming a cladding layer(Fig. 3 [15]) that surrounds the exposed portions of each of the first semiconductor layers(Fig. 3 [10a]), the cladding layer(Fig. 3 [15]) having a first atomic percentage of germanium different(Fig. 3 [10a] is Si, See paragraph 0032, while Fig. 3 [15] is SiGe, See paragraph 0025) from the first semiconductor layers(Fig. 3 [10a]); Diffusing germanium atoms(See paragraph 0023, “diffuse the work germanium containing work function adjusting elements into the nanosheets”) of the cladding layer(Fig. 3 [15]) into the first semiconductor layers(Fig. 3 [10a]) yielding intermixed layers(Fig. 4 [16]) comprising a second atomic percentage of germanium; Forming a gate electrode layer(Fig. 7 [19a]) that surrounds each of the intermixed layers(Fig. 7 [16]). Ando does not explicitly teach or disclose that the resulting intermixed layer has a second atomic percentage of germanium that is less than the first atomic percentage of germanium. However, this is an inevitable result of the process disclaimed by Ando for the following reason. The anneal reaction disclosed by Ando can be represented by the equation below: Sia + Si0.6Ge0.4 ⇌ SiyGez wherein the right side of the equation represents the silicon channel layer(Fig. 3 [10a], represented by Sia) and the cladding layer(Fig. 3 [15], represented by Si0.6Ge0.4), and the left side of the equation represents the resulting intermixed layer(Fig. 4 [16], represented by SiyGez). When the annealing process occurs, the germanium atoms can diffuse from the cladding layer into the intermixed layer, but in a case where, for example, the intermixed layer were for whatever reason having a higher Ge content than the cladding layer, the diffusion would happen in the opposite direction. The ratio of Ge on the left side must be lower than 0.4 due to the fact that a set amount of silicon is essentially being added to a set amount of SiGe to create the resulting intermixed layer. For this reason, it would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to arrive at the claimed limitations, due to the limitation being a necessary reality as a result of the disclosed chemical process of Ando. Adding this limitation would have generated a predictable result due to the fact that the expected result of this annealing process in view of Ando is known due to knowledge of chemical equilibrium in the art. However, the prior art of record does not appear to teach or disclose forming a capping layer on the cladding layer, wherein a first concentration of germanium atoms adjacent a first interface between the capping layer and the cladding layer being less than a second concentration of the germanium adjacent a second interface between the cladding layer and the first semiconductor layers. Claims 27-30 are also in the conditions for allowance due to their dependence upon claim 26. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Agrawal et al.(US 20230420507 A1) discloses an SiGe cladding to drive Ge inwards. Reboh et al.(US 20190157422 A1) discloses a thermal annealing which changes the thickness of silicon nanowires by driving germanium inwards. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897 /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Aug 19, 2022
Application Filed
Aug 07, 2025
Non-Final Rejection — §102, §103
Nov 12, 2025
Response Filed
Feb 18, 2026
Final Rejection — §102, §103 (current)

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