DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to claim(s) 21, Applicant’s arguments and/or amendments have resolved the typographical issues in these claims. Accordingly, the objection to claim(s) 21 is withdrawn.
RE: the rejection of the claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7, 11, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20210351299A1 (“Huang”) in view of US20170294522A1 (“Pandey”), further in view of US 20170110327 A1 (“Kim”).
RE: Claim 1, Huang discloses A method of forming a semiconductor device structure (100, FIGS. 2-7, 8A, 9-13, and 14A-14C are cross-sectional views of a FinFET device 100 at various stages of fabrication in accordance with some embodiments, [0015]), the method comprising:
forming a plurality of dummy gates (75 including 75A, 75B, 75C, [0032]) over a substrate (50/64);
performing a first etch step (anisotropic etching, [0037], FIG. 7) on the substrate exposed between the dummy gates, comprising:
performing an anisotropic etching process (anisotropic etching, [0037]; recesses 88 are formed in the fins 64 adjacent to the dummy gate structures 75, e.g., between adjacent dummy gate structures 75 and/or next to a dummy gate structure 75. The recesses 88 are formed by, e.g., an anisotropic etching, [0037]).
Huang does not explicitly disclose:
performing an isotropic etching process with an etchant being pushed toward a deeper level of the substrate; and
performing a second etch step on the substrate exposed between the dummy gates, the second etch step comprising an isotropic etching step, wherein:
after the second etch step, a recess defined in the substrate by the first etch step and the second etch step has a first width at a first depth, a second width at a second depth greater than the first depth, and a third width at a third depth greater than the second depth,
the second width is less than the first width and less than the third width, and
the first width, the second width, and the third width are measured in a direction extending from a first dummy gate of the dummy gates to a second dummy gate of the dummy gates.
In the same field of endeavor, Pandey discloses FIGS. 2A-2H depict various illustrative and novel methods of forming source/drain regions on FinFET devices, [0026].
Pandey further discloses:
performing a first etch step (first etching process 120 and second etching process 124, [0030]-[0031], FIGs. 2C-2D) on a substrate (102, 104, [0026]-[0027]) exposed, comprising:
performing an anisotropic etching process (first etching process 120 is an anisotropic etching process, [0030], FIG. 2C);
performing an isotropic etching process toward a deeper level of the substrate (second etching process 124 is an isotropic etching process, [0031], hereafter “first isotropic etching process”; FIG. 2D shows isotropic etching process 124 etching toward a deeper level of the substrate 104/102); and
performing a second etch step (third etching process 136, [0032]-[0033], FIG. 2F) on the substrate exposed, the second etch step comprising an isotropic etching step (136 is an isotropic etching process, [0033], hereafter “second isotropic etching process”), wherein:
after the second etch step, a recess (140; the third final cavity 140 constitutes a unique source/drain cavity for the FinFET device 100, [0033]) defined in the substrate by the first etch step and the second etch step has a first width at a first depth (Annotated FIG. 2F below shows first width at first depth), a second width at a second depth greater than the first depth (Annotated FIG. 2F below shows second width at a second depth greater than the first depth), and a third width at a third depth greater than the second depth (Annotated FIG. 2F below shows a third width at a third depth greater than the second depth),
the second width is less than the first width and less than the third width (Annotated FIG. 2F below shows the second width is less than the first width and less than the third width), and
the first width, the second width, and the third width are measured in a horizontal direction (Annotated FIG. 2F below shows the widths are measured in the horizontal direction).
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(Annotated FIG. 2F of Pandey)
Pandey further discloses FIG. 2H depicts the results of simulations that were run which indicate that formation of the novel final cavity 140 with the stepped profile disclosed herein should increase the performance capabilities of FinFET devices as, [0035].
Pandey further discloses Simulations also predict that the drive current for a FinFET device formed with the unique source/drain cavity 140 depicted herein will be about 2-3 percent greater, [0035].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further perform a first isotropic process and a second isotropic process, thereby forming a recess 88 with a stepped profile as taught by Pandey in order to increase performance and drive current as further taught by Pandey.
In FIG. 7 Huang, the horizontal direction would extend from a first dummy gate 75A and a second dummy gate 75B. Accordingly, each of the first width, second width, and third width would be measured in the horizontal direction extending from a first dummy gate 75A and a second dummy gate 75B.
Further, Huang discloses the substrate 50 may be a silicon wafer, [0016].
Huang further discloses The patterned mask 58 is subsequently used to pattern exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B), [0019], see FIGs. 2-3.
Accordingly, the fins 64 are made of silicon.
Huang further discloses lightly doped drain (LDD) regions 65 are formed in the fins 64, [0033].
Huang further discloses recesses 88 are formed in the fins 64 adjacent to the dummy gate structures 75, e.g., between adjacent dummy gate structures 75 and/or next to a dummy gate structure 75. The recesses 88 are formed by, e.g., an anisotropic etching process using the dummy gate structures 75 and the gate spacers 87 as an etching mask, in some embodiments, although any other suitable etching process may also be used, [0037].
Further, in the same field of endeavor, Kim discloses:
The dry etching may include, for example, anisotropic dry etching and isotropic dry etching, [0098].
Kim further discloses For example, the isotropic dry etching may use the plasma of gas including substance with high reactivity with silicon, such as chlorine (Cl2) gas, gas including hydrogen bromide (HBr) and chlorine (Cl2), gas including sulfur hexafluorine (SF6) and chlorine (Cl2), or gas including at least one of hydrogen bromide (HBr), chlorine (Cl2) or sulfur hexafluorine (SF6), but not limited thereto, [0101].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to, during the first isotropic etching process, use the plasma of gas including substance with high reactivity with silicon to etch the silicon in the fins 64 as taught by Kim in order to ensure silicon is reacted with and therefore removed during etching.
As a result, the plasma of the gas would be pushed toward a deeper level of the substrate 50/64 during the first isotropic etching process.
RE: Claim 2, Huang in view of Pandey, Kim discloses The method of claim 1, further comprising:
forming an epitaxial source/drain region in the recess (As modified, the first etch step and second etch step form a modified recess 88; Huang discloses the source/drain regions 80 are formed in the recesses 88. The source/drain regions 80 are formed by epitaxially growing a material in the recesses 88, [0037]).
RE: Claim 3, Huang in view of Pandey, Kim discloses The method of claim 1, wherein performing the anisotropic etching process in the first etch step comprises using at least one of HBr, Cl2, or Ar (Kim discloses the anisotropic dry etching may use plasma including fluorine (F) and argon (Ar). For the plasma including fluorine (F) and argon (Ar), for example, NF3/Ar, CF4/O2/Ar or CHF3/O2/Ar plasma may be used, [0100].
Accordingly, Kim teaches NF3/Ar is an etching used for anisotropic etching.
Further, there was a need to select an etchant for the anisotropic etching before the effective filing date of the claimed invention.
It would have been obvious to use NF3/Ar as the etchant during the anisotropic etching process as taught by Kim as this would have been obvious to try since NF3/Ar is one solution for the etchant in anisotropic etching and this would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 7, Huang in view of Pandey, Kim discloses The method of claim 1, wherein the etchant used in the isotropic etching process in the first etch step is at least one of H2, CH4, CH2F2, CH3F, CHF3, CF4, SF6, NF3, C4F8, C4F6, Ar, or N2 (Kim discloses the isotropic dry etching may use the plasma of gas including substance with high reactivity with silicon, such as chlorine (Cl2) gas, gas including hydrogen bromide (HBr) and chlorine (Cl2), gas including sulfur hexafluorine (SF6) and chlorine (Cl2), or gas including at least one of hydrogen bromide (HBr), chlorine (Cl2) or sulfur hexafluorine (SF6), [0101].
Further, there was a need to select an etchant for the first isotropic etching before the effective filing date of the claimed invention.
It would have been obvious to use sulfur hexafluorine (SF6) as the etchant during the first isotropic etching process as taught by Kim as this would have been obvious to try since sulfur hexafluorine (SF6) is one solution for the etchant in isotropic etching and this would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 11, Huang in view of Pandey, Kim discloses The method of claim 1, wherein performing the isotropic etching step in the second etch step comprises performing the isotropic etching step using at least one of H2, CH4, CH2F2, CH3F, CHF3, CF4, SF6, NF3, C4F8, C4F6, Ar, or N2 (Kim discloses the isotropic dry etching may use the plasma of gas including substance with high reactivity with silicon, such as chlorine (Cl2) gas, gas including hydrogen bromide (HBr) and chlorine (Cl2), gas including sulfur hexafluorine (SF6) and chlorine (Cl2), or gas including at least one of hydrogen bromide (HBr), chlorine (Cl2) or sulfur hexafluorine (SF6), [0101].
Further, there was a need to select an etchant for the second isotropic etching before the effective filing date of the claimed invention.
It would have been obvious to use sulfur hexafluorine (SF6) as the etchant during the second isotropic etching process as taught by Kim as this would have been obvious to try since sulfur hexafluorine (SF6) is one solution for the etchant in isotropic etching and this would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 14, Huang in view of Pandey, Kim discloses The method of claim 1, further comprising:
removing the dummy gates (Huang discloses Referring to FIG. 10, the dummy gate structures 75A, 75B, and 75C (see FIG. 9) are replaced by replacement gate structures 97A, 97B, and 97C, respectively, [0044]);
forming a plurality of gates (Huang FIG. 10: replacement gate structures 97A, 97B, and 97C, respectively, [0044]) on the substrate where the dummy gates are removed (FIG. 10 shows 97A, 97B, 97C are formed on substrate 64/50 where dummy gates 75A, 75B, 75C are removed);
forming an interlayer dielectric layer (ILD 92 in FIG. 11 Huang, [0050], ILD is interlayer dielectric, [0042]) over the gates and source/drain regions (80, [0050]); and
forming conductive contacts (102, 104 in FIG. 16 Huang, [0066]-[0067]) extending through the interlayer dielectric layer to connect with the source/drain regions and the gates, respectively.
RE: Claim 15, The method of claim 1, further comprising forming a fin field effect transistor (FinFET) (FIGS. 2-7, 8A, 9-13, and 14A-14C are cross-sectional views of a FinFET device 100, [0015]; Huang discloses FinFET is a Fin Field-Effect Transistor, [0002]; Accordingly, the method forms a fin field effect transistor).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim as applied to claim 1 above, and further in view of US20180151440A1 (“Liao”) in view of US20160148969 A1 (“Tsai”) in view of US9263455 B2 (“Tang”) in view of US20150099345 A1 (“Kong”) in view of US20100099266 A1 (“Oswald”).
RE: Claim 4, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 1, wherein:
performing the anisotropic etching process in the first etch step comprises using a gas mixture of HBr, Cl2, and Ar, and
flow rates of the HBr, the Cl2, and the Ar are controlled within ranges of about 10- 500 sccm, 10-500 sccm, and 30-300 sccm, respectively.
In the same field of endeavor, Liao teaches process parameters such as, for example, a process gas mixture, a voltage bias, and an RF power may be chosen such that etching is predominantly performed using physical etching, such as ion bombardment, rather than chemical etching, such as radical etching through chemical reactions. In some embodiments, a voltage bias may be increased to increase energy of ions used in the ion bombardment process and, thus, increase a rate of physical etching. Since, the physical etching i[s] anisotropic in nature and the chemical etching is isotropic in nature, such an etching process has an etch rate in the vertical direction that is greater than an etch rate in the lateral direction, [0049].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a voltage bias and/or RF power for the anisotropic etching process as taught by Liao in order to ensure the etching process is anisotropic.
In a similar field of endeavor, Tsai discloses the etching process 32 is a dry etching process over the back side S1 of the semiconductive substrate 1, [0056]. The dry etching process implements any suitable gas such as an oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr, He and/or CHBR3), iodine-containing gas, other suitable gases (Ar and/or CH4) and/or plasmas, and/or combinations thereof, [0056].
Tsai further discloses the semiconductive substrate 1 is made from silicon. The semiconductive substrate 1 includes bulk silicon, [0021].
Accordingly, before the effective filing date of the claimed invention, there was a need to select a gas mixture for etching the silicon in the substrate 50/64 in Huang.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a gas mixture of HBr, Ar, Cl2 for the anisotropic etching process as this would have been obvious to try since as this is one solution for the process gas mixture for etching silicon provided by Tsai and this would have had a reasonable expectation of success, see MPEP 2143. Further, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
As modified, as a HBr, Cl2, and Ar gas mixture is used during the anisotropic etching process, there would be a flow rate for each of the HBr, the Cl2, and the Ar.
Further, in a similar field of endeavor, Tang discloses where active area material 12 comprises elemental silicon, an example technique for producing the isolation trench outline as shown in FIGS. 10 and 11 includes a substantially anisotropic silicon etch in a suitable chamber at a pressure of from about 20 mTorr to 50 mTorr; substrate susceptor temperature at from about 10° C. to 70° C.; power to the chamber at from about 600 Watts to 950 Watts; HBr flow to the chamber at from about 300 sccm to 600 sccm (Col. 8, lines 20-27).
Further, in a similar field of endeavor, Kong discloses The chlorine or bromine containing gas may be provided at any flow rate suitable to provide a sufficient amount of chlorine to facilitate etching the silicon containing layer 204. For example, in some embodiments, the chlorine containing gas may be provided at a flow rate of about 50 to about 1000 sccm, [0022].
Further, in a similar field of endeavor, Oswald discloses between about 0 to about 400 sccm of Ar are provided to the mixing manifold for a process suitable for etching silicon material, [0054].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the claimed flow rates of the HBr, the Cl2, and the Ar within ranges of about 10- 500 sccm, 10-500 sccm, and 30-300 sccm, respectively as these flow rate ranges overlap with flow rate ranges of HBr, the Cl2, and Ar provided by Tang, Kong, Oswald when etching silicon. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim as applied to claim 1 above, and further in view of US 20040079632 A1 (“Ahmad”) in view of US 6379575 B1 (“Yin”) further in view of US 20130025663 A1 (“Liu”).
RE: Claim 5, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 1, wherein the anisotropic etching process in the first etch step is performed with a pressure of about 2-80 mTorr and a bias power of about 50 to 3000 W at a temperature of about 25-100°C.
In the same field of endeavor, Ahmad discloses physical etch step 14 employs a very low pressure of, for example, between 1.0 and 4.0 mTorr, in order to reduce collisions between ions and increase their means free path thereby increasing the anisotropic nature of the etch process, [0028].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the anisotropic etching process with a pressure in the claimed range 2-80 mTorr as this range overlaps the pressure range taught by Ahmad for anisotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
In the same field of endeavor, Yin discloses the power ratio P.sub.r of the source current power level (to inductor antenna 115) to the bias voltage power level (to the process electrodes 120, 125) is selected to enhance the ability of the etchant plasma to anisotropically etch the silicon-containing layers with high selectivity relative to the overlying mask layer, Col. 11, lines 45-51. Yin further discloses The plasma is formed by applying a current at a source power level of about 400 to about 3000 Watts to the inductor antenna 115 encircling the plasma zone 35; and the plasma ions are is attracted toward the substrate 25 by applying a voltage at a power level of about 20 to about 1000 Watts to the process electrodes 120, 125 in the plasma zone, Col. 11 line 65 to Col. 12 line 5. Accordingly, Yin is understood as teaching a bias power of 20 to about 1000 Watts.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a bias power of 1000 Watts for the anisotropic etching process as taught by Yin in order to enhance the ability of the etchant plasma to anisotropically etch the silicon as further taught by Yin.
Further, in the same field of endeavor Liu discloses in some embodiments, the greater than room temperature anisotropic silicon etch that is employed in expanding each of the openings 14 can be performed at a temperature within a range from 41°C. to 95°C, [0047].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the anisotropic etching process at a temperature of about 25-100°C as this temperature range overlaps the temperature range taught by Liu for anisotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim, in view of Ahmad, Yin, Liu as applied to claim 5, and further in view of US 20200075423 A1 to Kwok et al. (hereinafter “Kwok”), further in view of US20180226259A1 (“Choi”).
RE: Claim 6, Huang, in view of Pandey, Kim, Ahmad, Yin, Liu does not explicitly disclose The method of claim 5, wherein:
performing the anisotropic etching process in the first etch step comprises performing the anisotropic etching process for about 5 to 300 seconds, and
performing the isotropic etching process in the first etch step comprises performing the isotropic etching process for about 3 to 300 seconds.
However, in the same field of endeavor, Kwok discloses recesses 81 are formed in the fins 52. Epitaxial source/drain regions 82 (see FIGS. 15A-C) are subsequently formed in the recesses 81 of the fins 52, [0045]. The recesses 81 may be formed using a suitable anisotropic dry etching process, [0045].
Kwok further discloses the anisotropic dry etching process may be a plasma etching process, and the plasma etching process may be performed for a duration of time between about 30 seconds and about 1000 seconds. In some embodiments, process parameters of the plasma etching process may be controlled to control the characteristics of the recesses 81, such as depth, shape, width, or other characteristics, [0045].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the anisotropic etching process for a duration of about 5 to 300 seconds as this duration time range overlaps the duration time range in Kwok for anisotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Further, in the same field of endeavor, Choi discloses Second portion 414 may be characterized by a circular or ovular shape due to the isotropic nature of the etch performed to produce that portion, [0069]. As the time increases for the etching operation from about 5 seconds to about 20 seconds, the diameter of the second portion 414 may increase from about 10 nm to about 50 nm. Depending on the size of second portion 414, the etching operation may be performed for less than or about 30 seconds, and may be performed for less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 5 seconds, [0069].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process for a duration of about 3 to 300 seconds as this duration time range overlaps the duration time ranges in Choi for isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim as applied to claim 1 above, further in view of Liao, further in view of US 20210134973 A1 (“Huang-2”).
RE: Claim 8, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 1, wherein:
performing the isotropic etching process in the first etch step comprises using a gas mixture of H2, Ar, and N2, and
flow rates of the H2, the Ar, and the N2 are controlled within ranges of about 50 to 500 sccm, 20 to 300 sccm, and 5 to 200 sccm, respectively.
In the same field of endeavor, Liao discloses process parameters such as, for example, a process gas mixture may be chosen such that etching is predominantly performed using chemical etching rather than physical etching. In some embodiments, a voltage bias may be reduced to reduce energy of ions used in the ion bombardment process and, thus, reduce a rate of physical etching. Since, the physical etching in anisotropic in nature and the chemical etching is isotropic in nature, such an etching process has an etch rate in the vertical direction that is substantially same as an etch rate in the lateral direction, [0050].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a voltage bias and/or RF power for the first isotropic etching process as taught by Liao in order to ensure the etching process is isotropic.
In a similar field of endeavor, Huang-2 discloses FIGS. 18A and 18B illustrate the removal of dummy silicon layer 82 through an etching process, [0042]. The etching process 94 is performed using a mixed gas of hydrogen (H.sub.2) and Nitrogen tri-fluoride (NF.sub.3). Other gases such as N.sub.2, Ar, He, or combinations thereof may also be added, [0043].
Accordingly, before the effective filing date of the claimed invention, there was a need to select etchant(s) for etching silicon.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a mixture of gases including H2, the Ar, and the N2 for the isotropic etching as this would have been obvious to try since a mixture of gases including H2, the Ar, and the N2 is one solution for etching silicon provided by Huang-2 and this would have had a reasonable expectation of success, see MPEP 2143.
Huang-2 further discloses The flow rate of hydrogen may be in the range between about 100 sccm and about 5,000 sccm, and the flow rate of NF.sub.3 may be in the range between about 5 sccm and about 100 sccm. The flow rate of N.sub.2 may be in the range between about 0 sccm and about 5,000 sccm. The flow rate of Ar may be in the range between about 0 sccm and about 1,000 sccm. The flow rate of He may be in the range between about 0 sccm and about 4,000 sccm, [0043].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use flow rates of the H2, the Ar, and the N2 within ranges of about 50 to 500 sccm, 20 to 300 sccm, and 5 to 200 sccm, respectively as these ranges overlap the flow rate ranges in Huang-2 for H2, the Ar, and the N2 during etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
RE: Claim 9, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 1, wherein:
the etchant used in the isotropic etching process in the first etch step is at least one of CH4, CH2F2, CH3F, CHF3, CF4, SF6, NF3, C4F8, or C4F6; and
a flow rate of the CH4, the CH2F2, the CH3F, the CHF3, the CF4, the SF6, the NF3, the C4F8, or the C4F6 is controlled within a range of about 5 to 200 sccm.
However in the same field of endeavor, Liao discloses process parameters such as, for example, a process gas mixture may be chosen such that etching is predominantly performed using chemical etching rather than physical etching. In some embodiments, a voltage bias may be reduced to reduce energy of ions used in the ion bombardment process and, thus, reduce a rate of physical etching. Since, the physical etching in anisotropic in nature and the chemical etching is isotropic in nature, such an etching process has an etch rate in the vertical direction that is substantially same as an etch rate in the lateral direction, [0050].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a voltage bias and/or RF power for the first isotropic etching process as taught by Liao in order to ensure the etching process is isotropic.
In a similar field of endeavor, Huang-2 discloses FIGS. 18A and 18B illustrate the removal of dummy silicon layer 82 through an etching process, [0042]. The etching process 94 is performed using a mixed gas of hydrogen (H.sub.2) and Nitrogen tri-fluoride (NF.sub.3). Other gases such as N.sub.2, Ar, He, or combinations thereof may also be added, [0043].
Accordingly, before the effective filing date of the claimed invention, there was a need to select etchant(s) for etching silicon.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Nitrogen tri-fluoride (NF3) for the isotropic etching as this would have been obvious to try since Nitrogen tri-fluoride (NF3) is one solution for etching silicon provided by Huang-2 and this would have had a reasonable expectation of success, see MPEP 2143.
Huang-2 further discloses, The flow rate of hydrogen may be in the range between about 100 sccm and about 5,000 sccm, and the flow rate of NF.sub.3 may be in the range between about 5 sccm and about 100 sccm, [0043].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a flow rate of NF3 within a range of about 5 to 200 sccm as this range overlaps the flow rate range in Huang-2 for NF3 during etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim as applied to claim 7 above, further in view of US6767821 B1 (“Yang”), further in view of Choi.
RE: Claim 10, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 7, wherein performing the isotropic etching process in the first etch step comprises performing the isotropic etching process with a bias power of about 10 to 300 W and a pressure of about 2 to 80 mTorr at a temperature of about 25 to 100°C for a duration of about 3 to 150 seconds.
In the same field of endeavor, Yang discloses an isotropic plasma etch (IPE) process, Col. 3 Lines 62-65.
Yang further discloses The IPE process of the period 108 may be performed using, e.g., the DPS reactor. In one exemplary embodiment, the period 108 supplies about 20 to 500 sccm of sulfur hexafluoride, applies plasma power of about 200 to 3000 Watts and bias power of about 0 to 300 Watts, and maintains a gas pressure in the process chamber at about 5 to 500 mTorr and a wafer temperature at about 10 to 100 degrees Celsius. One illustrative process provides 250 sccm of SF.sub.6, applies 1000 Watts of plasma power and 20 W of bias power, a pressure of 40 mtorr and a temperature of 10 degrees Celsius. The process provides relative selectivity to polysilicon (wall 206) over the polymeric coating (protective mask 112) of about 20:1 or greater and, as such, facilitates directional notching of the wall in the unprotected bottom portion 207, Col. 4, lines 21-36.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process with a bias power of about 10 to 300 W and a pressure of about 2 to 80 mTorr at a temperature of about 25 to 100°C as these ranges overlap the bias power, pressure, and temperature ranges in Yang during isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Further, in the same field of endeavor, Choi discloses Second portion 414 may be characterized by a circular or ovular shape due to the isotropic nature of the etch performed to produce that portion, [0069]. The time increases for the etching operation from about 5 seconds to about 20 seconds, the diameter of the second portion 414 may increase from about 10 nm to about 50 nm. Depending on the size of second portion 414, the etching operation may be performed for less than or about 30 seconds, and may be performed for less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 5 seconds, or less in embodiments, [0069].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process for a duration of about 3 to 150 seconds as this duration time range overlaps the duration time range in Choi during isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
RE: Claim 12, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 11, wherein performing the isotropic etching process in the first etch step comprises performing the isotropic etching process with a bias power of about 30 to 1000 W and a pressure of about 2 to 80 mTorr at a temperature of about 25 to 100°C for a duration of about 3 to 150 seconds.
In the same field of endeavor, Yang discloses an isotropic plasma etch (IPE) process, Col. 3 Lines 62-65.
Yang further discloses The IPE process of the period 108 may be performed using, e.g., the DPS reactor. In one exemplary embodiment, the period 108 supplies about 20 to 500 sccm of sulfur hexafluoride, applies plasma power of about 200 to 3000 Watts and bias power of about 0 to 300 Watts, and maintains a gas pressure in the process chamber at about 5 to 500 mTorr and a wafer temperature at about 10 to 100 degrees Celsius. One illustrative process provides 250 sccm of SF.sub.6, applies 1000 Watts of plasma power and 20 W of bias power, a pressure of 40 mtorr and a temperature of 10 degrees Celsius. The process provides relative selectivity to polysilicon (wall 206) over the polymeric coating (protective mask 112) of about 20:1 or greater and, as such, facilitates directional notching of the wall in the unprotected bottom portion 207, Col. 4, lines 21-36.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process with a bias power of about 30 to 1000 W and a pressure of about 2 to 80 mTorr at a temperature of about 25 to 100°C as these ranges overlap the bias power, pressure, and temperature ranges in Yang during isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Further, in the same field of endeavor, Choi discloses Second portion 414 may be characterized by a circular or ovular shape due to the isotropic nature of the etch performed to produce that portion, [0069]. The time increases for the etching operation from about 5 seconds to about 20 seconds, the diameter of the second portion 414 may increase from about 10 nm to about 50 nm. Depending on the size of second portion 414, the etching operation may be performed for less than or about 30 seconds, and may be performed for less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 5 seconds, or less in embodiments, [0069].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process for a duration of about 3 to 150 seconds as this duration time range overlaps the duration time range in Choi during isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Kim as applied to claim 1, further in view of US20150294975 A1 (“Nakata”), further in view of Yang.
RE: Claim 13, Huang in view of Pandey, Kim does not explicitly disclose The method of claim 1, wherein performing the second etch step comprises performing the second etch step with a bias power lower than a bias power applied to the anisotropic etching process in the first etch step and higher than a bias power applied to the isotropic etching process in the first etch step.
In the same field of endeavor, Nakata discloses Isotropic dry etching can be implemented by using conditions adjusted such that, compared with anisotropic dry etching, the pressure is increased and the bias power is decreased, [0099].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the bias power for the second isotropic etching process decreased relative to the bias power used for the anisotropic etching process as taught by Nakata in order to ensure the second isotropic etching process is isotropic.
In the same field of endeavor, Yang discloses an isotropic plasma etch (IPE) process, Col. 3 Lines 62-65.
Yang further discloses The IPE process of the period 108 may be performed using, e.g., the DPS reactor. In one exemplary embodiment, the period 108 supplies about 20 to 500 sccm of sulfur hexafluoride, applies plasma power of about 200 to 3000 Watts and bias power of about 0 to 300 Watts, and maintains a gas pressure in the process chamber at about 5 to 500 mTorr and a wafer temperature at about 10 to 100 degrees Celsius. One illustrative process provides 250 sccm of SF.sub.6, applies 1000 Watts of plasma power and 20 W of bias power, a pressure of 40 mtorr and a temperature of 10 degrees Celsius. The process provides relative selectivity to polysilicon (wall 206) over the polymeric coating (protective mask 112) of about 20:1 or greater and, as such, facilitates directional notching of the wall in the unprotected bottom portion 207, Col. 4, lines 21-36.
Accordingly, before the effective filing date of the claimed invention, there was a need to select bias powers for the first and second isotropic etching.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a bias power applied in the second isotropic etching process in the range 0 to 300 Watts such as 300 Watts as taught by Yang as this would have been obvious to try since this falls within the bias power range identified by Yang for isotropic etching and this would have had a reasonable expectation of success, see MPEP 2143.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a bias power applied in the first isotropic etching process in the range 0 to 300 Watts such as 0 Watts as taught by Yang as this would have been obvious to try since this falls within the bias power range identified by Yang for isotropic etching and this would have had a reasonable expectation of success, see MPEP 2143.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, further in view of Yin, further in view of US20130005127A1 (“Yin-2”).
RE: Claim 18, Huang discloses A method of forming a source/drain region (80, [0014]) in a semiconductor device (100, FIGS. 2-7, 8A, 9-13, and 14A-14C are cross-sectional views of a FinFET device 100 at various stages of fabrication in accordance with some embodiments, [0015]), comprising:
etching a portion of (portion of 64) a substrate (64/50) exposed by a mask layer (75, 87, dummy gate structures 75 and gate spacers 87 are used as a mask, [0037]) over the substrate (recesses 88 are formed in the fins 64 adjacent to the dummy gate structures 75, e.g., between adjacent dummy gate structures 75 and/or next to a dummy gate structure 75. The recesses 88 are formed by, e.g., an anisotropic etching process using the dummy gate structures 75 and the gate spacers 87 as an etching mask, [0037], see FIGs. 6-7);
removing the portion of the substrate by performing a first etch step (anisotropic etching, [0037]), wherein:
the first etch step comprises:
an anisotropic etching process (anisotropic etching, [0037]); and
growing an epitaxial source/drain region (80, [0039]) from a recess created by removing the portion of the substrate (source/drain regions 80 are formed in the recesses 88. The source/drain regions 80 are formed by epitaxially growing a material in the recesses 88, [0038]).
Huang does not explicitly disclose:
the removing the portion of the substrate is performed by performing the first etch step and a second etch step, wherein:
the first etch step further comprises:
a first isotropic etching process in combination with the anisotropic etching process with a bias power different from a bias power applied to the anisotropic etching process, and
the second etch step comprises a second isotropic etching process performed with a bias power higher than the bias power applied to the first isotropic etching process; and wherein
the epitaxial source/drain region has a first width at a first depth into the substrate, a second width at a second depth greater than the first depth, and a third width at a third depth greater than the second depth,
the second width is less than the first width and less than the third width, and
the first width, the second width, and the third width are measured in a channel length direction.
In the same field of endeavor, Pandey discloses FIGS. 2A-2H depict various illustrative and novel methods of forming source/drain regions on FinFET devices, [0026].
Pandey further discloses:
removing a portion (portion of 104) of the substrate (102, 104, [0026]-[0027]) by performing a first etch step (first etching process 120 and second etching process 124, [0030]-[0031], FIGs. 2C-2D) and a second etch step (third etching process 136, [0032]-[0033], FIG. 2F), wherein:
the first etch step comprises:
an anisotropic etching process (first etching process 120 is an anisotropic etching process, [0030], FIG. 2C); and
a first isotropic etching process (second etching process 124 is an isotropic etching process, [0031], hereafter “first isotropic etching process”) in combination with the anisotropic etching process (FIGs. 2C-2D show the first isotropic etching process 124 was performed after the anisotropic etching process 120 to form a second cavity 130; Accordingly, the first isotropic etching process 124 is performed in combination with the anisotropic etching process 120 to form the second cavity 130), and
the second etch step comprises a second isotropic etching process performed (136 is an isotropic etching process, [0033], hereafter “second isotropic etching process”); and
growing an epitaxial source/drain region (150, [0034]; FIGS. 2A-2H depict various illustrative and novel methods of forming source/drain regions on FinFET devices, [0026]; an epitaxial growth process was performed to grow epi semiconductor material 150 in the final cavity 140, [0034]; third final cavity 140 constitutes a unique source/drain cavity for the FinFET device 100, [0033]; Accordingly, 150 are source/drain regions) from a recess (140) created by removing the portion of the substrate, wherein
the epitaxial source/drain region has a first width at a first depth into the substrate (Annotated FIG. 2G below shows 150 has a first width at a first depth into the substrate), a second width at a second depth greater than the first depth (Annotated FIG. 2G below shows 150 has a second width at a second depth greater than the first depth), and a third width at a third depth greater than the second depth (Annotated FIG. 2G below shows 150 has a third width at a third depth greater than the second depth),
the second width is less than the first width and less than the third width (Annotated FIG. 2G below shows the second width is less than the first width and less than the third width), and
the first width, the second width, and the third width are measured in a channel length direction (the channel region 155 has a horizontal length in FIG. 2F; Accordingly, the channel length direction is the horizontal direction; Annotated FIG. 2G below show the first width, the second width, and the third width are measured in the horizontal direction).
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(Annotated FIG. 2G of Pandey)
Pandey further discloses FIG. 2H depicts the results of simulations that were run which indicate that formation of the novel final cavity 140 with the stepped profile disclosed herein should increase the performance capabilities of FinFET devices as, [0035].
Pandey further discloses Simulations also predict that the drive current for a FinFET device formed with the unique source/drain cavity 140 depicted herein will be about 2-3 percent greater, [0035].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further perform a first isotropic process and a second isotropic process, thereby forming a recess 88 with a stepped profile as taught by Pandey in order to increase performance and drive current as further taught by Pandey.
In the same field of endeavor, Yin discloses the power ratio P.sub.r of the source current power level (to inductor antenna 115) to the bias voltage power level (to the process electrodes 120, 125) is selected to enhance the ability of the etchant plasma to anisotropically etch the silicon-containing layers with high selectivity relative to the overlying mask layer, Col. 11, lines 45-51. Yin further discloses The plasma is formed by applying a current at a source power level of about 400 to about 3000 Watts to the inductor antenna 115 encircling the plasma zone 35; and the plasma ions are is attracted toward the substrate 25 by applying a voltage at a power level of about 20 to about 1000 Watts to the process electrodes 120, 125 in the plasma zone, Col. 11 line 65 to Col. 12 line 5. Accordingly, Yin is understood as teaching applying a bias power of 20 to about 1000 Watts during anisotropic etching.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set a bias power of 1000 Watts for the anisotropic etching process as taught by Yin in order to enhance the ability of the etchant plasma to anisotropically etch the silicon as further taught by Yin.
In the same field of endeavor, Yin-2 discloses the semiconductor substrate 30 at the bottom of the fin 301 is isotropically etched by using the spacer 32 as a mask, so as to form the gap 33 between the fin 301 and the semiconductor substrate 30. In this embodiment, the isotropic etching may use a gas comprising Cl.sub.2, HBr, He and O.sub.2, with Cl.sub.2 having a flow rate ranging from 15 sccm to 25 sccm, and HBr having a flow rate ranging from 0.5 sccm to 2 sccm; and the etching may use a pressure ranging from 50 mtorr to 100 mtorr, a RF power ranging from 800 W to 1500 W, and a bias power ranging from 60 W to 120 W, [0056].
Accordingly, before the effective filing date of the claimed invention, there was a need to select bias powers for the first and second isotropic etching processes.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the bias power to 60W for the first isotropic etching as this would have been obvious to try since 60W is one solution for the bias power when isotropic etching identified by Yin-2 and this would have had a reasonable expectation of success, see MPEP 2143.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the bias power to 120W for the second isotropic etching as this would have been obvious to try since 120W is one solution for the bias power when isotropic etching identified by Yin-2 and this would have had a reasonable expectation of success, see MPEP 2143.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Yin, Yin-2 as applied to claim 18, further in view of Kwok, further in view of Choi.
RE: Claim 19, Huang in view of Pandey, Yin, Yin-2 discloses The method of claim 18, wherein:
the bias power applied to the anisotropic etching process in the first etch step is about 50 to 3000 W (As modified, the bias power applied to the anisotropic etching process is 1000W), and
the bias power applied to the first isotropic etching process in the first etch step is about 10 to 300 W (As modified, the bias power applied to the first isotropic etching process is 60W).
Huang in view of Pandey, Yin, Yin-2 does not explicitly disclose:
the bias power applied to the anisotropic etching process in the first etch step is applied for about 5 to 300 seconds, and
the bias power applied to the first isotropic etching process in the first etch step is applied for about 3 to 150 seconds.
However, in the same field of endeavor, Kwok discloses recesses 81 are formed in the fins 52. Epitaxial source/drain regions 82 (see FIGS. 15A-C) are subsequently formed in the recesses 81 of the fins 52, [0045]. The recesses 81 may be formed using a suitable anisotropic dry etching process, [0045].
Kwok further discloses the anisotropic dry etching process may be a plasma etching process, and the plasma etching process may be performed for a duration of time between about 30 seconds and about 1000 seconds. In some embodiments, process parameters of the plasma etching process may be controlled to control the characteristics of the recesses 81, such as depth, shape, width, or other characteristics, [0045].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the anisotropic etching process for a duration of about 5 to 300 seconds as this duration time range overlaps the duration time range in Kwok for anisotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Further, in the same field of endeavor, Choi discloses Second portion 414 may be characterized by a circular or ovular shape due to the isotropic nature of the etch performed to produce that portion, [0069]. As the time increases for the etching operation from about 5 seconds to about 20 seconds, the diameter of the second portion 414 may increase from about 10 nm to about 50 nm. Depending on the size of second portion 414, the etching operation may be performed for less than or about 30 seconds, and may be performed for less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 5 seconds, [0069].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the first isotropic etching process for a duration of about 3 to 150 seconds as this duration time range overlaps the duration time ranges in Choi for isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey, Yin, Yin-2 as applied to claim 18, further in view of Choi.
RE: Claim 20, Huang in view of Pandey, Yin, Yin-2 discloses The method of claim 18, wherein:
the bias power applied to the second isotropic etching process in the second etch step is about 30 to 1000 W (As modified, the bias power applied to the second isotropic process is 120W) and is applied for about 3 to 150 seconds.
Huang in view of Pandey, Yin, Yin-2 does not explicitly disclose:
the bias power applied to the second isotropic etching process in the second etch step is applied for about 3 to 150 seconds.
In the same field of endeavor, Choi discloses Second portion 414 may be characterized by a circular or ovular shape due to the isotropic nature of the etch performed to produce that portion, [0069]. As the time increases for the etching operation from about 5 seconds to about 20 seconds, the diameter of the second portion 414 may increase from about 10 nm to about 50 nm. Depending on the size of second portion 414, the etching operation may be performed for less than or about 30 seconds, and may be performed for less than or about 25 seconds, less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 5 seconds, [0069].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the second isotropic etching process for a duration of about 3 to 150 seconds as this duration time range overlaps the duration time ranges in Choi for isotropic etching. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Pandey.
RE: Claim 21, Huang discloses A method of forming a semiconductor device structure (100, FIGS. 2-7, 8A, 9-13, and 14A-14C are cross-sectional views of a FinFET device 100 at various stages of fabrication in accordance with some embodiments, [0015]), the method comprising:
forming a semiconductor fin (65, [0014]; 65 are doped regions in the fins 64, [0033]);
forming a gate (97A, 97B, 97C in FIG. 10, [0044]) over the semiconductor fin;
performing a first etch step to remove a first portion of the semiconductor fin (portion of 65 in FIG. 6 which is removed in FIG. 7) and a first portion of a semiconductor strip below the semiconductor fin (lower portion of 64 below 65 in FIG. 6 which is removed in FIG. 7) to define a recess (88 in FIG. 7);
forming an epitaxial source/drain region (80 in FIG. 8A, [0014]) in the recess.
Huang does not explicitly disclose:
removing the first portion of the semiconductor fin exposes an isolation region in the recess;
a second portion of the semiconductor fin is concealed by the gate, and
performing the first etch step comprises:
performing an anisotropic etching process; and
performing an isotropic etching process after performing the anisotropic etching process, wherein after the isotropic etching process, the recess has a slope that continues to decrease when moving from a top of the semiconductor fin to a location of the semiconductor strip defining a bottom of the recess;
performing a second etch step to remove a second portion of the semiconductor strip laterally adjacent the first portion of the semiconductor strip to yield a modified recess; and
forming an epitaxial source/drain region in the modified recess.
In the same field of endeavor, Pandey discloses:
performing a first etch step to remove a first portion of the semiconductor fin (upper portion of fin 104 in FIG. 2A which is removed in FIG. 2C) and a first portion of a semiconductor strip below the semiconductor fin (lower portion of fin 104 in FIG. 2C which is removed in FIG. 2D and which was below the upper portion of 104) to define a recess (130; Pandey discloses a first etching process 120, i.e., an anisotropic etching process, was performed to define a first cavity 122, [0030]; a second etching process 124, i.e., an isotropic etching process, was performed to define a second cavity 130, [0031]), wherein:
removing the first portion of the semiconductor fin exposes an isolation region (isolation 106 labeled in FIG. 2A, [0027]) in the recess (FIG. 2D shows the second etching process 124 exposes isolation 106);
a second portion of the semiconductor fin is concealed by the gate (FIG. 2D shows a second portion of 104 concealed by gate 114, [0029]), and
performing the first etch step comprises:
performing an anisotropic etching process (first etching process 120 is an anisotropic etching process, [0030], FIG. 2C); and
performing an isotropic etching process (second etching process 124 is an isotropic etching process, FIG. 2D, [0031], hereafter “first isotropic etching process”) after performing the anisotropic etching process, wherein after the isotropic etching process, the recess has a slope that continues to decrease when moving from a top of the semiconductor fin to a location of the semiconductor strip defining a bottom of the recess (FIG. 2D shows the recess 130 has a slope that continues to decrease when moving from an upper part of the semiconductor fin 104 to a location of the lower part of the fin 104 defining a bottom of the recess and the claimed semiconductor strip);
performing a second etch step to remove a second portion of the semiconductor strip laterally adjacent the first portion of the semiconductor strip to yield a modified recess (140; Annotated FIG. 2F below shows second isotropic etching 136 is performed to remove a second portion of the semiconductor strip laterally adjacent the first portion of the semiconductor strip to yield a modified recess 140); and
forming an epitaxial source/drain region (150 in FIG. 2G; 150, [0034]; FIGS. 2A-2H depict various illustrative and novel methods of forming source/drain regions on FinFET devices, [0026]; an epitaxial growth process was performed to grow epi semiconductor material 150 in the final cavity 140, [0034]; third final cavity 140 constitutes a unique source/drain cavity for the FinFET device 100, [0033]; Accordingly, 150 are source/drain regions) in the modified recess.
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(Annotated FIG. 2F of Pandey)
Pandey further discloses FIG. 2H depicts the results of simulations that were run which indicate that formation of the novel final cavity 140 with the stepped profile disclosed herein should increase the performance capabilities of FinFET devices as, [0035].
Pandey further discloses Simulations also predict that the drive current for a FinFET device formed with the unique source/drain cavity 140 depicted herein will be about 2-3 percent greater, [0035].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further perform a first isotropic process and a second isotropic process, thereby forming a recess 88 with a stepped profile as taught by Pandey in order to increase performance and drive current as further taught by Pandey.
RE: Claim 22, Huang in view of Pandey discloses The method of claim 21, wherein:
the modified recess has a first width at a first vertical position (Annotated FIG. 2F Pandey below shows 140 has a first width at a first vertical position), a second width at a second vertical position above the first vertical position (Annotated FIG. 2F Pandey below shows 140 has a second width at a second vertical position above the first vertical position), and a third width at a third vertical position above the second vertical position (Annotated FIG. 2F Pandey below shows 140 has a third width at a third vertical position above the second vertical position), and
the second width is less than the first width and less than the third width (Annotated FIG. 2F Pandey below shows the second width is less than the first width and less than the third width; Accordingly, as modified, the modified recess 88 in Huang would have a first width at a first vertical position, a second width at a second vertical position above the first vertical position, and a third width at a third vertical position above the second vertical position; wherein the second width is less than the first width and less than the third width).
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(Annotated FIG. 2G of Pandey)
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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