DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 27 2026 has been entered.
Claim Objections
Claim 10 is objected to because of the following informalities: “dispensing an adhesive layer on a top surface the package substrate” is grammatically incorrect. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 20-21, 23-27, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Too et al. (“Too” US 2013/0309814), Im et al. (“Im” US 2004/0036183), Lee et al. (“Lee” US Patent No. 9,704,842), Heo et al. (“Heo” US 2022/0399311), and Hua et al. (“Hua” US 2003/0209801).
Regarding claim 18, Too discloses a method comprising:
bonding a plurality of integrated circuit dies to a wafer in a package region of the wafer (para. [0005]);
forming a back-side metal layer (28) on [the molding compound and] back-sides of the plurality of integrated circuit dies (plurality of die is shown in Figure 5);
depositing a first flux (step 60, Figure 3, para. [0029]) on back-sides of the integrated circuit dies (12) of the bonded package component;
attaching a thermal interface material to the first flux (22, step 70, Figure 3), the thermal interface material comprising indium (para. [0024]);
forming a second flux (flux applied to thermal interface material, see para. [0031]) on the thermal interface material (22);
attaching a lid (20) to the package substrate (14, Figure 2), the thermal interface material (22) [and the retaining structure] being coupled to the lid (20, Figure 2); and
performing a bonding process (Figure 3, bonding process steps 85/90, see para. [0032]-[0033]) to bond the thermal interface material (22) to the back-side metal layer (28) and the lid (20, see para. [0033]), the bonding process (85/90) comprising:
a first step (85) of heating to a temperature (100 degrees Celsius, see para. [0032]) less than a melting point of the indium (the melting point of indium is around 150 degrees Celsius) while applying a compressive force (see para. [0032]) to at least one of the lid and the package substrate (applied to the lid 20, see para. [0031]); and
a second step (90) of heating to a temperature (170-190 degrees Celsius, see para. [0033]) greater than the melting point of the indium (the melting point of indium is around 150 degrees Celsius, this process is also a reflow process, which in the art is performed above the melting point temperature of the material).
Too does not disclose encapsulating the plurality of integrated circuit dies with a molding compound.
Lee discloses encapsulating the plurality of integrated circuit dies (20, Figure 11) with a molding compound (24, col. 11, line 62 – col. 10, line 9).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lee into the teachings of Too to include an encapsulation of the plurality of IC dies for the purpose of protecting the IC dies and exposing the top from the encapsulation to aid in heat dissipation (Lee, col. 11, line 62 – col. 10, line 9 and col. 9 lines16-17). Further, it would have been obvious to place the back-side metallization layer also on the molding compound (in additional to the IC dies) in order to improve adhesion between the molding compound and subsequently added layers, as this is a well-known method in the art to improve adhesion between elements of a semiconductor package.
Too does not disclose forming a retaining structure adjacent the package component and the thermal interface material.
Im discloses forming a retaining structure (106A) adjacent the package component (102, 110) and the thermal interface material (104, shown in Figure 8).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Im into the teachings of Too to include a retaining structure for the purpose of preventing the TIM from flowing down the semiconductor chip at high temperatures (Im, para. [0012]).
Too discloses, in the background section of the disclosure (para. [0005]-[0011]) a singulation process and bonding process (see para. [0005]):
[after forming the back-side metal layer], singulating the package region from the wafer to form a package component (“cutting” is a singulation process in para. [0005]);
bonding the package component to a package substrate (“structures” the packages are mounted to and the circuit board disclosed in para. [0005] are interpreted to include or be a package substrate).
However, Too does not provide evidence that this singulation and bonding process is employed for the embodiment of Figure 2. One of ordinary skill in the art would be motivated to apply this singulation and bonding process to the embodiment of Figure 2 of Too for the purpose of improving productivity in the electronics industry (Heo, para. [0004]).
The examiner notes that while Too discloses a second flux on the thermal interface material (see above), it would have been obvious to form the retaining structure (incorporation of the teachings of the retaining structure of Im) after forming said second flux because the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (see MPEP 2144.04(IV)(C), In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946), Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959), In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930)).
In the same vein, Too discloses forming the back-side metal layer, but does not explicitly disclose the order of steps of singulating the package region from the wafer after forming the back-side metal layer. However, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (see MPEP 2144.04(IV)(C), In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946), Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959), In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930)).
Finally, Too does not disclose that the second step of heating is performed while applying a compressive force to at least one of the lid and the package substrate.
Hus discloses, however, a reflow process (see Figure 4, para. [0034]-[0037]) performed while applying a compressive force (via the clips 450, see para. [0034]) to at least one of the lid (HIS 300) and the package substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hua into the teachings of Too to include a compressive force during the second heating process (reflow process) for the purpose of dissolving and migrating the solder material in order to improve bonding at a bonding interface (Hua, para. [0036]-[0037]).
Regarding claim 20, Im discloses wherein the retaining structure (106A) physically contacts the package component (Figure 8).
Regarding claim 21, Too discloses a method comprising:
forming a package component in a package region of a wafer, the package component comprising an integrated circuit die (para. [0005], Figure 2, Figure 5);
forming a metal layer (28) on a back-side of the integrated circuit die (12, Figure 2);
forming an underfill (26) between the package substrate (14) and the package component (die 12 and interconnects 24);
placing a thermal interface material (22) on the metal layer (28); and
attaching a lid (20) to the package substrate (14), the lid (20) being coupled to the thermal interface material (22, Figure 2); and
performing a bonding process (Figure 3, bonding process steps 85/90, see para. [0032]-[0033]) to bond the thermal interface material (22) to the metal layer (28) and the lid (20, see para. [0033]), the bonding process (85/90) comprising:
a first step (85) of heating to a temperature (100 degrees Celsius, see para. [0032]) less than a melting point of the indium (the melting point of indium is around 150 degrees Celsius) while applying a compressive force (see para. [0032]) to at least one of the lid and the package substrate (applied to the lid 20, see para. [0031]); and
a second step (90) of heating to a temperature (170-190 degrees Celsius, see para. [0033]) greater than the melting point of the indium (the melting point of indium is around 150 degrees Celsius, this process is also a reflow process, which in the art is performed above the melting point temperature of the material).
Too does not disclose forming a retaining structure on the package substrate adjacent the package component, wherein the retaining structure is configured to retain any bleeding or reflow of the thermal interface material.
Im discloses forming a retaining structure (106A) on the package substrate (100) adjacent the package component (Figure 8), wherein the retaining structure (106A) is configured to retain any bleeding or reflow of the thermal interface material (para. [0012]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Im into the teachings of Too to include a retaining structure for the purpose of preventing the TIM from flowing down the semiconductor chip at high temperatures (Im, para. [0012]).
The examiner notes that incorporation of the retaining structure of Im into the teachings of Too would result in the claimed feature requiring that the retaining structure extends from the underfill along the package component to a height higher than a top surface of the thermal interface material. This is accomplished from the combination because the retaining structure 106A of Figure 8 of Im extends from a top surface of the substrate 100 to a lower surface of the lid 108A (see Figure 8), therefore, incorporation of the retaining structure 106A into the package of Too would result in a configuration where the retaining structure extends from the surface that the underfill is on (the upper surface of the substrate 14, thus extending from the underfill) up to the lower surface of the lid 20 which is above the top surface of the thermal interface material 22, or at a height higher than the top surface of the thermal interface material 22 (see Figure 2 of Too along with Figure 8 of Im).
Too discloses, in the background section of the disclosure (para. [0005]-[0011]) a singulation process and bonding process (see para. [0005]):
singulating the package region from the wafer (para. [0005]);
connecting the package component to a package substrate (“structures” and circuit board in para. [0005] are interpreted to include or be a package substrate);
However, Too does not provide evidence that this singulation and bonding process is employed for the embodiment of Figure 2. One of ordinary skill in the art would be motivated to apply this singulation and bonding process to the embodiment of Figure 2 of Too for the purpose of improving productivity in the electronics industry (Heo, para. [0004]).
Finally, Too does not disclose that the second step of heating is performed while applying a compressive force to at least one of the lid and the package substrate.
Hus discloses, however, a reflow process (see Figure 4, para. [0034]-[0037]) performed while applying a compressive force (via the clips 450, see para. [0034]) to at least one of the lid (HIS 300) and the package substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hua into the teachings of Too to include a compressive force during the second heating process (reflow process) for the purpose of dissolving and migrating the solder material in order to improve bonding at a bonding interface (Hua, para. [0036]-[0037]).
Regarding claim 23, Too discloses wherein the thermal interface material (22) comprises indium (para. [0024]).
Regarding claim 24, Im discloses wherein the retaining structure (106A) physically contacts the package component (Figure 8).
Regarding claim 25, Too further discloses forming an underfill (26) between the package substrate (14) and the package component (die 12 and interconnects 24).
Regarding claim 26, Im discloses wherein the retaining structure (106A) physically contacts the lid (108A, Figure 8).
Regarding claim 27, Too further discloses dispensing an adhesive layer (18) on the package substrate (14), the adhesive layer (18) adhering the lid (20) to the package substrate (14, para. [0024]).
Regarding claim 31, Too discloses wherein the lid (20) comprises a second back-side metal layer (nickel layer 38, para. [0027]), the second back-side metal layer (38) contacting the second flux (flux layer disposed on top of the thermal interface material 22) and the retaining structure (incorporated from the teachings of Im).
The incorporation of the retaining structure 106A of Im into the teachings of Too would result in a configuration where the second back-side metal layer 38 contacts the retaining structure because Im’s retaining structure contacts the lower surface of the lid of Im in Figure 8.
Claims 10-11, 15, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Too, Im, Heo, and Lin et al. (“Lin” US 2020/0161275).
Regarding claim 10, Too discloses a method comprising:
packaging an integrated circuit die (12) in a package region of a wafer;
depositing a back-side metal layer (28, metallization stack) on a back-side of the integrated circuit die (12, shown in Figure 2);
placing a thermal interface material (22) on the back-side metal layer (28, Figure 2);
dispensing an adhesive layer (18) on a top surface the package substrate (14, see Figure 2),;
attaching a lid (20) to the package substrate (14) with the adhesive layer (18), the lid (20) being coupled to the thermal interface material (22, see Figure 2); and
performing a bonding process (reflow step 90, see para. [0033]) to bond the thermal interface material (22) to the back-side metal layer (28) and the lid (20, described in para. [0033]), the bonding process (reflow, step 90) being performed at a temperature greater than the melting point of the thermal interface material (22, the bonding process is a reflow process, thus it is clear that the process if performed at a temperature greater than the melting temperature of the thermal interface material since reflow processes are performed such that the material is melted).
Too does not disclose dispensing a retaining structure adjacent the package component and the thermal interface material.
Im discloses dispensing a retaining structure (106A) adjacent the package component (102, 110) and the thermal interface material (104, shown in Figure 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Im into the teachings of Too to include a retaining structure for the purpose of preventing the TIM from flowing down the semiconductor chip at high temperatures (Im, para. [0012]).
Too discloses, in the background section of the disclosure (para. [0005]-[0011]) a singulation process and bonding process (see para. [0005]):
singulating the package region from the wafer to form a package component (process is disclosed in para. [0005], background, “cutting” is interpreted to mean “singulating”);
after singulating the package region, connecting the package component to a package substrate (disclosed in para. [0005], “circuit board” or “structures” are interpreted to include a package substrate, such as substrate 14 in Figure 2);
However, Too does not provide evidence that this singulation and bonding process is employed for the embodiment of Figure 2. One of ordinary skill in the art would be motivated to apply this singulation and bonding process to the embodiment of Figure 2 of Too for the purpose of improving productivity in the electronics industry (Heo, para. [0004]).
The combination of Too and Im to teach the retaining structure and the adhesive layer do not disclose that the retaining structure and the adhesive layer are formed simultaneously of a same material.
Lin discloses, however, a process of dispensing an adhesive layer (60) on a top surface the package substrate (52, see Figure 3B) and a retaining structure (62 is called a “first TIM”, however has material retaining properties, and thus is considered a retaining structure, for the other “second TIM” 64 due to being positioned on a peripheral region of the second TIM 64 and having large particle sizes, see para. [0057]), wherein the retaining structure (62) and the adhesive layer (60) are formed simultaneously of a same material (see para. [0050] which discloses that the retaining structure 62 and the adhesive 60 are formed of the same material, and are dispensed by using the same dispenser in the same process step, thus are considered as being formed simultaneously in the manufacturing process).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of the combination of Too and Im above for the purpose of reducing manufacturing process times (Lin, para. [0050]).
Regarding claim 11, Im discloses wherein the retaining structure (106A) physically contacts the package component (102, 110, shown in Figure 8).
Regarding claim 15, Im discloses wherein the retaining structure (106A) physically contacts the lid (108A, shown in Figure 8).
Regarding claim 30, Too further discloses after placing a thermal interface material (22) on the back-side metal layer (28) and before attaching a lid (20) to the package substrate (14), dispensing an adhesive layer (18) on a top surface the package substrate (14, shown in Figure 2), the adhesive layer adhering the lid to the package substrate (para. [0024]).
Too discloses an order of steps in Figure 3 in which the lid adhesive is applied to the substrate prior to the thermal interface material being deposited. This order is the opposite order of what Applicant has claimed, however it would have been obvious to one of ordinary skill in the art at the time the invention was made to place the thermal interface material before placing the lid adhesive since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (see MPEP 2144.04(IV)(C), In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946), Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959), In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930)).
The examiner notes that the formation of the retaining structure 106A is accomplished through dispensing material (see Im, para. [0053]-[0055], Figures 8 and 10) onto the substrate 100, and the adhesive layer 18 of Too is formed by dispensing the adhesive material on the substrate 14 (see para. [0027]). Thus, the combination of the teachings of Im and Too above also teaches the limitation “wherein the adhesive and the retaining structure are formed by a same process.” Specifically, said same process is disposing both materials onto the package substrate.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Too and Im as applied to claim 27 above, and further in view of Lin et al. (“Lin” US 2020/0161275).
Regarding claim 28, Lin discloses an adhesive (60) and a retaining structure (62 is called a “first TIM”, however has material retaining properties, and thus is considered a retaining structure, for the other “second TIM” 64 due to being positioned on a peripheral region of the second TIM 64 and having large particle sizes, see para. [0057]), wherein the adhesive (60) and the retaining structure (62) have a same material composition.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of the combination of Too and Im above for the purpose of reducing manufacturing process times (Lin, para. [0050]).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Too and Im as applied to claim 21 above, and further in view of Lin et al. (“Lin” US 2020/0161275).
Regarding claim 29, Im discloses wherein the retaining structure (106A) comprises a polymeric material (epoxy is a well-known polymeric material, para. [0032])
Im does not disclose a filler material used for the retaining structure.
Lin discloses, however, a retaining structure (62 is called a “first TIM”, however has material retaining properties, and thus is considered a retaining structure, for the other “second TIM” 64 due to being positioned on a peripheral region of the second TIM 64 and having large particle sizes, see para. [0057]) comprising a polymeric material (see para. [0037], “base material” is a polymer material) and a filler material (62f, see para. [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Lin into the teachings of Too and Im to include using a polymeric and filler material composition for the retaining structure for the purpose of further preventing overflow of the thermal interface material due to the filler particles (Lin, para. [0056]).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Too and Im as applied to claim 21 above, and further in view of Wang et al. (“Wang” US 2009/0321948).
Too does not disclose that the first step and the second step are performed in a same process chamber without breaking an ambient atmosphere of the chamber.
Wang discloses, however, first and second heating steps (curing/reflow cycles, see para. [0023]) performed in the same process chamber (heating chamber 150) without breaking an ambient atmosphere of the chamber (Wang discloses placing the device into the heating chamber, performing these heating processes together, and once the heating processes are completed, removing the device from the chamber for further processing, thus the processes are performed without breaking an ambient atmosphere of the chamber until the heating processes are complete).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Wang into the teachings of Too to perform the first and second heating processes in the same process chamber without breaking an ambient atmosphere of the chamber. All of the claimed elements were known in the prior art before the effective filing date of the present invention, and the combination would result in a predictable result to one having ordinary skill in the art of reducing manufacturing times by performing the heating processes in the same chamber, thereby eliminating the need to physically transfer the device into different process apparatuses. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 10, 18, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899