Prosecution Insights
Last updated: August 17, 2026
Application No. 17/891,923

INTEGRATED DIPOLE REGION FOR TRANSISTOR

Non-Final OA §103§112
Filed
Aug 19, 2022
Examiner
WILCZEWSKI, MARY A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 835 resolved
+16.9% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
39 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
44.2%
+4.2% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 835 resolved cases

Office Action

§103 §112
DETAILED ACTION This Office action is in response to the Request for Continued Examination (RCE) filed on 22 April 2026. Claims 1-20 are pending in the application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered. Allowable Subject Matter The indicated allowability of claim 8 is withdrawn in view of the newly discovered references to Troyan, US 2017/0069839 and Higa, US 4,496,994. Rejections based on the newly cited reference(s) follow. Claim Rejections - 35 USC § 112 In light of Applicant’s Amendment, the rejection of claims 1-13 under 35 U.S.C. 112(b) has been withdrawn. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, of record, in view of Bao et al., US 2023/0134180, newly cited. With respect to claim 14, Chu et al. disclose a p-type field effect transistor (p-FET), see paragraphs [0009], [0014], and [0017] (“[0017] Each of the transistors 200A-200D further includes a pair of source/drain features 260. For n-type transistors, the source/drain features 260 are of n-type. For p-type transistors, the source/drain features 260 are of p-type.“), shown in Figs. 4A and 10A, comprising: an interfacial layer 280 on a top surface of a channel 215 located between a source and a drain 260 on the substrate 202, see Figs. 2B, 2C, and 3 and paragraph [0024]; a high-k dielectric layer 282 on the interfacial layer 280, see Fig. 3 and paragraph [0024]; a dipole layer 410 on the high-k dielectric layer 282, the dipole layer 410 comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te), see Fig. 4A and paragraphs [0025]-[0026]; and optionally, a capping layer 290 on the dipole layer 410, as shown in Fig. 4B In paragraph [0026], Chu et al. disclose the dipole layer 410 can be an oxide or a nitride, with one or more dipole elements. Chu et al. further disclose that in some embodiments, the dipole elements can be lanthanum (La), yttrium (Y), strontium (Sr), aluminum (Al), titanium (Ti), niobium (Nb), erbium (Er), scandium (Sc), or other suitable chemical elements. Bao et al. disclose using dipoles to adjust the threshold voltage of transistors, see Fig. 2 and paragraphs In paragraphs [0019] and [0020]. Bao et al. disclose a dipole element, such as, lanthanum, yttrium, magnesium, or gadolinium, shifts the threshold voltage toward the conduction band, thereby decreasing the threshold voltage of N-type transistors but increasing the threshold voltage of p-type transistors. Therefore, in light of this teaching of Bao et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that yttrium could have been used in the dipole layer 410 of Chu et al., if it is desired to increase the threshold voltage of the p-type transistors in the known device of Chu et al. It is within the purview of the skilled artisan to recognize in the device of Chu et al. that strontium, yttrium, and lanthanum are n-dipole elements, which would increase the threshold voltage of a p-type transistor, and aluminum, titanium, niobium, or scandium are p-dipole elements, which would decrease the threshold voltage of a p-type transistor. Therefore, the dipole element in the known method of Chu et al. would be chosen based on the desire to increase or decrease the threshold voltage of the p-type field effect transistor. With respect to claim 15, in the electronic device of Chu et al., the interfacial layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics, see paragraph [0024]. With respect to claim 16, in the p-FET of Chu et al., the interfacial layer has a thickness in a range of from 0.2 nm to 0.8 nm, see paragraph [0024]: “the interfacial layer 280 has a thickness of about 0.5 nm to about 3 nm”. With respect to claim 17, in the p-FET of Chu et al., the high-k dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx), see paragraph [0024]. With respect to claim 18, in the p-FET of Chu et al., the high-k dielectric layer has a thickness in a range of from 1 nm to 2 nm, see paragraph [0024]: “the high-k dielectric layer 282 has a thickness of about 1 nm to about 3 nm”. With respect to claim 19, in the p=FET of Chu et al., the dipole layer 410 has a thickness in a range of from 0.3 nm to 1.5 nm, see paragraph [0026]: “the dipole layer 410 is deposited to a substantially uniform thickness about 0.5 nm or less to about 1 nm”. With respect to claim 20, the p-FET of Chu et al. comprises a capping layer 430 (shown in Fig. 8B) and the capping layer has a thickness in a range of from 0.5 nm to 2 nm, see paragraph [0037]: “layer 430 has a thickness of about 2 nm to about 5 nm”. Claims 1-5, 9-10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, in view of Puurunen, both of record, further in view of Bao et al., US 2023/0134180, newly cited.. With respect to claim 1, Chu et al. disclose a method of manufacturing a p-type field effect transistor (p-FET), see paragraphs [0009], [0014], and [0017] (“[0017] Each of the transistors 200A-200D further includes a pair of source/drain features 260. For n-type transistors, the source/drain features 260 are of n-type. For p-type transistors, the source/drain features 260 are of p-type.“), the method comprising: depositing an interfacial layer 280 on a top surface of a channel 215 located between a source and a drain 260 on a substrate 202, see Figs. 2B, 2C, and 3 and paragraph [0024]; depositing a high-k dielectric layer 282 on the interfacial layer 280, see Fig. 3 and paragraph [0024]; depositing a dipole layer 410 on the high-k dielectric layer 282 by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant, the metal precursor comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te), see Fig. 4A and paragraphs [0025]-[0026] (Paragraph [0026]: “ the dipole layer 410 may include an oxide or a nitride of the dipole elements. For example, the dipole layer 410 may include La.sub.2O.sub.3, Y.sub.2O.sub.3, SrO, LaN, YN, Sr.sub.3N.sub.2”. Since Chu et al. disclose yttrium and strontium, Chu et al. disclose a p-dipole layer.); and annealing the substrate 202 at a temperature of less than or equal to 1050 *C to drive atoms from the dipole layer into the high-K dielectric layer, see paragraph [0035]. In paragraph [0026], Chu et al. disclose the dipole layer 410 can be an oxide or a nitride, with one or more dipole elements. Chu et al. further disclose that in some embodiments, the dipole elements can be lanthanum (La), yttrium (Y), strontium (Sr), aluminum (Al), titanium (Ti), niobium (Nb), erbium (Er), scandium (Sc), or other suitable chemical elements. Bao et al. disclose using dipoles to adjust the threshold voltage of transistors, see Fig. 2 and paragraphs In paragraphs [0019] and [0020]. Bao et al. disclose a dipole element, such as, lanthanum, yttrium, magnesium, or gadolinium, shifts the threshold voltage toward the conduction band, thereby decreasing the threshold voltage of N-type transistors but increasing the threshold voltage of p-type transistors. Therefore, in light of this teaching of Bao et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that yttrium could have been used in the dipole layer 410 of Chu et al., if it is desired to increase the threshold voltage of the p-type transistors in the known device of Chu et al. It is within the purview of the skilled artisan to recognize in the device of Chu et al. that strontium, yttrium, and lanthanum are n-dipole elements, which would increase the threshold voltage of a p-type transistor, and aluminum, titanium, niobium, or scandium are p-dipole elements, which would decrease the threshold voltage of a p-type transistor. Therefore, the dipole element in the known method of Chu et al. would be chosen based on the desire to increase or decrease the threshold voltage of the p-type field effect transistor. Although Chu et al. disclose YN or SrN2 as the dipole material 410 and that the dipole material is deposited by ALD, Chu et al. do not specifically disclose that the dipole layer 410 is deposited by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant, the metal precursor comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te). However, this is the actual definition of ALD, see section IIA of Puurunen, “Basic Characteristics of ALD”. Puurunen disclose a reaction cycle in Fig. 2, and further disclose that this reaction cycle is repeated until the desired amount of material has been deposited. Puurunen also discloses that metal nitrides can be deposited from a metal precursor and a nitrogen-containing precursor, such as NH3 or N2/NH3, see the top of the second column on page 121301-4 of the Puurunen article. Since Chu et al. disclose YN and SrN2 as dipole materials, it would have been obvious to the skilled artisan that alternating cycles of a metal precursor (Y or Sr) and a nitrogen-containing reactant (NH3 or N2/NH3) would be in the ALD of Chu et al. With respect to claim 2, in the method of Chu et al., the interfacial layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx),doped silicon, doped silicon oxide, or spin-on dielectrics, see paragraph [0024]. With respect to claim 3, in the method of Chu et al., the high-k dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx), see paragraph [0024]. With respect to claims 4 and 5, Chu et al. discloses YN or SrN2, however, Chu et al. does not disclose the specific metal precursors recited in dependent claims 4 and 5.. However, Puurunen discloses that reactants used in ALD are either inorganic or metalorganic, and the organometallic reactants can include cyclopentadienyls and amidinate, see section. ALD processes, 2. Classes of metal reactants used. Therefore, in light of the disclosure of Puurunen, it would have been obvious that the metal precursor used in the ALD of YN or SrN2 could comprise one or more of strontium imidazole, strontium amidinate, strontium bisamidinate, strontium cyclopentadienyl, or Bis(tri-isopropylcyclopentadienyl) strontium, or one of yttrium formamidinate, Tris(N,N'-di-i-propylformamidinato) yttrium (III), yttrium triscyclopentadienyl, tris(butylcyclopentadienyl) yttrium, tris(methlycyclopentadienyl) yttrium, or tris(n-propylcyclopentadienyl) yttrium. With respect to claim 9, in the method of Chu et al. in view of Puurunen, Chu et al. disclose YN and SrN2 as dipole materials, and Puurunen discloses that metal nitrides can be deposited from a metal precursor and a nitrogen-containing precursor, such as NH3 or N2/NH3, see the top of the second column on page 121301-4 of the Puurunen article. Therefore, it would have been obvious to the skilled artisan that the metal precursor comprises one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb) and the nitrogen-containing reactant comprises one or more of nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or a co-flow of nitrogen radicals (N2*) and hydrogen radicals (H2*). With respect to claim 10, Chu et al. teach the p-dipole layer 410 is deposited on the high-k dielectric layer 282 by atomic layer deposition (ALD), see paragraph [0026]. Chu et al. do not disclose the temperature and pressure at which the ALD is performed. However, these processing parameters would have been obvious in light of the disclosure of Puurunen and ascertainable through routine experimentation. Requiring the atomic layer deposition (ALD) deposition of p-dipole layer 410 at a temperature of less than or equal to 500 *C and at a pressure of less than or equal to 50 Torr is not deemed to patentably distinguish Applicant’s claimed method from that of Chu et al.. With respect to claim 12, the method of Chu et al. further comprises depositing a capping layer 430 on the p-dipole layer 410, see Fig. 8B and paragraph [0037]. With respect to claim 13, in the method of Chu et al., the capping layer 430 comprises one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide, see paragraph [0037]. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, in view of Puurunen, further in view of Bao et al., US 2023/0134180, as applied to claim 1 above, further in view of Guha et al., US 2009/0302370, of record. Chu et al., Puurunen, and Bao et al.are applied as above. Although Chu et al. teach that dipole layer 410 can comprise strontium and yttrium, Chu et al. lack anticipation of the dipole layer 410 comprising ytterbium (Yb). However, in the same field of endeavor, that is, a method for modulating the threshold voltage of a transistor, Guha et al. disclose that the dipole material can comprise a metal nitride, and specifically discloses ytterbium, see paragraphs [0015], [0028]-[0030] and Table I. In light of the disclosure of Guha et al., it would have been obvious that a metal nitride dipole layer comprising ytterbium could have been used in the known method of Chu et al. Puurunen discloses that metal nitrides can be deposited from a metal precursor and a nitrogen-containing precursor, such as NH3 or N2/NH3, see the top of the second column on page 121301-4 of the Puurunen article. Puurunen also discloses that reactants used in ALD are either inorganic or metalorganic, and the organometallic reactants can include cyclopentadienyls and amidinate, see section. ALD processes, 2. Classes of metal reactants used. Therefore, in light of the disclosure of Puurunen, it would have been obvious to the skilled artisan that the metal precursor used in the known method of Chu et al. could comprise one or more of ytterbium formamidinate, Tris(N,N'-di-i-propylformamidinato) ytterbium(III) or ytterbium cyclopentadienyl. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, in view of Puurunen, further in view of Bao et al., US 2023/0134180, as applied to claim 1 above, further in view of Li et al., CN 105826188, of record. Chu et al., Puurunen, and Bao et al. are applied as above. Although Chu et al. teach that dipole layer 410 can comprise strontium and yttrium, Chu et al. lack anticipation of the dipole layer 410 comprising antimony (Sb). However, Li et al. disclose that a dipole layer can comprise antimony. In light of this disclosure, it would have been obvious to the skilled artisan that the dipole layer 410 of Chu et al. could comprise antimony. Chu et al. disclose that the dipole layer can be a metal nitride. Puurunen disclose that antimony pentachloride can be used as a metal precursor in the ALD of antimony-containing layers, see page 121301-14 of the Puurunen article. Therefore, in light of these references, it would have been obvious to the skilled artisan that the dipole of Chu et al. could comprise antimony nitride deposited by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant, the metal precursor comprising antimony (Sb) and the metal precursor comprising one or more of antimony trichlor antimony pentachloride, or antimony tris(trimethylsilane). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, in view of Puurunen, as applied to claim 1 above, further in view of Martin, Chapter 3:Surface Preparation for Film and Coating Deposition Processes, PP 93-134, all of record. Chu et al. and Puurunen are applied as above. Chu et al. lack anticipation of performing a radical treatment to remove carbide, nitride, or oxide from the dipole layer. However, in light of the disclosure of Martin, it would have been obvious to the skilled artisan to perform a radical treatment to remove carbide, nitride, or oxide from the dipole layer by using a plasma, thereby cleaning the surface of the dipole layer 410 to remove contaminants and to achieve optimal bonding of the capping layer 430. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al., US 2021/0366783, in view of Puurunen, further in view of Bao et al., US 2023/0134180, as applied to claim 1 above, further in view of Troyan, US 2017/0069839 and Higa, US 4,946,994, both newly cited. Chu et al., Puurunen, and Bao et al. are applied as above. Neither Chu et al, Puurunen, nor Bao et al. disclose a dipole layer comprising tellurium. However, it is taught by Troyan that Te films can increase dipole concentration in dielectric layers, see paragraph [0122]. Higa discloses ditertiarybutyltelluride is one of the best tellurium source compounds, see Summary of the Invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that ditertiarybutyltelluride could have been used as the metal precursor in depositing the dipole layer in the known method of Chu et al. Response to Arguments Applicant's arguments filed 16 April 2026 have been fully considered but they are not persuasive. Applicant has argued that Chu does not disclose a p-FET according to amended claim 14, having a dipole layer comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te). Applicant further argues that Chu does not disclose, teach, or suggest using a metal precursor comprising strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te) to deposit a dipole layer for a p-type transistor. In paragraph [0026], Chu et al. disclose the dipole layer 410 can be an oxide or a nitride, with one or more dipole elements. Chu et al. further disclose that in some embodiments, the dipole elements can be lanthanum (La), yttrium (Y), strontium (Sr), aluminum (Al), titanium (Ti), niobium (Nb), erbium (Er), scandium (Sc), or other suitable chemical elements. Bao et al. disclose using dipoles to adjust the threshold voltage of transistors, see Fig. 2 and paragraphs In paragraphs [0019] and [0020]. Bao et al. disclose a dipole element, such as, lanthanum, yttrium, magnesium, or gadolinium, shifts the threshold voltage toward the conduction band, thereby decreasing the threshold voltage of N-type transistors but increasing the threshold voltage of p-type transistors. Therefore, in light of this teaching of Bao et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that yttrium could have been used in the dipole layer 410 of Chu et al., if it is desired to increase the threshold voltage of the p-type transistors in the known device of Chu et al. It is within the purview of the skilled artisan to recognize in the device of Chu et al. that strontium, yttrium, and lanthanum are n-dipole elements, which would increase the threshold voltage of a p-type transistor, and aluminum, titanium, niobium, or scandium are p-dipole elements, which would decrease the threshold voltage of a p-type transistor. Therefore, the dipole element in the known method of Chu et al. would be chosen based on the desire to increase or decrease the threshold voltage of the p-type field effect transistor, and choice of the appropriate metal is well within the purview of the skilled artisan. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose transistors having dipole layers and methods for their fabrication.. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Aug 19, 2022
Application Filed
Aug 19, 2025
Non-Final Rejection mailed — §103, §112
Nov 07, 2025
Response Filed
Feb 17, 2026
Final Rejection mailed — §103, §112
Apr 16, 2026
Response after Non-Final Action
Apr 22, 2026
Request for Continued Examination
May 04, 2026
Response after Non-Final Action
Jul 08, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.1%)
2y 7m (~0m remaining)
Median Time to Grant
High
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