Prosecution Insights
Last updated: May 29, 2026
Application No. 17/892,344

SEMICONDUCTOR PACKAGE AND METHOD

Non-Final OA §103
Filed
Aug 22, 2022
Examiner
KOLB, THADDEUS J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
22 granted / 26 resolved
+16.6% vs TC avg
Strong +24% interview lift
Without
With
+23.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
19 currently pending
Career history
69
Total Applications
across all art units

Statute-Specific Performance

§103
84.1%
+44.1% vs TC avg
§102
6.5%
-33.5% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 26 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see remarks, filed 09/03/2025, with respect to the rejection(s) of claim(s) 1-15 and 21-25 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen (US-12199025-B2) in view of Chen et al. (US-20210020602-A1 – hereinafter Chen), and further in view of Duong et al. (US-20230420373-A1 – hereinafter Duong). Regarding claim 1, Shen teaches a method (Fig.13-19; col 11 line 64-66) comprising: forming a first redistribution structure (Fig.2 100; col 6 line 38-41) over a carrier (Fig.13 400; col 12 line 1-5), wherein forming the first redistribution structure (100) comprises: forming a plurality of first organic (col 5 line 50-55) polymer layers (Fig.14 112; col 12 line 15-20) over the carrier (400); and forming a plurality of first conductive lines (Fig.14 114; col 12 line 15-25) in the plurality of first organic polymer layers (112); attaching a first package structure (Fig.20-23; col 13 line 24-30) to the first redistribution structure (100), the first package structure comprising: a first semiconductor die (Fig.2 D1; col 7 line 18-25); a molding material (Fig.2 216; col 8 line 20-25) that surrounds an entirety of a perimeter of the first semiconductor die (D1) in a top-down view; and dispensing a first underfill (Fig.2 205 top section; col 8 line 4-10) into a first gap between the plurality of first conductive lines (114) and the first package structure (D1); bonding a substrate (Fig.2 204; col 7 line 14-20) to the first redistribution structure (100) using first conductive connectors (Fig.2 206; col 8 line 8), the substrate (204) being bonded to an opposing side of the first redistribution structure (100) as the first package structure (D1); and dispensing a second underfill (Fig.2 205 bottom section; col 8 line 4-10) into a second gap between the substrate (204) and the first redistribution structure (100). Shen does not explicitly teach a second redistribution structure on bottom surfaces of the first semiconductor die and the molding material. However, this feature is well-known in the art at the time of filing. Chen teaches a die (Fig.1E SC2; ¶0023 of Chen) having a redistribution structure (Fig.1E 202; ¶0023 of Chen). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a redistribution structure for only an individual die (202 of Chen), as taught by Chen on the die of Shen (D1 of Shen). A practitioner would be motivated to make this modification for a configuration where the attached chip (D1 of Shen) needs its signals redistributed. This is a well-established practice in the art and any practitioner could employ this to suit the respective device application. Shen in view of Chen does not teach wherein a first portion of the molding material that is disposed on a first sidewall of the first semiconductor die has a first width, wherein a second portion of the molding material that is disposed on a second sidewall of the first semiconductor die has a second width, and wherein the first width is substantially equal to the second width. Duong teaches a molding material (Fig.2A 141; ¶0040 of Duong) surrounding a die (Fig.2A 114; ¶0040 of Duong) where the thickness of the molding material is the same thickness around the die (Fig.2A of Duong). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the thickness of the molding material (216 of Shen) around the dies (Dn of Shen) of name to be uniform (141 of Duong) as taught by Duong to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of uniform protective material around the individual dies. Regarding claim 2, the aforementioned combination of Shen in view of Chen, and further in view of Duong from claim 1 teaches the method of claim 1, wherein the second redistribution structure comprises: a second organic polymer layer (Fig.1E 202; ¶0023 of Chen) on the bottom surfaces of the first semiconductor die (D1 of Shen) and the molding material (216 of Shen); and a second conductive line (Fig.1E 202-LM and 202-TM of Chen) in the second organic polymer layer (202 of Chen). Regarding claim 3, the aforementioned combination of Shen in view of Chen, and further in view of Duong from claim 2 teaches the method of claim 2, wherein the plurality of first organic polymer layers and the second organic polymer layer comprise polybenzoxazole (PBO), polyimide or benzocyclobutene (BCB) (the organic layers comprise polyimide; col 5 line 55-56 of Shen). Regarding claim 4, the aforementioned combination of Shen in view of Chen, and further in view of Duong from claim 2 teaches the method of claim 2. The aforementioned combination does not explicitly teach wherein the second redistribution structure comprises a thickness that is in a range from 2 μm to 50 μm. However, it would have been obvious to form the redistribution structure within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 5, the aforementioned combination of Shen in view of Chen, and further in view of Duong from claim 1 teaches the method of claim 1, wherein the plurality of first conductive lines (114 of Shen) comprises at least four redistribution layers (four redistribution layers can be seen in Fig.2 of Shen) in the plurality of first organic polymer layers (112 of Shen). Regarding claim 6, the aforementioned combination of Shen in view of Chen from claim 1 teaches the method of claim 1. The aforementioned combination does not explicitly teach wherein the first width and the second width are in a range from 10 μm to 500 μm. However, it would have been obvious to form the molding material within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 7, the aforementioned combination of Shen in view of Chen, and further in view of Duong from claim 1 teaches the method of claim 1 further comprising adhering a stiffener ring (Fig.2 218; col 8 line 33-40 of Shen) on the substrate (204 of Shen), wherein the stiffener ring (218 of Shen) encircles the first redistribution structure (100 of Shen) in a top view. Claim(s) 8 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Lai et al. (US-20210233835-A1 – hereinafter Lai). Regarding claim 8, Shen teaches a package structure (Fig.2 of Shen) having a second redistribution structure (Fig.2 100; col 6 line 38-41), a first package component (Fig.2 D1; col 7 line 18-25 of Shen) and a second package component (Fig.2 Dn; col 7 line 60-67 of Shen); and after (Col 13 line 33-34) coupling the first package component (D1) and the second package component (Dn) to the second redistribution structure (100), dispensing an underfill (Fig.2 205; col 8 line 4-10) into a second gap between the first package component (D1) and the second package component (Dn), and into a third gap between the first package component (D1) and the second redistribution structure (100), wherein the underfill (205) is disposed above a bottommost surface of the second redistribution structure (100). Shen does not explicitly teach a method comprising: attaching a first die and a second die to a carrier substrate; forming a molding material to fill in a gap between adjacent sidewalls of the first die and the second die, wherein the molding material surrounds an entirety of a perimeter of each of the first die and the second die; forming a first redistribution structure over top surfaces of the first die, the second die and the molding material; detaching the carrier substrate from the first redistribution structure; performing a singulation process to form a first package component and a second package component, the first package component comprising the first die, and the second package component comprising the second die, wherein after the singulation process a first width of the molding material that surrounds and is in physical contact with the entirety of the perimeter of each of the first die and the second die is in a range from 10 μm to 500 μm. Lai teaches a method comprising: attaching a first die (Fig.3 left 50; ¶0025 of Lai) and a second die (Fig.3 right 50; ¶0025 of Lai) to a carrier substrate (Fig.3 106; ¶0024 of Lai); forming a molding material (Fig.4 110; ¶0026 of Lai) to fill in a gap between adjacent sidewalls of the first die (left 50 of Lai) and the second die (right 50 of Lai), wherein the molding material (110 of Lai) surrounds an entirety of a perimeter of each of the first die (left 50 of Lai) and the second die (right 50 of Lai); forming a first redistribution structure (Fig.5 112; ¶0027 of Lai) over top surfaces of the first die (left 50 of Lai), the second die (right 50 of Lai) and the molding material (110 of Lai); detaching (Fig.8; ¶0041 of Lai) the carrier substrate (106 of Lai) from the first redistribution structure (112 of Lai); performing a singulation process (¶0003 of Lai discloses a singulation process as an option) to form a first package component and a second package component, the first package component comprising the first die (left 50 of Lai), and the second package component comprising the second die (right 50 of Lai), wherein after the singulation process a first width of the molding material (110 of Lai) that surrounds and is in physical contact with the entirety of the perimeter of each of the first die (left 50 of Lai) and the second die (right 50 of Lai) is in a range from 10 μm to 500 μm (singulation would result in this limitation being met). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the method taught by Lai to produce the first package component (D1 of Shen) and second package component (Dn of Shen) to arrive at the claimed invention. A practitioner would be motivated to use this method because it is one of many reasonable options a practitioner of ordinary skill would find useful to fabricate the dies (D1 and Dn of Shen) in the process taught by Shen. Additionally, Shen explicitly teaches that both dies (D1 and Dn of Shen) can be fabricated using techniques well known to those skilled in the art (col 7 line 1-5). Regarding claim 11, the aforementioned combination of Shen in view of Lai from claim 8 teaches the method of claim 8. The aforementioned combination does not explicitly teach wherein the first redistribution structure has a thickness that is in a range from 2 μm to 50 μm. However, it would have been obvious to form the first redistribution structure within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 12, the aforementioned combination of Shen in view of Lai from claim 8 teaches the method of claim 8, wherein the first redistribution structure (110 of Lai) and the second redistribution structure (100 of Shen) comprise organic polymers (col 5 line 50-55 of Shen). Regarding claim 13, the aforementioned combination of Shen in view of Lai from claim 12 teaches the method of claim 12, wherein the second redistribution structure (110 of Shen) comprises at least four redistribution layers (Fig.2 114; col 12 line 15-20 of Shen). Regarding claim 14, the aforementioned combination of Shen in view of Lai from claim 8 teaches the method of claim 8, wherein each of the first package component (D1 of Shen) and the second package component (Dn of Shen) comprise a first sidewall having a second width (a side of D1 in one direction) and a second sidewall having a third width (a second side of D1 in the other direction), wherein the second width is larger than the third width, wherein a fourth width of the second redistribution structure (100 of Shen) is larger than the second width (long sides of D1 and Dn), and wherein after coupling the first package component (D1 of Shen) and the second package component (Dn of Shen) to the second redistribution structure (100 of Shen) the first package component and the second package component are disposed such that the second sidewall of the first package component is adjacent to the second sidewall of the second package component (short sides of D1 and Dn are adjacent in Fig.2). Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Lai, and further in view of Chen et al. (US-11088086-B2 – hereinafter Shih). Regarding claim 9, the aforementioned combination of Shen in view of Lai from claim 8 teaches the method of claim 8. The aforementioned combination does not teach wherein after dispensing the underfill, a top surface of the underfill is level with a top surface of the first die and a top surface of the molding material that surrounds the first die. Shih teaches chips (Fig.1A 130; col 6 line 5-13 of Shih) and an underfill portion (Fig.1A 152; col 6 line 5-13 of Shih) where the top surface of the chips (130 of Shih) are level with the top surface of the underfill (152 of Shih). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the underfill configuration of Shih (152 of Shih) to the prior art combination of Shen in view of Lai to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of allowing adequate heat dissipation off the tops of the dies. Regarding claim 10, the aforementioned combination of Shen in view of Lai, and further in view of Shih from claim 9 teaches the method of claim 9, wherein the molding (Primary reference Shen also teaches a molding material 216 having all of the required characteristics of the molding material 110 of Lai to effectively teach the claimed subject matter) material (Fig.2 216; col 8 line 20-25 of Shen) comprises first filler particles in a first base material (col 8 line 4-20 of Shen), wherein the underfill comprises second filler particles in a second base material (col 8 line 4-20 of Shen), and wherein the first base material is different from the second base material (the molding material can comprise silica and the underfill material can comprise an epoxy polymer and filler). Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Lai, and further in view of Lin et al. (US-10790158-B2 – hereinafter Lin) Regarding claim 15, the aforementioned combination of Shen in view of Lai from claim 14 teaches the method of claim 14. Additionally, with the second package component of Shen being labeled as Dn instead of D2 (col 7 line 1 of Shen), this suggests more dies may be added to the method of Shen in view of Lai. The aforementioned combination does not teach coupling a third die and a fourth die to the second redistribution structure, wherein the third die and the fourth die are adjacent to the first sidewall of the first package component; and coupling a fifth die and a sixth die to the second redistribution structure, wherein the fifth die and the sixth die are adjacent to the first sidewall of the second package component. Lin teaches a multi-die device comprising dies of a variety of sizes (Fig.1 of Lin). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a third through sixth die to the structure of Lai in view of Lin having a smaller size (depicted in Fig.1 of Lin) to arrive at the claimed invention. A practitioner would be motivated to make this modification to meet the requirements of different device applications where at least 6 dies are required. Simply adding more IC die components is does not patentably distinguish claim 15 over claim 14 when the primary reference suggests the presence of additional dies and the teaching reference depicts at least 6 IC dies. Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Newlin (US-20220351901-A1 – hereinafter Newlin), and further in view of Chen, and further in view of Duong. Regarding claim 21, Shen teaches a method comprising: forming (Fig.13-19; col 11 line 64-66) a first redistribution structure (Fig.2 100; col 6 line 38-41) over a carrier (Fig.13 400; col 12 line 1-5), wherein the first redistribution structure (100) comprises: a plurality of first insulating layers (Fig.14 112; col 12 line 15-20) over the carrier (400); and a plurality of first conductive lines (Fig.14 114; col 12 line 15-25) in the plurality of first insulating layers (112); attaching a first package structure (Fig.20-23; col 13 line 24-30) and a first semiconductor die (Fig.2 D1; col 7 line 18-25) to a first side of the first redistribution structure (100) using first conductive connectors (Fig.2 210; col 7 line 60-67), wherein the first package structure (Fig.20-23) comprises: a second semiconductor die (Fig.2 Dn; col 7 line 10-25); and encapsulating each of the first package structure (Fig.20-23) and the first semiconductor die (D1) with an encapsulant (Fig.2 216; col 8 line 20-25); and bonding a substrate (Fig.2 205; col 8 line 4-10) to a second side of the first redistribution structure (100) using second conductive connectors (Fig.2 206; col 8 line 8), wherein the first side of the first redistribution structure (100) and the second side of the first redistribution structure (100) are opposite sides of the first redistribution structure (100). Shen does not teach the second semiconductor die having a molding material disposed on sidewalls of the second semiconductor die. Newlin teaches a chip package (Fig.6; ¶0021 of Newlin) having a chip (Fig.6 41; ¶0021) encapsulated by a mold (Fig.6 61; ¶0021). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to individually encapsulate the second semiconductor die (Dn of Shen) with the mold of Newlin (61 of Newlin) to arrive at the claimed invention. A practitioner would be motivated to make this modification for the benefit of protecting the second semiconductor die (Dn of Newlin) from the outside environment (¶0021 of Newlin). Shen in view of Newlin does not teach a second redistribution structure disposed below the second semiconductor die and the molding material, the second redistribution structure being electrically connected to the second semiconductor die. Chen teaches a die (Fig.1E SC2; ¶0023 of Chen) having a redistribution structure (Fig.1E 202; ¶0023 of Chen). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a redistribution structure for only an individual die (202 of Chen), as taught by Chen on the second semiconductor die of Shen (Dn of Shen). A practitioner would be motivated to make this modification for a configuration where the attached die (Dn of Shen) needs its signals redistributed. This is a well-established practice in the art and any practitioner could employ this to suit the respective device application. Shen in view of Newlin, and further in view of Chen does not teach wherein a height of the molding material is equal to a height of the second semiconductor die, and wherein a topmost surface of the second semiconductor die is level with a topmost surface of the molding material. Duong teaches a molding material (Fig.2A 141; ¶0040 of Duong) surrounding a die (Fig.2A 114; ¶0040 of Duong) where the top surface of the die (114 of Duong) is level with the top surface of the molding material (141 of Duong). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the molding material configuration of Duong (141 of Duong) to the prior art combination of Shen in view of Newlin, and further in view of Chen to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of allowing adequate heat dissipation off the tops of the dies. Regarding claim 22, the aforementioned combination of Shen in view of Newlin, and further in view of Chen, and further in view of Duong from claim 21 teaches the method of claim 21, wherein the plurality of first insulating layers (112 of Shen) comprise an organic polymer (col 5 line 50-55 of Shen). Regarding claim 23, the aforementioned combination of Shen in view of Newlin, and further in view of Chen, and further in view of Duong from claim 22 teaches the method of claim 22, wherein the organic polymer comprises polybenzoxazole (PBO), polyimide or benzocyclobutene (BCB) (the organic layers comprise polyimide; col 5 line 55-56 of Shen). Regarding claim 24, the aforementioned combination of Shen in view of Newlin, and further in view of Chen, and further in view of Duong from claim 21 teaches the method of claim 21 further comprising adhering a stiffener ring (Fig.2 218; col 8 line 33-40 of Shen) on the substrate (205 of Shen), wherein the stiffener ring (218 of Shen) encircles the first redistribution structure (100 of Shen) in a top view. Regarding claim 25, the aforementioned combination of Shen in view of Newlin, and further in view of Chen, and further in view of Duong from claim 21 teaches the method of claim 21. The aforementioned combination does not explicitly teach wherein a width of a first portion of the molding material that is disposed on a first sidewall of the second semiconductor die is in a range from 10 μm to 500 μm. However, it would have been obvious to form the molding material within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.J.K./ Examiner, Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Aug 22, 2022
Application Filed
Jun 04, 2025
Non-Final Rejection mailed — §103
Sep 03, 2025
Response Filed
Oct 16, 2025
Final Rejection mailed — §103
Dec 16, 2025
Response after Non-Final Action
Jan 07, 2026
Request for Continued Examination
Jan 26, 2026
Response after Non-Final Action
May 26, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+23.5%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
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