DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant’s election without traverse of Invention 1 corresponding to claims 17-20 in the reply filed on 03/25/2025 is acknowledged. Claims 1-16 were canceled and claims 21-36 were newly added in the reply.
In response to Applicant’s amendments in the reply on 03/25/2025, the Examiner required a further species restriction, which was mailed on 05/05/2025.
Applicant’s election without traverse of Species 1 (FIGS. 4, 5A-11A and 5B-11B) corresponding to claims 17-22, 24-34 and 36-38 in the reply filed on 06/02/2025 is acknowledged. Claims 17, 21, 30, 34, and 36 were amended, claims 23 and 35 were canceled, and claims 37-38 were new newly added in the reply. Claims 1-16 remain cancelled. No claims are withdrawn.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following elements mentioned in the description: “source/drain features” FIGS. 3B and 3D. The specification states in [0029]: “FIG. 3B depicts a top, plan view of source/drain features…FIG 3D depicts a top, plan view of source/drain features…”. However, neither FIG. 3B nor FIG. 3D depict “source/drain features”.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following limitations must be shown or the feature(s) canceled from the claim(s):
1) In claim 21, lines 7-10: “wherein the first gate structure is disposed over the first active region and the second active region, wherein the second gate structure is disposed over the first active region and the second active region” must be shown. Assuming the claimed first and second gate structures correspond to 130A and 130D (since those are the only two gate structures which both intersect two separate active regions 108 in FIGS. 3A-3D), none of the figures show the bolded portion of the claim limitation above. The cross-sectional views of FIGS. 5A-11B show gate structures 130D and 130A disposed over a first active region 108, but not a second active region 108.
2) In claim 22, lines 3-6: “wherein the second active region comprises a second source/drain feature, and the method further comprises: forming a second trench exposing a bottom surface of the first gate structure and a bottom surface of the second source/drain feature” must be shown. The source/drain features 114N shown in the cross sections of FIGS. 5A-11B cannot correspond to the claimed “second source/drain feature”, since they are source/drain features for active regions 106 and not 108. Additionally, the trench 514a shown in FIG. 8A cannot correspond to the claimed “second trench” because it does not expose a bottom surface of a gate structure, nor does it expose a bottom surface of a source/drain feature of active region 108.
3) In claim 28, lines 4-5: “a center line of the source/drain contact is offset from a center line of the conductive feature” should be shown in FIGS 10B, 11B, 12B and 17B.
4) In claim 30, line 5: “a second source/drain feature”, line 7: “..second source/drain feature are disposed between the first and second gate structures”, line 10: “forming a second source/drain contact over and electrically coupled to the second source/drain feature”, and lines 15-16: “forming a second conductive feature under and electrically coupled to the second source/drain feature and the first gate structure” must be shown. The source/drain feature 114N shown in the cross sections of FIGS. 5A-11B cannot correspond to the claimed “second source/drain feature”, since there is not a conductive feature “under and electrically coupled to the second source/drain feature and the first gate structure” in these figures as required by lines 15-16 of the claim. The conductive feature 334 in FIGS. 10A and 11A cannot correspond to the claimed “second conductive feature” because it is not electrically coupled to both the second source/drain feature and the first gate structure. The claimed second conductive feature appears to refer to butted contact 326, but 326 is not shown in any figure as being under a second source/drain feature and first gate structure.
5) In claim 32, lines 4-5: “forming a second silicide layer between the second conductive feature and the second source/drain feature” must be shown. The source/drain feature 114N shown in the cross sections of FIGS. 5A-11B cannot correspond to the claimed “second source/drain feature” as described above, so silicide layer 518a cannot correspond to the claimed second silicide layer.
6) In claim 33, line 3: “a second dielectric liner” must be shown. Since the conductive feature 334 in FIGS. 10A and 11A cannot correspond to the claimed “second conductive feature” as explained above, 516 cannot correspond to the claimed “second dielectric liner”.
7) In claim 36, lines 4-5: “forming a first power line disposed over the memory cell; and forming a second power line disposed under the memory cell” must be shown. If the claimed first and second power lines correspond to reference characters 510 and 522, respectively, of FIG. 11A, the specification does not refer to them as power lines. Reference character 510 is referred to as a MLI structure ([0049]) and 522 is referred to as a “backside power rail” ([0057]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered, and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 30 is objected to because of the following informalities: lines 6-7 recite “first and second source/drain feature are…”. It is recommended to change the quoted language to “first and second source/drain features are…” for proper subject-verb agreement. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-22, 24-34 and 36-38 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21, lines 7-10 recite: “wherein the first gate structure is disposed over the first active region and the second active region, wherein the second gate structure is disposed over the first active region and the second active region”. There is no direct support for the bolded limitations in the original disclosure filed 08/22/2022. Assuming the claimed first and second gate structures correspond to 130A and 130D (since those are the only two gate structures which both intersect two separate active regions 108 in FIGS. 3A-3D), none of the figures show the bolded portion of the claim limitation above, nor does the specification provide support for it. The cross-sectional views of FIGS. 5A-11B show gate structures 130D and 130A disposed over a first active region 108, but not disposed over a first and second active region. For purposes of examination, it is assumed gate structures 130A and 130D are disposed over both active regions 108 shown in FIG. 3A.
Claim 21, line 15 recites “forming a conductive feature in the trench…”. There is no direct support for the bolded portion of the limitation in the original disclosure filed 08/22/2022. It appears the limitation refers to reference character 328 in FIGS. 3A and 10B, which is referred to as a butted contact [0037] or a contact feature [0065]. Applicant’s cooperation in using claim terminology consistent with the specification is requested.
Claim 22, lines 4-8 recite the limitation: “wherein the method further comprises: forming a second trench exposing a bottom surface of the first gate structure and a bottom surface of the second source/drain feature; and forming a second conductive feature in the trench”. There is no direct support for the bolded limitation in the original disclosure filed 08/22/2022. The limitation appears to be directed to a method for forming the backside butted contact 326, but the specification does not provide a method for forming 326 including “forming a second trench exposing a bottom surface of the first gate structure and a bottom surface of the second source/drain feature”. Additionally, the trench 514a shown in FIG. 8A cannot correspond to the claimed “second trench” because it does not expose a bottom surface of a gate structure, nor does it expose a bottom surface of a source/drain feature of active region 108. For purposes of examination, the bolded portion of the limitation will be treated as corresponding to a source/drain feature and a trench for the active region 108 in FIG. 3C which has the backside butted contact 326.
Claim 30, line 10 recites the limitation: “forming a second source/drain contact over and electrically coupled to the second source/drain feature”. There is no direct support for the bolded limitations in the original disclosure filed 08/22/2022. The limitation appears to be directed to forming source/drain contact 314 which is electrically connected to the drain of transistor PU-1 ([0037], FIG. 3A). However, neither the specification nor the figures have explicit support for the bolded portion of the limitation.
Claim 30, lines 12 and 14 recite “forming a first conductive feature” and “forming a second conductive feature” in the trench…”. There is no direct support for the bolded portions of the limitation in the original disclosure filed 08/22/2022. It appears the limitation refers to reference characters 328 and 326 in FIG. 3, which are referred to as butted contacts [0037]. It appears reference character 328 may also be referred to as a contact feature [0065]. Applicant’s cooperation in using claim terminology consistent with the specification is requested.
Claim 30, lines 15-16 recite: “forming a second conductive feature under and electrically coupled to the second source/drain feature and the first gate structure”. There is no direct support for the bolded portion of the limitation in the original disclosure filed 08/22/2022. The claimed second conductive feature appears to refer to butted contact 326, but 326 is not shown in any figure as being under a second source/drain feature and first gate structure, nor is it described as such in the specification. For purposes of examination, the bolded portion of the limitation will be treated as a conductive feature similar to 328 (FIG. 10B, [0037]).
Claim 32, lines 4-5 recite the limitation: “forming a second silicide layer between the second conductive feature and the second source/drain feature”. There is no direct support for the bolded portion limitation in the original disclosure filed 08/22/2022. The claimed “second silicide layer” cannot correspond to 518a of FIGS. 10A and 11A because reference character 334 cannot correspond to the second conductive feature, as explained above. Silicide layers 506 (FIG. 5A, [0047]) also cannot correspond to the claimed “second silicide layer”, as it does not meet the limitations “between the second conductive feature and the second source/drain feature”. For purposes of examination, the bolded portion of the limitation will be treated as a silicide layer similar to layer 518b (FIG. 10B, [0055]) between butted contact 326 and a source/drain feature of transistor PU-1.
Claim 33, line 3 recites the limitation: “forming…a second dielectric liner providing isolation between the second conductive feature and the substrate”. There is no direct support for the bolded limitations in the original disclosure filed 08/22/2022. The claimed “second dielectric liner” cannot correspond to reference character 516 of FIG. 10A because reference character 334 cannot correspond to the second conductive feature, as explained above. For purposes of examination, the bolded portion of the limitation will be treated as a dielectric liner similar to reference character 516 (FIG. 10B, [0052]) providing insulation between butted contact 326 and the substrate 12.
Claim 36, lines 4-5 recite the limitation: “forming a first power line disposed over the memory cell; and forming a second power line disposed under the memory cell”. There is no direct support for the bolded limitations in the original disclosure filed 08/22/2022. The limitation appears to be directed to reference characters 510 and 522 of FIG. 11A, which are respectively referred to as a MLI structure ([0049]) a “backside power rail” ([0057]). For purposes of examination, the first and second power lines will be interpreted as any conductive structure capable of providing electrical power to the memory cell.
Claims 24-29 and 37 are rejected at least based on their dependency on independent claim 21, and claims 31-34, 36, and 37 are rejected at least based on their dependency on independent claim 30.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-22, 24-29 and 37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21, line 4 recites “adjacent to first channel region”. There is insufficient antecedent basis for the bolded portion of this limitation in the claim. For purposes of examination, “first channel region” will be interpreted as “the channel region”, as recited in lines 3-4 of the claim.
Claim 22, line 7 recites the limitation “forming a second conductive feature in the trench”. It is unclear which trench is being referred to, since line 2 recites “the trench is a first trench” and line 5 recites “a second trench”. For purposes of examination, the bolded limitation will be treated as “the second trench”, since the limitation appears to be directed to a trench in which contact 326 is formed, similar to, but separate than the trench 514b in which contact 328 is formed.
Claims 22, 24-29 and 37 are rejected at least based on their dependency on independent claim 21, noting dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 30, 31, 36, and 38 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie).
Regarding claim 30, Xie teaches in FIGS. 1A-8C a method, comprising:
forming a first gate-all-around transistor (320, FIG. 1B, [0028]) and a second gate-all-around transistor (310, FIG. 1A, [0028]) over a substrate (100/110, [0029]), the first gate-all-around transistor (320) comprising a first gate structure (520, FIG. 1B, 0031]) and a first source/drain feature (321/322, FIG. 1B, [0028]), and the second gate-all-around transistor (310) comprising a second gate structure (510, FIG. 1A, [0031]) and a second source/drain feature (311/312, FIG. 1A, [0028]), wherein the first and second gate structures (520 and 510) extend lengthwise along a first direction (vertical direction in inset of FIG. 1A/1B/1C), and the first and second source/drain feature (321/322 and 311/312) are disposed between the first and second gate structures (520 and 510);
forming a first source/drain contact (711, FIG. 4A, [0039]) over and electrically coupled to the first source/drain feature (311/312),
forming a second source/drain contact (721, FIG. 4B, [0039]) over and electrically coupled to the second source/drain feature (321/322), wherein the first source/drain contact (711) and the second source/drain contact (721) extend lengthwise along the first direction (vertical direction in inset of FIG. 1A/1B/1C);
forming a first conductive feature (871/852/742, FIG. 8A, [0046]/[0045]) under and electrically coupled to the first source/drain (321/322) feature and the second gate structure (510; FIGS 8A and 8C show portion 871 of contact feature 871/852/742 electrically coupled to gate structure 510 and source/drain feature 321/322 through contact 620, [0035]); and
forming a second conductive feature (851/741, FIG. 8A, [0046]) under and electrically coupled to the second source/drain feature (311/312, FIG. 8A; contact 620 electrically couples source/drain feature 211/212 to 311/312) and the first gate structure (520; cross-couple 731 in FIG. 4B, [0039], electrically couples first gate structure 520 to second source/drain feature 311/312, so second conductive feature 851/741 is electrically coupled to first gate structure 520).
Regarding claim 31, Xie teaches the method of claim 30, wherein the first conductive feature (871/852/742, FIG. 8A) is in direct contact with the second gate structure (510, FIG. 8A).
Regarding claim 36, Xie teaches the method of claim 31, wherein the first gate-all-around transistor (320) and the second gate-all-around transistor (310) are parts of a memory cell (SRAM device, [0002]/[0022]), and the method further comprises:
forming a first power line (910, FIG. 5A/5B/5C, [0041]) disposed over the memory cell (SRAM device); and
forming a second power line (930, FIG. 9A/9B/9C) disposed under the memory cell (SRAM device), wherein the first power line (910) and the second power line (930) are configured to receive different voltages (910 and 930 are separate power lines and are therefore configured to receive different voltages).
Regarding claim 38, Xie teaches the method of claim 36, wherein the first gate-all-around transistor (320) and the second gate-all-around transistor (310) are pull-up transistors of the memory cell (SRAM device; [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie).
Regarding claim 17, Xie teaches in FIGS. 4A-8C, a method, comprising:
providing a workpiece (see annotated FIGS. 4A/4B/4C) comprising:
a channel region (channel region of transistor 220, annotated FIG. 4B) over a substrate (100/110, [0029]), the channel region comprising a plurality of nanostructures ([0032]),
a source/drain feature (221, FIG. 4B, [0028]) coupled to the channel region (annotated FIG. 4B), and
a gate structure (510, FIG. 1A, [0031]) over the channel region (annotated FIGS. 4A/4B/4C);
flipping over the workpiece (11; [0041], FIG. 6A);
after the flipping over of the workpiece, forming a contact feature (871/852/742, FIG. 8A, [0046]/[0045]), wherein the contact feature (871/852/742) is electrically coupled to the source/drain feature (221) and the gate structure (510; FIGS 8A and 8C show portion 871 of contact feature 871/852/742 electrically coupled to gate structure 510 and source/drain feature 221).
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Annotated FIGS. 4A/4B/4C (Xie)
Xie does not explicitly teach performing an etching process, thereby forming an opening extending through the substrate, wherein bottom surfaces of the source/drain feature and the gate structure are exposed in the opening.
However, Xie teaches contact feature 871/852/742 and contact 75 are formed similarly to internal contact 620 in FIG. 2B and 3B ([0045]), namely, by performing an etching process, thereby forming an opening ([0034]) extending through a dielectric layer (130, [0034]) and then forming the contact feature 871/852/742 in the opening ([0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed Xie’s contact structure by forming an opening extending through the substrate, wherein bottom surfaces of the source/drain feature and the gate structure are exposed in the opening, as taught by Xie in the steps of FIGS. 2A and 2B and in paragraphs [0034]-[0035], in order to electrically couple the gate of a first pull-down transistor to a source/drain region of a second pull-down transistor in an SRAM device ([0046]).
Regarding claim 18, Xie teaches the method of claim 17. Xie further teaches wherein a portion of the contact feature (871/852/742) is disposed directly under the gate structure (510, FIG. 8A, noting FIG. 8A has been flipped).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Bae et al. in U.S. Patent Application Publication US 2022/0320115 A1 (hereinafter Bae).
Regarding claim 19, Xie teaches the method of claim 17.
Xie does not explicitly teach wherein the contact feature (871/852/742) is spaced apart from the source/drain feature (211) by a silicide layer.
Bae teaches in FIG. 5A and related text, a contact feature (AC3, [0094]) is spaced apart from a source/drain feature (SD2, [0046]) by a silicide layer (SC, [0079]).
Xie and Bae are analogous art to the claimed invention because they are directed to SRAM devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Bae because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie such that the contact feature is spaced apart from the source/drain feature by a silicide layer, as taught by Bae, with the purpose of decreasing contact resistance at the interface between the contact feature and the source/drain feature. Use of silicide layers to reduce contact resistance is widely known in the art, and the transistors in Xie’s SRAM device would benefit from having reduced contact resistance, as would any transistor.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Chen et al. in U.S. Patent Application Publication US 2021/0098468 A1 (hereinafter Chen) and further in view of Kodate in U.S. Patent Application Publication US 2022/0069097 A1 (hereinafter Kodate).
Regarding claim 20, Xie teaches the method of claim 17.
Xie does not explicitly teach further comprising: before the forming of the contact feature, forming a dielectric liner along sidewalls of the opening, wherein the contact feature is spaced apart from the substrate by the dielectric liner.
Chen teaches in FIGS. 12, 13 and related text: before the forming of a contact feature (243, [0065]), forming a dielectric liner (650, [0064]) along sidewalls of an opening (FIG. 12), wherein the contact feature (243) is spaced apart from a substrate (280, [0036) by the dielectric liner (650).
Kodate teaches in FIG. 10B and related text, a dielectric liner (90A, [0039]) serves as a diffusion barrier ([0095]).
Xie, Chen and Kodate are analogous art to the claimed invention because they are directed to field effect transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Chen and Kodate because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie such that it further comprises: before the forming of the contact feature, forming a dielectric liner along sidewalls of the opening, wherein the contact feature is spaced apart from the substrate by the dielectric liner, as taught by Chen, with the purpose of preventing diffusion of contaminants or metal ions, since Kodate teaches a dielectric liner serves as a diffusion barrier (Kodate, [0095]).
Claims 21, 22, 28, 29 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie).
Regarding claim 21, Xie teaches in FIGS. 1A-8C, a method, comprising:
forming a first active region (active region of transistor 320, [0028], FIG. 1A) and a second active region (active region of transistor 310, [0028]), FIG. 1A) over a substrate (100/110, [0029]) and extending lengthwise along a first direction (horizontal direction in inset of FIGS. 1A/1B/1C), the first active region (active region of transistor 320) comprising a channel region (see annotated FIG. 1A) and a source/drain feature (321/322, FIG. 1B, [0028]) adjacent to first channel region (annotated FIG. 1A), the first channel region (annotated FIG. 1A) comprising a plurality of nanostructures ([0032]);
forming a first gate structure (520, FIG. 1B, [0031]) and a second gate structure (510, FIG. 1A, [0031])) extending lengthwise along a second direction (vertical direction in inset of FIGS. 1A/1B/1C) different from the first direction (horizontal direction in inset of FIGS. 1A/1B/1C), wherein the first gate structure (520) is disposed over the first active region (active region of transistor 320) and the second active region (active region of transistor 310), wherein the second gate structure (510) is disposed over the first active region (active region of transistor 320) and the second active region (active region of transistor 310);
forming a dielectric layer (140, FIGS. 4A/4B/4C, [0038]) extending over the first gate structure (520) and the second gate structure (510);
forming a conductive feature (871/852/742, FIG. 8A, [0046]/[0045]) to electrically couple to the second gate structure (510) and the source/drain feature (321/322; FIGS 8A and 8C show portion 871 of contact feature 871/852/742 electrically coupled to gate structure 510 and source/drain feature 321/322 through contact 620, [0035]).
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Annotated FIGS. 1A/1B/1C (Xie)
Xie does not explicitly teach forming a trench exposing a bottom surface of the second gate structure and a bottom surface of the source/drain feature.
However, Xie teaches contact feature 871/852/742 and contact 752 are formed similarly to internal contact 620 in FIG. 2B and 3B ([0045]), namely, by forming a trench (opening, [0034]) in a dielectric layer (130, [0034]) and then forming the contact feature 871/852/742 in the opening ([0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed Xie’s contact structure by forming a trench exposing a bottom surface of the second gate structure and a bottom surface of the source/drain feature, as taught by Xie in the steps of FIGS. 2A and 2B and in paragraphs [0034]-[0035], in order to electrically couple the gate of a first pull-down transistor to a source/drain region of a second pull-down transistor in an SRAM device ([0046]).
Regarding claim 22, Xie teaches the method of claim 21. Xie further teaches wherein the source/drain feature (321/322) is a first source/drain feature (321/322), the trench (opening, [0034]) is a first trench, and the conductive feature (871/852/742) is a first conductive feature (871/852/742), wherein the second active region (active region of transistor 310) comprises a second source/drain feature (311/312, FIG. 1A, [0028]), and the method further comprises:
forming a second trench (opening in layer 140, [0038]; FIG 4B) exposing a bottom surface of the first gate structure (520, [0038] appears exposed in FIG. 4B the unflipped version, and then becomes a bottom surface as it appears in FIG. 6B the flipped version of the drawing) and a bottom surface of the second source/drain feature (311/312, [0038]; appears in FIG. 6C the flipped version of the drawing: the claim does not preclude this interpretation since it does not provide a reference point of orientation or require consistency in the orientation of top/bottom surfaces of the first and second trenches); and
forming a second conductive feature (723/731/713, FIG. 4B, [0039]) in the trench to electrically couple to the first gate structure (520) and the second source/drain feature (311/312; FIG. 4B shows 731 of second conductive feature 723/731/713 electrically coupled to first gate structure 520, and FIG. 4C shows 731 electrically coupled to second source/drain feature 311).
Regarding claim 28, Xie teaches the method of claim 21. Xie teaches further comprising: forming a source/drain contact (721, FIG. 4B, [0039]) extending through the dielectric layer (140) and electrically coupled to the source/drain feature (321/322), wherein, a center line of the source/drain contact (721) is offset from a center line of the conductive feature (871/852/742, FIG. 8A/8B).
Regarding claim 29, Xie teaches the method of claim 21. Xie teaches wherein the second gate structure (510) is further disposed laterally adjacent to an edge of the first active region (active region of transistor 320, FIGS. 1A/1B).
Regarding claim 37, Xie teaches the method of claim 21. Xie teaches further comprising: forming inner spacers (522, FIG. 1B, [0031]) disposed under a topmost nanostructure of the plurality of nanostructures (annotated FIG. 1B in the rejection of claim 21) and disposed between the first gate (520) structure and the source/drain feature (321/322).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Chen et al. in U.S. Patent Application Publication US 2021/0098468 A1 (hereinafter Chen) and further in view of Kodate in U.S. Patent Application Publication US 2022/0069097 A1 (hereinafter Kodate).
Regarding claim 24, Xie teaches the method of claim 21.
Xie does not explicitly teach: after forming the trench, forming a dielectric liner extending along sidewalls of the trench.
Chen teaches in FIGS. 12, 13 and related text: after forming a trench (520, FIG. 12, [0059]), forming a dielectric liner (650, [0064]) extending along sidewalls of the trench (520).
Kodate teaches in FIG. B and related text, a dielectric liner (90A, [0039]) serves as a diffusion barrier ([0095]).
Xie, Chen and Kodate are analogous art to the claimed invention because they are directed to field effect transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Chen and Kodate because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie such that it further comprises: after forming the trench, forming a dielectric liner extending along sidewalls of the trench, as taught by Chen, with the purpose of preventing diffusion of contaminants or metal ions, since Kodate teaches a dielectric liner serves as a diffusion barrier (Kodate, [0095]).
Regarding claim 25, Xie as modified by Chen and Kodate teaches the method of claim 24.
Chen further teaches wherein the dielectric liner (650) extends into a source/drain feature (400, [0064]).
Xie, Chen and Kodate are analogous art to the claimed invention because they are directed to field effect transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Chen and Kodate because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie and Chen such that the dielectric liner extends into a source/drain feature, as taught by Chen, with the purpose of preventing diffusion of contaminants or metal ions, since Kodate teaches a dielectric liner serves as a diffusion barrier (Kodate, [0095]).
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Bae et al. in U.S. Patent Application Publication US 2022/0320115 A1 (hereinafter Bae).
Regarding claim 26, Xie teaches the method of claim 21.
Xie does not explicitly teach further comprising: after forming the trench, forming a silicide layer disposed between the source/drain feature and the conductive feature.
Bae teaches in FIGS. 9A and 10A: after forming a trench ([0125]), forming a silicide layer (SC, FIG. 10A, [0126]) disposed between a source/drain feature (SD2, FIG. 10, [0126]) and a conductive feature (AC3, FIG. 10A, [0126]).
Xie and Bae are analogous art to the claimed invention because they are directed to SRAM devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Bae because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie to include: after forming the trench, forming a silicide layer disposed between the source/drain feature and the conductive feature, as taught by Bae, with the purpose of decreasing contact resistance at the interface between the contact feature and the source/drain feature. Use of silicide layers to reduce contact resistance is widely known in the art, and the transistors in Xie’s SRAM device would benefit from having reduced contact resistance, as would any transistor.
Regarding claim 27, Xie as modified by Bae teaches the method of claim 26. Xie further teaches wherein a width of a bottom surface of the contact feature (bottom surface of 742 in 871/852/742) is less than a width of a top surface of the conductive feature (871/852/742). The combined structure of Xie and Bae thus teaches wherein a width of the silicide layer is less than a width of a top surface of the conductive feature.
Claims 32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Bae et al. in U.S. Patent Application Publication US 2022/0320115 A1 (hereinafter Bae).
Regarding claim 32, Xie teaches the method of claim 31.
Xie does not explicitly teach further comprising: forming a first silicide layer between the first conductive feature and the first source/drain feature; and forming a second silicide layer between the second conductive feature and the second source/drain feature.
Bae teaches in FIGS. 9A and 10A: forming a silicide layer (SC, FIG. 10A, [0126]) between a conductive feature (AC3, FIG. 10A, [0126]) and a source/drain feature (SD2, FIG. 10, [0126]).
Xie and Bae are analogous art to the claimed invention because they are directed to SRAM devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Bae because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie to further comprise: forming a first silicide layer between the first conductive feature and the first source/drain feature; and forming a second silicide layer between the second conductive feature and the second source/drain feature, as taught by Bae, with the purpose of decreasing contact resistance at the interface between the conductive features and the source/drain features. Use of silicide layers to reduce contact resistance is widely known in the art, and the transistors in Xie’s SRAM device would benefit from having reduced contact resistance, as would any transistor.
Regarding claim 34, Xie teaches the method of claim 31. Xie further teaches transistors in SRAM devices may be p-type ([0002]), and transistors 310 and 320 are first and second pull-up transistors ([0028]).
Xie does not explicitly teach wherein the first gate-all-around transistor and the second gate-all-around transistor comprise p-type transistors.
Bae teaches first and second pull-up transits may be p-type transistors ([0022]).
Xie and Bae are analogous art to the claimed invention because they are directed to SRAM devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Bae because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie wherein the first gate-all-around transistor and the second gate-all-around transistor comprise p-type transistors, as taught by Bae, in order to form an SRAM memory cell ([0022]). The devices of Xie and Bae both have the gates of the first and second pull-up transistors electrically coupled to the source/drains of the second and first pull-up transistors, respectively (Bae, [0022]; Xie, [0026]), as is common in an SRAM memory cell.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al in. U.S. Patent Application Publication US 2023/0345691 A1 (hereinafter Xie) in view of Chen et al. in U.S. Patent Application Publication US 2021/0098468 A1 (hereinafter Chen) and further in view of Kodate in U.S. Patent Application Publication US 2022/0069097 A1 (hereinafter Kodate)..
Regarding claim 33, Xie teaches the method of claim 31.
Xie does not explicitly teach further comprising: forming a first dielectric liner providing isolation between the first conductive feature and the substrate and a second dielectric liner providing isolation between the second conductive feature and the substrate.
Chen teaches in FIGS. 12, 13 and related text: forming a dielectric liner (650, [0064]) providing isolation between a conductive feature (243, FIG. 13, [0065]) and a substrate (280, [0065]).
Kodate teaches in FIG. B and related text, a dielectric liner (90A, [0039]) serves as a diffusion barrier ([0095]).
Xie, Chen and Kodate are analogous art to the claimed invention because they are directed to field effect transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie in view of Chen and Kodate because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie such that it further comprises: forming a first dielectric liner providing isolation between the first conductive feature and the substrate and a second dielectric liner providing isolation between the second conductive feature and the substrate, as taught by Chen, with the purpose of preventing diffusion of contaminants or metal ions, since Kodate teaches a dielectric liner serves as a diffusion barrier (Kodate, [0095]).
Conclusion
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/S.L.J./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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