DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21, 24-29, 32-39, 41, and 43-44 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Support for the amended intendent claims 21, 29, and 43 were disclosed as finding support in Figs. 10-12, [0048], and [0055]-[0060]. However, the examiner disagrees.
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Claim 21 recites the limitations a method for forming a device stack comprising a logic section, a first memory section comprising a set of landing pads and a redistribution layer connected to the set of landing pads, and a second memory section, the method comprising: removing a first portion of a substrate from a first side of the second memory section, wherein: a second side of the second memory section is disposed on a sacrificial substrate; and a second portion of the substrate remains on the first side of the second memory section; subsequent to removing the first portion of the substrate and while the second side of the second memory section is disposed on the sacrificial substrate bonding the redistribution layer of the first memory section to the second memory section, wherein the second portion of the substrate is disposed between the redistribution layer and the first side of the second memory section, the redistribution layer being connected to the second memory section; (emphasis added) bonding the logic section to a second side of the first memory section; and removing at least a portion of the sacrificial substrate from the second side of the second memory section. However the feature wherein the second portion of the substrate is disposed between the redistribution layer and the first side of the second memory section, the redistribution layer being connected to the second memory section; is not shown in Fig. 12. The second portion of the substrate is formed on the lower portion of the second memory section (as seen in annotated Fig. 12 above) and is not disposed between the redistribution layer and the first side of the second memory section. According to the embodiment as seen in Fig. 12 the sacrificial substrate is the substrate that is formed between the redistribution layer and the first side of the second memory section. Therefore the amendments are not supported by the specification as originally filed. Claims 23-28 depend from this claim and therefore inherit its deficiency. Appropriate action is required.
Claim 29 recites the limitations a method for forming a device stack comprising a logic section, a first memory section comprising a set of landing pads and a redistribution layer connected to the set of landing pads, and a second memory section, the method comprising: removing a first portion of a substrate from a first side of the second memory section, wherein: a second side of the second memory section is disposed on a sacrificial substrate; and a second portion of the substrate remains on the first side of the second memory section; bonding the redistribution layer of the first memory section to the second memory section, wherein the second portion of the substrate is disposed between the redistribution layer and the first side of the second memory section, the redistribution layer being connected to the second memory section; (emphasis added) subsequent to bonding the redistribution layer of the first memory section to the second memory section, bonding the logic section to a second side of the first memory section; and removing at least a portion of the sacrificial substrate from the second side of the second memory section. However the feature wherein the second portion of the substrate is disposed between the redistribution layer and the first side of the second memory section, the redistribution layer being connected to the second memory section; is not shown in Fig. 12. The second portion of the substrate is formed on the lower portion of the second memory section (as seen in annotated Fig. 12 above) and is not disposed between the redistribution layer and the first side of the second memory section. According to the embodiment as seen in Fig. 12 the sacrificial substrate is the substrate that is formed between the redistribution layer and the first side of the second memory section. Therefore the amendments are not supported by the specification as originally filed. Claims 32-34 depend from this claim and therefore inherit its deficiency. Appropriate action is required.
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Claim 35 recites the limitations a method for a stack of memory sections, wherein a first side of the first memory section is disposed on a first substrate, and wherein a second side of the first memory section is disposed on a second substrate, the method comprising: removing a first portion of the second substrate, wherein a second portion of the second substrate remains on the second side of the first memory section; forming a second memory section comprising a redistribution layer connected to a set of landing pads, wherein the redistribution layer comprises a first set of bonding pads, bonding the redistribution layer to the first memory section while the first side of the first memory section is disposed on the first substrate, wherein the second portion of the second substrate is disposed between the redistribution layer and the second side of the first memory section; and removing at least a portion of the first substrate from the first side of the first memory section. However the feature wherein the second portion of the second substrate is disposed between the redistribution layer and the second side of the first memory section; is not shown in Fig. 12. The second portion of the substrate is formed on the lower portion of the first memory section (as seen in annotated Fig. 12 above) and is not disposed between the redistribution layer and the second side of the first memory section. According to the embodiment as seen in Fig. 12 the sacrificial substrate is the substrate that is formed between the redistribution layer and the second side of the first memory section. Therefore the amendments are not supported by the specification as originally filed. Claims 36-39 and 41 depend from this claim and therefore inherit its deficiency. Appropriate action is required.
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Claim 43 recites the limitations a method for forming a memory device comprising a bonded stack of a bottommost memory section, one or more intermediate memory sections, and a topmost memory section, each of the one or more intermediate and topmost memory sections comprising a redistribution layer, the bottommost memory section being disposed on a first substrate, the method comprising: while the bottommost memory section is disposed on the first substrate: removing a first portion of a second substrate from a first intermediate memory section of the one or more intermediate memory sections, wherein a second portion of the second substrate remains on the first intermediate memory section; bonding the topmost memory section to the first intermediate memory section of the one or more intermediate memory sections, wherein the second portion of the second substrate is disposed between the topmost memory section and the first intermediate memory section; and subsequent to bonding the topmost memory section to the first intermediate memory section of the one or more intermediate memory sections, bonding a logic section to the topmost memory section; and removing at least a portion of the first substrate from the bottommost memory section. However the feature bonding the topmost memory section to the first intermediate memory section of the one or more intermediate memory sections, wherein the second portion of the second substrate is disposed between the topmost memory section and the first intermediate memory section; is not shown in Fig. 12. The second portion of the second substrate is formed on the lower portion of the first intermediate memory section (as seen in annotated Fig. 12 above) and is not disposed between the topmost memory section and the first intermediate memory section. According to the embodiment as seen in Fig. 12 an additional substrate that is formed on the topmost memory section is the substrate that is formed between the topmost memory section and the first intermediate memory section. Therefore the amendments are not supported by the specification as originally filed. Claim 44 depends from this claim and therefore inherit its deficiency. Appropriate action is required.
Response to Arguments
Applicant’s arguments with respect to claim(s) 21, 29, 35, and 43 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 12/23/25
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897