DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed April 27, 2026.
Claims 1-8 are pending. Claims 1 and 5 are amended. Claims 1 and 5 are independent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang et al. (U.S. 2016/0099070; hereinafter “Jiang”).
Regarding independent claim 1, Jiang discloses a method comprising:
programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer and the N different values are all possible values the analog neural non-volatile memory cell will be programmed to during operation (“one or more targets data states of threshold voltage ranges,” see page 5, par. 0070);
verifying that a respective one of the N different values stored in the analog neural non-volatile memory cell within an acceptable window of values set by an upper threshold and a lower threshold (see Figs. 10C-10E: the plurality of number of cells store different states and each state is set by an upper threshold and a lower threshold, for example, S1 has a starting threshold Vv1 and an ending threshold before Vv2, S2 has a starting threshold at Vv2 and an ending threshold before Vv2) around the respective target value (“several verify pulses between each program pulse to test for different program states,” see page 6, par. 0072);
repeating the programming and verifying for all other values within the N values (a plurality of program pulse are applied, i.e. programming is repeated, and between each program pulse, verify pulses are applied to test for different program states, i.e. N values, see page 6, par. 0072), wherein the acceptable window of values is different in size for two or more of the N values for a same programming stage (From Figure 10C to 10E the acceptable window of values is different in size, different size values shown in Figs. 10C to 10E are in a same programming process, see page 6, par. 0080), wherein the size is the difference between the upper threshold and the lower threshold for the acceptable window of values (Figs. 10C-10E: during the repetition of the programming and verifying, the size of the acceptable window varies from 10C to 10E. For example: the difference between Vv1’ and Vv2’ of Fig. 10C varies from the difference between Vv1 and Vv2 of Fig. 10E); and
identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates the respective one of the N different values stored in the cell is not within the acceptable window of values around the respective target value (see page 6, par. 0073).
Regarding claim 2, Jiang discloses wherein the analog neural non-volatile memory cell is a stacked-gate flash memory cell (see page 2, par. 0044).
Regarding claim 3, Jiang discloses wherein the analog neural non-volatile memory cell is a split-gate flash memory cell (see page 2, par. 0044).
Regarding independent claim 5, Jiang discloses a system (Fig. 7) comprising:
an array of analog neural non-volatile memory cells (Fig. 7: 700); and
test control logic to:
program a selected analog neural non-volatile memory cell in the array to a respective target value representing one of N different values, where N is an integer and the N different values are all possible values the analog neural non-volatile memory cell will be programmed to during operation (“one or more targets data states of threshold voltage ranges,” see page 5, par. 0070);
verify that a respective one of the N different values stored in the selected analog neural non-volatile memory cell is within an acceptable window of values set by an upper threshold and a lower threshold (see Figs. 10C-10E: the plurality of number of cells store different states and each state is set by an upper threshold and a lower threshold, for example, S1 has a starting threshold Vv1 and an ending threshold before Vv2, S2 has a starting threshold at Vv2 and an ending threshold before Vv2) around the respective target value (“several verify pulses between each program pulse to test for different program states,” see page 6, par. 0072);
repeat the programming and verifying for all other values within the N values (a plurality of program pulse are applied, i.e. programming is repeated, and between each program pulse, verify pulses are applied to test for different program states, i.e. N values, see page 6, par. 0072), wherein the acceptable window of values is different in size for two or more of the N values for a same programming stage (From Figure 10C to 10E the acceptable window of values is different in size, different size values shown in Figs. 10C to 10E are in a same programming process, see page 6, par. 0080), wherein the size is the difference between the upper threshold and the lower threshold for the acceptable window of values (Figs. 10C-10E: during the repetition of the programming and verifying, the size of the acceptable window varies from 10C to 10E. For example: the difference between Vv1’ and Vv2’ of Fig. 10C varies from the difference between Vv1 and Vv2 of Fig. 10E); and
identify the selected analog neural non-volatile memory cell as bad if any of the verifying indicates the respective one of the N different values stored in the cell is not within the acceptable window of values around the respective target value (see page 6, par. 0073).
Regarding claim 6, Jiang discloses wherein the selected analog neural non-volatile memory cell is a stacked-gate flash memory cell (see page 2, par. 0044).
Regarding claim 7, Jiang discloses wherein the selected analog neural non-volatile memory cell is a split-gate flash memory cell (see page 2, par. 0044).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (U.S. 2016/0099070; hereinafter “Jiang”) in view of Lai et al. (U.S. 2020/0202941; hereinafter “Lai”).
Regarding claim 4, Jiang discloses the limitations with respect to claim 1.
However, Jiang is silent with respect to the array is part of a neural network.
Similar to Jiang, Lai teaches programming operation in an array of non-volatile memory cell (see Abstract).
Furthermore, Lai teaches wherein the array is part of a neural network (see page 1, par. 0019-0020).
Since Lai and Jiang are from the same field of endeavor, the teachings described by Lai would have been recognized in the pertinent art of Jiang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lai with the teachings of Jiang for the purpose of provide save circuit area, see Lai’s page 4, par. 0050.
Regarding claim 8, Jiang discloses the limitations with respect to claim 5.
However, Jiang is silent with respect to the array is part of a neural network.
Similar to Jiang, Lai teaches a system (Fig. 1) comprising test control logic (Fig. 1: PE1) to perform programming operation in an array of non-volatile memory cell (see Abstract).
Furthermore, Lai teaches wherein the array is part of a neural network (see page 1, par. 0019-0020).
Since Lai and Jiang are from the same field of endeavor, the teachings described by Lai would have been recognized in the pertinent art of Jiang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lai with the teachings of Jiang for the purpose of provide save circuit area, see Lai’s page 4, par. 0050.
Response to Arguments
Applicant's arguments filed with respect to claims 1 and 5 have been fully considered but they are not persuasive.
With respect to independent claims 1 and 5, Applicant asserts that Jiang discloses different programming stages from Figure 10C to 10E and therefore fails to disclose acceptable window of values is different in size for “the same programming stage” as amended, see Applicant’s Remarks pages 5-6. This particular remark is not considered persuasive.
Jiang’s Figures 10C to 10E shows different sizes of threshold voltage distribution for a plurality of memory cells, and the difference in size is within a same “programming process,” see Jiang’s paragraph 0080. Therefore, the rejection is considered proper and maintained. The rejection has been augmented to address the recent amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
Prosecution Insights