Prosecution Insights
Last updated: May 29, 2026
Application No. 17/893,277

ELECTRONIC DEVICES WITH REDUCED OHMIC TO OHMIC DIMENSIONS

Final Rejection §103
Filed
Aug 23, 2022
Examiner
TRAN, TAN N
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed, Inc.
OA Round
4 (Final)
87%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
953 granted / 1100 resolved
+18.6% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
38 currently pending
Career history
1138
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
76.0%
+36.0% vs TC avg
§102
11.7%
-28.3% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1100 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claim(s) 17, 18, 20, 22, 23, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (9780181) in view of Lin et al. (20230378313). With regard to claim 17, Teo et al. disclose an electronic device (for example, see figs. 2A, 2B), comprising: a group III-nitride semiconductor layer (15; for example, column 6, lines 29 - 32); and a pair of ohmic contacts (S/D contacts; for example, column 6, lines 55 - 58) on the semiconductor layer (15), wherein the ohmic contacts (S/D) are laterally spaced apart on the semiconductor layer (15) by a distance of about less than 2 micron (for example, see column 7, lines 37 – 39 discloses Gate to Source electrode distance Lgs = 0.2 μm; and Gate to Drain electrode distance Lgd = 1.7 μm and Gate length Lg = 50 nm = 0.05 μm; so the ohmic contacts (S/D) are laterally spaced apart on the semiconductor layer (15) by a distance of about Lgs + Lgd + Lg = 1.95 μm); PNG media_image1.png 413 530 media_image1.png Greyscale Teo et al. do not clearly disclose the ohmic contacts comprise a metal silicide layer that is in direct contact with the semiconductor layer. However, Lin et al. discloses the ohmic contacts comprise a metal silicide layer that is in direct contact with the semiconductor layer. (for example, see paragraphs [0024], [0020] fig. 8). PNG media_image2.png 477 601 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al.’s device to replace the ohmic contacts comprise a metal silicide layer that is in direct contact with the semiconductor layer as taught by Lin et al. in order to enhance a low resistance of the source or drain for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 18, Teo et al. disclose the ohmic contacts (S/D) are spaced apart on the semiconductor layer (15) by a distance of about 1.95 μm (for example, see column 7, lines 37 – 39 discloses Gate to Source electrode distance Lgs = 0.2 μm; and Gate to Drain electrode distance Lgd = 1.7 μm and Gate length Lg = 50 nm = 0.05 μm; so Lgs + Lgd + Lg = 1.95 μm). With regard to claim 20, Lin et al. disclose the ohmic contacts (56) comprise metal silicide contacts. (for example, see paragraphs [0024], [0020] fig. 8). With regard to claim 22, Lin et al. disclose the ohmic contacts (56) comprise TiSi. (for example, see paragraphs [0024], [0020] fig. 8). With regard to claim 23, Lin et al. disclose the metal silicide contacts (56) comprise TiSi. (for example, see paragraphs [0024], [0020] fig. 8) inherently have a sheet resistance of less than about 3 ohms/square. (Because the metal silicide contacts of Lin et al. is formed the same material, TiSi, as that of applicant, thus the metal silicide contacts have the same results as the claimed invention). With regard to claim 26, Teo et al. disclose the semiconductor layer (15) comprises GaN. (for example, column 6, lines 29 - 32). 3. Claim(s) 19, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (9780181) in view of Lin et al. (20230378313) and further in view of Boos (6448648). With regard to claim 19, Teo et al. and Lin et al. do not clearly disclose the ohmic contacts are spaced apart on the semiconductor layer by a distance of about 0.5 micron. However, Boos discloses the ohmic contacts (ohmic contacts 28 functioning as a source and a drain) are spaced apart on the semiconductor layer (22) by a distance of about 0.5 micron. (for example, see column 1, lines 61 - 67; column 3, lines 38 – 43, fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al. and Lin et al.’s device to have the ohmic contacts are spaced apart on the semiconductor layer by a distance of about 0.5 micron as taught by Boos in order to enhance a low resistance of the source or drain for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 24, Teo et al. and Lin et al. do not clearly disclose the metal silicide contacts have a vertical thickness above the semiconductor layer of about 100 nm. However, Boos discloses the metal silicide contacts have a vertical thickness above the semiconductor layer of about 100 nm. (a thickness of said barrier layer is 1000.ANG = 100 nm wherein the barriers are the metal silicide contacts; for example, see claim 2). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al. and Lin et al.’s device to have the metal silicide contacts have a vertical thickness above the semiconductor layer of about 100 nm as taught by Boos in order to enhance a low resistance of the source or drain for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. 4. Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (9780181) in view of Lin et al. (20230378313) and further in view of Hagleitner et al. (9548206). With regard to claim 21, Teo et al. and Lin et al. do not clearly disclose the metal silicide contacts are free of non-silicided portions of the metal. However, Hagleitner et al. discloses the metal silicide contacts are free of non-silicided portions of the metal (a Ni film formed by sputtering at the rear surface of the semiconductor substrate 10 entirely is converted into a silicide to form the contacts. Therefore, the metal silicide contacts are inherently free of non-silicided portions of the metal; for example, see column 17, lines 28 - 30). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al. and Lin et al.’s device to have the metal silicide contacts are free of non-silicided portions of the metal as taught by Hagleitner et al. in order to improve a surface morphology and sharp, well-defined edge features contacts on the semiconductor devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. 5. Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (9780181) in view of Lin et al. (20230378313) and further in view of Hashizume et al. (11876131). With regard to claim 25, Teo et al. and Lin et al. do not clearly disclose the metal silicide contacts comprise NiSi. However, Hagleitner et al. discloses the metal silicide contacts (115’) comprise NiSi. (for example, see column 2, lines 3 – 6, fig. 4). PNG media_image3.png 316 526 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al. and Lin et al.’s device to incorporate the metal silicide contacts comprise NiSi as taught by Hagleitner et al. in order to reducing an on-resistance for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. 6. Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (9780181) in view of Lin et al. (20230378313) and further in view of Zhou (5038187). With regard to claim 28, Teo et al. disclose the ohmic contacts (S/D) are formed on contact regions (regions, forming directly under the S/D and in the semiconductor layer 15, functions contact regions) of the semiconductor layer (15). Teo et al. and Lin et al. do not clearly disclose the contact regions comprise n+ regions in the semiconductor layer. However, Zhou discloses the contact regions (20) comprise n+ regions in the semiconductor layer (20, 34). (for example, see fig. 3). PNG media_image4.png 585 844 media_image4.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Teo et al. and Lin et al.’s device to have the contact regions comprise n+ regions in the semiconductor layer as taught by Zhou in order to a high electron mobility efficiency of the device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Response to Amendment 7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
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Prosecution Timeline

Show 5 earlier events
Nov 11, 2025
Request for Continued Examination
Nov 18, 2025
Response after Non-Final Action
Nov 21, 2025
Interview Requested
Dec 04, 2025
Examiner Interview Summary
Dec 04, 2025
Applicant Interview (Telephonic)
Dec 30, 2025
Non-Final Rejection mailed — §103
Mar 27, 2026
Response Filed
May 08, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+10.1%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1100 resolved cases by this examiner. Grant probability derived from career allowance rate.

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