DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 17 – 20, 22 – 24, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boos (6448648) in view of Lin et al. (20230378313).
With regard to claim 17, Boos discloses an electronic device (for example, see fig. 1), comprising:
a semiconductor layer (22 or two or more semiconductors, column 2, lines 47, 48); and
a pair of ohmic contacts (Pd/barrier/Au or Pd/Pt/Au ohmic contacts 28 functioning as a pair of ohmic contacts wherein ohmic contacts 28 functioning as a source and a drain; for example, see column 1, lines 61 – 65; column 5, lines 10 - 11) on the semiconductor layer (22), wherein the ohmic contacts (28) are laterally spaced apart on the semiconductor layer (22) by a distance of about 1 micron or less than 2 micron (for example, see column 1, lines 61 – 67; column 3, lines 38 - 43);
the ohmic contacts (Pd/barrier/Au ohmic contacts 28 functioning as ohmic contacts) comprise metal silicide contacts (for example, see column 3, lines 17 – 18; or the palladium layer is chemically reactive with the semiconductor device to facilitate low contact resistance material wherein the low contact resistance material may comprise a metal silicide material; for example, see column 3, lines 2 - 4).
for example, see column 3, lines 2 - 4
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Boos do not clearly disclose the metal silicide layer that is in direct contact with the semiconductor layer.
However, Lin et al. discloses a metal silicide layer (56) that is in direct contact with the semiconductor layer (12). (for example, see paragraphs [0024], [0020] fig. 8).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos’s device to replace the ohmic contacts comprise metal silicide contacts by the metal silicide layer that is in direct contact with the semiconductor layer as taught by Lin et al. in order to enhance a low resistance of the source or drain for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 18, Boos discloses the ohmic contacts (ohmic contacts 28 functioning as a source and a drain) are spaced apart on the semiconductor layer (22) by a distance of less than 2 micron or about 1.5 microns. (for example, see column 3, lines 38 - 43).
With regard to claim 19, Boos discloses the ohmic contacts (ohmic contacts 28 functioning as a source and a drain) are spaced apart on the semiconductor layer (22) by a distance of about 0.5 micron.
With regard to claim 20, Boos discloses the ohmic contacts (Pd/barrier/Au ohmic contacts 28 functioning as ohmic contacts) comprise metal silicide contacts. (for example, see column 3, lines 17 - 18).
With regard to claim 22, Boos discloses the metal silicide contacts comprise TiSi. (for example, see column 3, lines 17 - 18).
With regard to claim 23, Boos discloses the metal silicide contacts (for example, see column 3, lines 17 - 18) inherently have a sheet resistance of less than about 3 ohms/square. (because the metal silicide contacts of Boos is formed the same, TiSi material, as that of applicant, thus the metal silicide contacts has the same results as the claimed invention).
With regard to claim 24, Boos discloses the metal silicide contacts have a vertical thickness above the semiconductor layer of about 100 nm. (a thickness of said barrier layer is 1000.ANG = 100 nm wherein the barriers are the metal silicide contacts; for example, see claim 2).
With regard to claim 26, Boos discloses the semiconductor layer (the semiconductor selected from the group consisting of Group III-V elements wherein Group III-V elements comprises GaN).
3. Claim(s) 21, 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boos (6448648) in view of Lin et al. (20230378313) and further in view of Hagleitner et al. (9548206).
With regard to claim 21, Boos and Lin et al. do not clearly disclose the metal silicide contacts are free of non-silicided portions of the metal.
However, Hagleitner et al. discloses the metal silicide contacts are free of non-silicided portions of the metal (a Ni film formed by sputtering at the rear surface of the semiconductor substrate 10 entirely is converted into a silicide to form the contacts. Therefore, the metal silicide contacts are inherently free of non-silicided portions of the metal; for example, see column 17, lines 28 - 30).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos and Lin et al.’s device to have the metal silicide contacts are free of non-silicided portions of the metal as taught by Hagleitner et al. in order to improve a surface morphology and sharp, well-defined edge features contacts on the semiconductor devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 27, Boos and Lin et al. do not clearly disclose the semiconductor layer comprises SiC.
However, Hagleitner et al. discloses the semiconductor layer comprises SiC. (for example, see column 5, line 5).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos and Lin et al.’s device to have the semiconductor layer comprises SiC as taught by Hagleitner et al. in order to enhance a breakdown voltage and reducing an on-resistance for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
4. Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boos (6448648) in view of Lin et al. (20230378313) and further in view of Hashizume et al. (11876131).
With regard to claim 25, Boos and Lin et al. do not clearly disclose the metal silicide contacts comprise NiSi.
However, Hagleitner et al. discloses the metal silicide contacts (115’) comprise NiSi. (for example, see column 2, lines 3 – 6, fig. 4).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos and Lin et al.’s device to incorporate the metal silicide contacts comprise NiSi as taught by Hagleitner et al. in order to reducing an on-resistance for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
5. Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boos (6448648) in view of Lin et al. (20230378313) and further in view of Zhou (5038187).
With regard to claim 28, Boos disclose the ohmic contacts (28) are formed on contact regions (referred to as “22A” by examiner’s annotation shown in fig. 1 below) of the semiconductor layer (22).
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Boos and Lin et al. do not clearly disclose the contact regions comprise n+ regions in the semiconductor layer.
However, Zhou discloses the contact regions (20) comprise n+ regions in the semiconductor layer (20, 34). (for example, see fig. 3).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos and Lin et al.’s device to have the contact regions comprise n+ regions in the semiconductor layer as taught by Zhou in order to a high electron mobility efficiency of the device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Arguments
6. Applicant’s arguments filed 11/11/25 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that "neither Boos nor Lin, taken alone or together, enables a skilled person to make "a pair of ohmic contacts on the semiconductor layer, wherein the ohmic contacts are laterally spaced apart on the semiconductor layer by a distance of less than 2 microns; wherein the ohmic contacts comprise a metal silicide layer that is in direct contact with the semiconductor layer". However, column 1, lines 61 - 65; column 3, lines 2 - 4; column 5, lines 10 - 11, and column 1, lines 61 - 67; column 3, lines 38 - 43, fig. 1 of Boos does show a pair of ohmic contacts (Pd/barrier/Au or Pd/Pt/Au ohmic contacts 28 functioning as a pair of ohmic contacts wherein ohmic contacts 28 functioning as a source and a drain; for example, see column 1, lines 61 - 65; column 5, lines 10 - 11) on the semiconductor layer (22), wherein the ohmic contacts (28) are laterally spaced apart on the semiconductor layer (22) by a distance of about I micron or less than 2 micron (for example, see column 1 lines 61 - 67; column 3, lines 38 - 43); wherein the ohmic contacts (28) may comprise a metal silicide layer (the palladium layer is chemically reactive with the semiconductor device to facilitate low contact resistance material wherein the low contact resistance material may comprises a metal silicide material; for example, see column 3, lines 2 - 4) that is in direct contact with the semiconductor layer. The ohmic contacts (28) are not sure to comprise a metal silicide material functioning as a metal silicide layer. However, Lin et al. discloses a metal silicide layer (56) that is in direct contact with the semiconductor layer (12). (for example, see paragraphs [0024], [0020] fig. 8). It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Boos’s device to replace the ohmic contacts comprise metal silicide contacts by the metal silicide layer that is in direct contact with the semiconductor layer as taught by Lin et al. in order to enhance a low resistance of the source or drain for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Thus, applicant's claims do not distinguish over Boos and Lin et al. references.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812