Attorney’s Docket Number: TEL0040-US (130576-0142)
Filing Date: 08/23/2022
Claimed Priority Date: 09/01/2021 (PRO 63/239,880)
Applicant: Fulford et al
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendment filed on 08/04/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 08/04/2025, responding to the Office action mailed on 04/14/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant amended claims 1, 9 Accordingly, pending in this office action are claims 1-20.
Response to Amendment
Applicant’s amendments to the claims 1, 9, 15 have overcome the claim rejections under 35 U.S.C. 112, and 35 U.S.C. 103, as previously formulated in the same Office action.
However, applicant’s amendments have raised new issues, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments to the claims.
Applicants’ amendments to the specification and drawings have overcome the previous objections, however new objections to the drawings are listed below.
Drawings
The drawings of Figure 3 are objected to under 37 CFR 1.83(a) because they fail to show the device. Fig 3 Cross-sectional view 306 includes a white box that is not labeled or described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
Figure 17 Top View 1700/1704 seems to show two columns of transistors, while the cross sectional view 1702/1706, shows three columns of transistors making the drawing difficult to interpret. All other top views/cross sections show three columns of transistors.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a core extending orthogonally through a central portion of the device region, wherein the core comprises one of air or dielectric material” as part of the first device, and not the second. The disclosure as originally filed fails to support an arrangement where the core gap exists in only a first device and as the indentations of the claim shows, the core gap does not exist in the second device. In Par [0079] of the specification, the cavity or gap core may extend “through the central portion of the device regions, as well as beneath and above the device regions, comprising air gap or a dielectric material filling for electrical insulation.”
The specification and figures (e.g., Fig 8) describes the hollow core existing in both device regions, the first and the second. As such the claimed subject matter is directed to New Matter.
The applicant may cancel the claim, amend the claim, or demonstrate explicit support for the claimed subject matter in the original disclosure (e.g., by citing specific excerpts from Specification or features in Drawings related to the claimed embodiment, as originally filed). A broad statement alleging support for the claimed subject matter will be considered non-persuasive.
Claim 2-8 depends from claim 1, thus inherits the deficiencies identified supra.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 08/04/2025 have been considered but are moot in view of the new grounds of rejection.
Allowable Subject Matter
Claims 9-20 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 9 and claim 16, the closest identified prior art, discloses a stacked vertical FET comprising:
a stack of layers upon a substrate, the stack of layers including:
a first device (e.g., lower vertical device segments 263 in Fig 16) comprising:
a first insulation layer (e.g., second protective liner 150) separating a source contact layer (e.g., lower source/drain contact 340 [0135]) from a gate contact layer (e.g., 284/282 [0107]) and a second insulation layer (e.g., first protective liner 150) separating a drain contact layer (e.g., lower source/drain slabs 350) from the gate contact layer; a device region orthogonal to a plane defined by a surface of at least one of the layers in the stack of layers (e.g., vertical pillars 260), the device region comprising a source and drain (e.g., S/D 261 separated by channel region) separated by a channel region (e.g., 260) that is at least partially surrounded by a gate dielectric interposed between the gate contact layer and the channel region (e.g., 260 is partially surrounded by a gate dielectric 280) ; and
a first region comprising a first silicide formed at a first end of the device region proximal to the source and a second region comprising a second silicide formed at a second end of the device region proximal to the drain (e.g., contacts 340 and 350 may be comprised of a silicide and they are positioned at ends of the device region [0135]); and
a second device comprising:
a third insulation layer (e.g., fourth protective liner 210) separating a second source contact layer (e.g., upper source/drain contacts 310) from a second gate contact layer (e.g., e.g., 284/282 [0107]) and a fourth insulation layer (e.g., third protective liner 190) separating a second drain contact layer (e.g., upper source/drain contact sections 322) from the second gate contact layer;
a second device region orthogonal to the plane (e.g., vertical pillars 260) and comprising a second source and a second drain (e.g., S/d 262 separated by a channel region) separated by a second channel region that is at least partially surrounded by a second gate dielectric interposed between the second gate contact layer and the second channel region (e.g., 260 is partially surrounded by a gate dielectric 280); and
While Zhou discloses silicide used to contact the S/D regions, it does not disclose germanicide formed at the ends of the second device region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose stacked vertical FET devices
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814