Prosecution Insights
Last updated: May 29, 2026
Application No. 17/894,095

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Aug 23, 2022
Examiner
PRASAD, NEIL R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
4 (Final)
85%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
598 granted / 702 resolved
+17.2% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
722
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.2%
+42.2% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 702 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 2/3/2026 have been fully considered but they are not persuasive. Regarding claim 1, applicant argues that the prior art does not show a portion of the first encapsulant located between the first die and first redistribution structure. However, in the embodiment in Figure 5, Song discloses an encapsulant (524) which is both above and below the die (204) and redistribution structures (214/526). Regarding claim 10, applicant argues one would not be motivated to view the second integrated circuit die 140 of Yu alone as a replacement for the device die 58 of Su. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Additionally, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). Regarding claim 16, applicant argues that encapsulating the second die after attaching the third die would not be possible because without the encapsulant material, there would be insufficient support. In response to applicant's argument, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In this case, it is suggested that using Song’s interconnect and encapsulation structure would provide improved rigidity to the device. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Publication No. 2017/0133351) in view of Song et al. (US Publication No. 2009/0321908), and further in view of Mallik et al. (US Publication No. 2023/0207545). Regarding claim 1, Su discloses a semiconductor package (Figures 12 and 15), comprising: a first redistribution structure (70) a second redistribution structure (52) over the first redistribution structure (70) a first die (58) located between the first redistribution structure (70) and the second redistribution structure (52) a first encapsulant (66) laterally encapsulating the first die (58) a second die (34) disposed on and electrically connected (44 connects to 52) to the second redistribution structure (52) a second encapsulant (48) laterally encapsulating the second die conductive connectors (32) surrounding the second die (34), wherein the conductive connectors are embedded in the second encapsulant (48) a third die (234 including interconnect structure 92/94) disposed over the second die (34), wherein the third die (234) is in direct contact with the second encapsulant (48) and the conductive connectors (32), the third die (234 including interconnect structure 92/94) comprises a semiconductor substrate (234) and an interconnect structure (92/94) disposed on the semiconductor substrate (234) PNG media_image1.png 402 714 media_image1.png Greyscale Su does not disclose a portion of the first encapsulant located between the first die and first redistribution structure and the second encapsulant to be integrally formed and a portion of the second encapsulant is sandwiched between the second die and the interconnect structure of the third die. However, Song discloses the first encapsulant (218) located between a die first (204) and a first redistribution structure (206) and a second encapsulant (102) which is integrally formed with conductive connectors (222) embedded and between the second die (lower die of stack 220) and the interconnect structure (222) of the third die (upper die connected to 222) (Figure 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the first encapsulant to be between the first die and redistribution structure and second encapsulant of Su to be integrally formed, as taught by Song, since it can mitigate warpage by providing locking support and structural rigidity (paragraph 25) and protect the die (204) from environmental conditions, such as humidity, which can decrease the life of the device. Su does not disclose the third die in direct contact with the second encapsulant and the conductive connectors. However, Mallik discloses a third die (202/208) in direct contact with an encapsulant (224) and conductive connectors (222). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the third die of Su to be in direct contact with the encapsulant and conductive connectors, as taught by Mallik, since it can minimize complexity of processing TSVs and provide a structurally robust encapsulation of the IC die (paragraphs 15-16). Regarding claim 2, Su discloses the interconnect structure (92/94) is in direct contact with the second encapsulant (48) and the conductive connectors (32). Regarding claim 5, an embodiment of Su (Figure 15) discloses each of the conductive connectors (84/32) comprises a conductive post (32) and a conductive ball (84) connected to the conductive post (32), wherein the conductive post (32) is in direct contact with the second redistribution structure (connections below 32), and the conductive ball (84) is in direct contact with the third die (200). At least part, the conductive post (32) of the conductive connectors (84/32) is embedded in the second encapsulant (48) and surround the second die (34). Regarding claim 7, Su discloses an embodiment (Figure 15) in which each of the conductive connectors (84/32) comprises a conductive post (84) and a conductive cap (32) connected to the conductive post (84), the conductive cap (32) is in direct contact with the second redistribution structure (connections below 32), and the conductive post (84) is in direct contact with the third die (200). At least part, the conductive post (32) of the conductive connectors (84/32) is embedded in the second encapsulant (48) and surround the second die (34). Regarding claim 8, Su discloses conductive structures (56) surrounding the first die (58), wherein the conductive structures penetrate through the first encapsulant (66) to electrically connect the first redistribution structure (70) and the second redistribution structure (52). Regarding claim 9, Su discloses the first encapsulant (66) and the second encapsulant (48) are made of a same material (paragraphs 21 and 29 describe both encapsulants to be a molding compound). Claims 10-11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Publication No. 2017/0133351) in view of Song et al. (US Publication No. 2009/0321908), and further in view of Mallik et al. (US Publication No. 2023/0207545), and further in view of Yu et al. (US Publication No. 2021/0193582). Regarding claim 10, Su discloses a semiconductor package (Figures 12 and 15), comprising: a first redistribution structure (70) a first die (58) having an active surface and a rear surface opposite to the active surface, wherein the first die (58) is disposed on and electrically connected to the first redistribution structure (70) a first encapsulant (66) laterally encapsulating the first die (58) a second redistribution structure (52) disposed over the rear surface of the first die a second die (34) disposed on and electrically connected to the second redistribution structure (52), the second die (34) has an active surface (side facing 50) and a rear surface (side facing 94) opposite to the active surface conductive connectors (32) disposed on and electrically connected to the second redistribution structure (52) a second encapsulant (48) laterally encapsulating the conductive connectors (32) and the second die (34), wherein the second encapsulant (48) completely covers sidewalls of the conductive connectors (32) a third die (234) including interconnect structure (92) disposed on and in contact with the second encapsulant (48) and the conductive connectors (32) Su does not disclose the second encapsulant to be integrally formed with a portion of the second encapsulant sandwiched between the third die and the rear surface of the second die. However, Song discloses a die (204) formed in an encapsulant (218) which is integrally formed with conductive connectors (216 and 208) embedded (Figure 2), wherein a portion of the encapsulant (218) is sandwiched between the third die (220) and the rear surface of the second die (204). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the encapsulant of Su to be integrally formed, as taught by Song, since it can mitigate warpage by providing locking support and structural rigidity (paragraph 25). Su does not disclose the third die in direct contact with the second encapsulant and the conductive connectors. However, Mallik discloses a third die (202/208) in direct contact with an encapsulant (224) and conductive connectors (222). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the third die of Su to be in direct contact with the encapsulant and conductive connectors, as taught by Mallik, since it can minimize complexity of processing TSVs and provide a structurally robust encapsulation of the IC die (paragraphs 15-16). Su does not disclose the first die comprises TSVs protruding from its semiconductor substrate at the rear surface of the first die, which are in direct contact with the second distribution structure. However, Yu discloses first redistribution layer (206) with a first die (100) with TSVs (134/154) in direct physical and electrical contact with a second redistribution layer (240) at the rear surface of the first die (100) (Figure 15). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Su, to include a first die with TSVs, as taught by Yu, since it can they can improve signal throughput by minimizing the path from the first RDL (240) and second RDL (206), thereby improving speed and decreasing heat from the device (paragraphs 29-30). Regarding claim 11, Su discloses the active surface (side facing 50) of the second die (34) faces the second redistribution structure (52), and a portion of the second encapsulant (48 including DAF 38) is sandwiched between the third die (234) and the rear surface of the second die (34). Regarding claim 13, an embodiment of Su (Figure 15) discloses each of the conductive connectors (84/32) comprises a conductive post (32) and a conductive ball (84) connected to the conductive post (32), wherein the conductive post (32) is in direct contact with the second redistribution structure (connections below 32), and the conductive ball (84) is in direct contact with the third die (200). At least part, the conductive post (32) of the conductive connectors (84/32) is embedded in the second encapsulant (48) and surround the second die (34). Regarding claim 15, Su discloses an embodiment (Figure 15) in which each of the conductive connectors (84/32) comprises a conductive post (84) and a conductive cap (32) connected to the conductive post (84), the conductive cap (32) is in direct contact with the second redistribution structure (connections below 32), and the conductive post (84) is in direct contact with the third die (200). At least part, the conductive post (32) of the conductive connectors (84/32) is embedded in the second encapsulant (48) and surround the second die (34). Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Publication No. 2017/0133351) in view of Song et al. (US Publication No. 2009/0321908). Regarding claim 16, Su discloses a manufacturing method of a semiconductor package, comprising: providing a first redistribution structure (70) (Figure 5) placing a first die (58) on the first redistribution structure (70) (Figure 8) forming a first encapsulant (66) on the first redistribution structure (70) to laterally encapsulate the first die (Figure 7) forming a second redistribution structure (52) over the first die (58) and the first encapsulant (66) placing a second die (34) on the second redistribution structure (52) (Figure 5) attaching a third die (234/92) to the second redistribution structure (52) through conductive connectors (32), wherein the third die is over the second die encapsulating the second die (34) and the conductive connectors (32) by a second encapsulant (48) such that the second encapsulant (48) is in direct contact with the third die (234/92) Su does not disclose encapsulating the second die after the third is attached to the second redistribution structure. However, Song discloses forming a second die (304) and third die (302) attached to a redistribution structure (634), and then molding (632) around the connectors (316) and second die (304). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the encapsulating step to be after the third die is attached to the second redistribution, as taught by Song, since it can improve structural rigidity and therefore reliability of the device (paragraphs 25-26). Regarding claim 17, Su discloses at least a portion (202) of each conductive connector (32) is formed on the third die (234/92) prior to the attachment of the third die to the second redistribution structure (52) (Figures 10-11 show package 200 being already formed and connected to package 76, with connectors (202) already formed attached to the third die (234)). Regarding claim 18, Su discloses prior to the attachment of the third die (234/92) to the second redistribution structure (52), a first portion (32) of each conductive connector (32/202) is formed on the second redistribution structure (52), and a second portion (202) of each conductive connector (32/202) is formed on the third die (234) (paragraph 34). Regarding claim 19, Su discloses the first portion (32) comprises a conductive post or a conductive ball, and the second portion (202) comprises a conductive ball (ball 84 is connected to and a part of element 202). Regarding claim 20, Su discloses encapsulating (48) the second die (34) and encapsulating the conductive connectors (32) are performed simultaneously (Figure 4). Claims 3-4, 6, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US Publication No. 2017/0133351) in view of Song et al. (US Publication No. 2009/0321908), and further in view of Mallik et al. (US Publication No. 2023/0207545), and further in view of Lee et al. (US Publication No. 2018/0358288). Regarding claim 3, Su/Song/Mallik discloses the limitations as discussed in the rejection of claim 1 above. Su also discloses one end of the conductive connector (32) is in direct contact with the second redistribution structure (52), and another end of the conductive connector (32) is in direct contact with the third die (234/92). Su/Song/Mallik does not disclose each of the conductive connectors comprises a conductive ball. However, Lee discloses conductive connectors (120) comprising conducive balls (Figure 5). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive connectors of Su/Song/Mallik to comprise conductive balls, as taught by Lee, since they can behave as a buffer between differences in CTE, thereby improving conductive characteristics (paragraph 54). Regarding claim 4, Lee discloses the conductive ball (120) comprises a copper ball (120a) (paragraph 52), a nickel layer (120b) wrapping around the copper ball (120a), and a solder layer (120b) wrapping around the nickel layer (paragraph 57) (Claim 4 of Lee describes the solder buffer (120b) to include a multilayered structure of solder and nickel layers). Regarding claim 6, Su discloses the limitations as discussed in the rejection of claim 1 above. Su does not disclose each of the conductive connectors comprises conductive balls connecting the second redistribution structure and the third die. However, Lee discloses each of the conductive connectors (120) comprises a first conductive ball (120) and a second conductive ball (140b) connected to the first conductive ball (120), the first conductive ball is in direct contact with the second redistribution structure (RDL), and the second conductive ball (140b) is in direct contact with the third die (100b). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive connectors of Su to comprise conductive balls, as taught by Lee, since they can behave as a buffer between differences in CTE, thereby improving conductive characteristics (paragraph 54). Regarding claim 12, Su/Song/Mallik discloses the limitations as discussed in the rejection of claim 10 above. Su also discloses one end of the conductive connector (32) is in direct contact with the second redistribution structure (52), and another end of the conductive connector (32) is in direct contact with the third die (234/92). Su/Song/Mallik does not disclose each of the conductive connectors comprises a conductive ball. However, Lee discloses conductive connectors (120) comprising conducive balls (Figure 5). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive connectors of Su/Song/Mallik to comprise conductive balls, as taught by Lee, since they can behave as a buffer between differences in CTE, thereby improving conductive characteristics (paragraph 54). Regarding claim 14, Su/Song/Mallik discloses the limitations as discussed in the rejection of claim 10 above. Su/Song/Mallik does not disclose each of the conductive connectors comprises conductive balls connecting the second redistribution structure and the third die. However, Lee discloses each of the conductive connectors (120) comprises a first conductive ball (120) and a second conductive ball (140b) connected to the first conductive ball (120), the first conductive ball is in direct contact with the second redistribution structure (RDL), and the second conductive ball (140b) is in direct contact with the third die (100b). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive connectors of Su/Song/Mallik to comprise conductive balls, as taught by Lee, since they can behave as a buffer between differences in CTE, thereby improving conductive characteristics (paragraph 54). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 5/3/2026Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Show 10 earlier events
Oct 09, 2025
Request for Continued Examination
Oct 12, 2025
Response after Non-Final Action
Nov 03, 2025
Non-Final Rejection mailed — §103
Dec 12, 2025
Interview Requested
Jan 05, 2026
Applicant Interview (Telephonic)
Jan 06, 2026
Examiner Interview Summary
Feb 03, 2026
Response Filed
May 06, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.4%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 702 resolved cases by this examiner. Grant probability derived from career allowance rate.

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