DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/24/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (PG Pub. No. US 2021/0233997 A1) in view of Greene et al. (PG Pub. No. US 2017/0200807 A1).
Regarding claim 1, Chen teaches a semiconductor device structure (figs. 17A-17B among others), comprising:
a semiconductor substrate (¶ 0012: 50);
semiconductor channel sheets (¶ 0056: 55N and/or 55P) disposed over the semiconductor substrate (fig. 17A: 55N/55P disposed over 50);
source and drain regions (¶ 0013: 92), located beside the semiconductor channel sheets (fig. 17B: 92 located beside 55N and/or 55P);
a gate structure (¶ 0013: 85, including portions 112 and 114), disposed between the source and drain regions (fig. 17B: 112/114 disposed between 92) and disposed over and surrounding the semiconductor channel sheets (fig. 17A: 112/114 disposed around 55N and/or 55P), wherein the gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets (fig. 17: 112/114 comprises a top portion above 55N and/or above 55P, and a bottom portion between 55N and/or between 55P); and
sidewall spacers (¶ 0041: 81 and/or 83), disposed between the gate structure and source and drain regions (fig. 17B: 81/83 disposed between 112/114 and 92);
wherein the sidewall spacers located next to the top gate electrode structure have slant sidewalls extending from a topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers and outer perpendicular sidewall surfaces (¶ 0085, figs. 15C & 17B among others: at least 81 and/or 83 next to top portion of 112/114 include slant sidewalls and extend from topmost 55N/55P to tops of 81/83, which include outer perpendicular sidewall surfaces).
Chen does not explicitly teach the slant sidewalls with inner sidewall surfaces being slant and extending slantingly from the topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers.
Greene teaches a semiconductor device structure (figs. 9A-9D among others) including gate sidewall spacers (¶ 0060: 3, including dielectric material formed on a gate sidewall), the sidewall spacers including slant inner sidewall surfaces being slant and extending slantingly from a topmost channel region to tops of the sidewall spacers (figs. 9B, 9D: 3 includes slant extending continuously from height of 15 to tops of 3).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the slant inner spacer sidewall of Chen from the topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers, as a means to prevent pinching off a replacement gate metal layer and generating voids, eliminating the formation of a passageway through the gate structure that can transmit processing chemicals from one region of a substrate to another. (Greene, ¶ 0050).
Regarding claim 2, Chen in view of Greene teaches the structure of claim 1, wherein each of the sidewall spacers includes a first spacer (Chen, ¶ 0041: 83) and a second spacer (Chen, ¶ 0041: 81) disposed on the first spacer (Chen, fig. 17B: 81 disposed on 83), and the slant sidewalls of the first spacers extend slantingly and continuously from the topmost channel sheet to tops of the first spacers (Chen, fig. 17B: 83 comprises slant sidewalls as modified with the continuous slant of Greene, from 55N/55P to tops of 83), and the top gate electrode structure is in physical contact with the first spacers (Chen, figs. 15G, 17B: 112/114U in contact with 83).
Regarding claim 3, Chen in view of Kim teaches the structure of claim 2, wherein the gate structure includes a gate dielectric layer (Chen, ¶ 0013: 112) and a gate metallic layer (Chen, ¶¶ 0013, 0083-0084: 114, including metal-containing material of electrode layer 110), and the gate dielectric layer of the top gate electrode structure is in physical contact with the first spacers (Chen, fig. 15G: top portion of 112 proximal to 114U in physical contact with 83).
Regarding claim 4, Chen in view of Kim teaches the structure of claim 1, wherein each of the sidewall spacers includes a first spacer (Chen, ¶ 0041: 83) and a second spacer (Chen, ¶ 0041: 81) disposed on the first spacer, and the slant sidewalls of the first spacers extend slantingly and continuously from the topmost channel sheet to tops of the first spacers (Chen, fig. 17B: 83 comprises slant sidewalls as modified with the continuous slant of Greene, from 55N/55P to tops of 83), and the top gate electrode structure is in physical contact with the first spacers and the second spacers (Chen, figs. 15G, 17B: 112/114U in physical contact with 83 and 81).
Regarding claim 5, Chen in view of Kim teaches the structure of claim 4, wherein the gate structure includes a gate dielectric layer (Chen, ¶ 0013: 112) and a gate metallic layer (Chen, ¶¶ 0013, 0083-0084: 114, including metal-containing material of electrode layer 110), and the gate dielectric layer of the top gate electrode structure is in physical contact with the first spacers and the second spacers (Chen, figs. 15G, 17B: top portion of 112 in physical contact with 81 and 83).
Regarding claim 6, Chen in view of Kim teaches the structure of claim 1, wherein the top gate electrode structure has a first maximum width larger than a second maximum width of the lower gate electrode structures (Chen, fig. 15G: top portion of 112/114 has a first maximum width larger than a second maximum width of lower portion of 112/114), and the semiconductor channel sheets have a channel Length larger than the first maximum width (Chen, figs. 15G, 17B: 55N/55P have channel width larger than maximum width of upper portion of 112/114).
Regarding claim 8, Chen in view of Kim teaches the structure of claim 1, further comprising an interlayer dielectric layer (Chen, ¶ 0054: 96) disposed beside the sidewall spacers and covering the source and drain regions (Chen, fig. 17B: 96 disposed beside 81/83 and cover 92), wherein the source and drain regions are epitaxy source and drain terminals (Chen, ¶ 0013: 92 comprises epitaxial material).
Regarding claim 9, Chen in view of Kim teaches the structure of claim 1, further comprising lateral inner spacers (Chen, ¶ 0046: 90) located between the lower gate electrode structures and the source and drain regions (Chen, fig. 17B: 90 located between lower portions of 112/114 and 92).
Regarding claim 10, Chen in view of Kim teaches the structure of claim 1, wherein the semiconductor channel sheets include silicon or silicon germanium (Chen, ¶¶ 0021, 0056: 55N and/or 55P formed from layers of silicon or silicon germanium).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Kim as applied to claim 1 above, and further in view of Min et al. (PG Pub. No. US 2023/0070925 A1).
Regarding claim 7, Chen in view of Kim teaches the structure of claim 1, wherein the top gate electrode structure has a first maximum width, the lower gate electrode structures has a second maximum width (figs. 15G, 17B: top portion of 112/114 has a first maximum width, lower portion of 112/114 has a second maximum width), and the semiconductor channel sheets have a channel length larger than the first maximum width and the second maximum width (figs. 15G, 17B: maximum length of 55N larger than maximum widths of top and lower portions of 112/114).
Chen in view of Kim does not teach the first maximum width is substantially equivalent to the second maximum width.
Min teaches a structure (fig. 2B among others) including a top gate electrode structure (¶¶ 0064-0065: top portion of 120/130) has a first maximum width substantially equivalent to a second maximum width of lower gate electrode structures (fig. 2B: maximum width of top portion of 120/130 substantially equivalent to maximum with of lower portions of 120/130), and semiconductor channel sheets (¶ 0041: NS1) have a channel length larger than the first maximum width and the second maximum width (fig. 2B: length of NS1 in X1-axis direction larger than widths of top and lower portions of 120/130).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the top gate electrode of Chen in view of Kim with equivalent width to the lower gate electrode, as a means to allow for a wider lower gate electrode structure, improving current control capability of the semiconductor channels.
Furthermore, the Examiner notes that the limitation of claim 7 (“top gate electrode structure has a first maximum width substantially equivalent to a second maximum width of the lower gate electrode structures”) is mutually exclusive to the limitation of claim 6 (“the top gate electrode structure has a first maximum width larger than a second maximum width of the lower gate electrode structures”). Should the Applicant traverse on the grounds that the proposed modification is non-obvious, Applicant should submit evidence or identify such evidence now of record showing the inventions to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ramaswamy et al. (PG Pub. No. US 2021/0184045 A1) and Chang et al. (PG Pub. No. US 2021/0335613 A1).
Regarding claim 11, Chen teaches a structure (figs. 1 & 17A-17B among others), comprising:
a substrate (¶ 0012: 50) having a first region and a second region (¶ 0058 & fig. 17B: 50 comprises regions 50N and 50P);
first semiconductor channel sheets (¶¶ 0011, 0056: nano-structures 55N) disposed over the substrate and in the first region (fig. 17B: 55N disposed over 50 in region 50N);
second semiconductor channel sheets (¶¶ 0011, 0056: nano-structures 55P) disposed over the substrate and in the second region (fig. 17B: 55P disposed over 50 in region 50P);
source and drain regions (¶ 0013: 92), located at opposite sides of the first semiconductor channel sheets and at opposite sides of the second semiconductor channel sheets (fig. 17B: 92 located at opposite sides of 55N and opposite sides of 55P);
a first gate structure (¶ 0013: 112/114 in region 50N), disposed over and laterally surrounding the first semiconductor channel sheets (fig. 17A: 112/114 disposed over and laterally surround 55N);
first sidewall spacers (¶ 0041: 81 and/or 83) disposed between the first gate structure and the source and drain regions (fig. 17B: 81/83 disposed between 112/114 and 92 in region 50N), wherein the first sidewall spacers have slant sidewalls (figs. 15G, 17B: 81/83 in region 50N has slant sidewalls);
a second gate structure (¶ 0013: 112/114 in region 50P), disposed over and laterally surrounding the second semiconductor channel sheets (fig. 17A: 112/114 disposed over and laterally surrounds 55P);
a gate contact (¶ 0090: second 120) located on the second gate structure (fig. 18: second 120 located on 114 in region 50P); and
second sidewall spacers (¶ 0041: 81/83) disposed between the second gate structure and the source and drain regions (fig. 17B: 81/83 disposed between 112/114 and 92 in region 50P), wherein the second sidewall spacers have slant sidewalls (figs. 15C, 15G, 17B: 81/83 in region 50P has slant sidewalls),
wherein the second gate structure that is located above the second semiconductor channel sheets includes a lateral portion that is in contact with the second sidewall spacers and a central portion surrounded by the lateral portion (figs. 17A-17B: 112/114 in region 50P includes lateral portion contacting 81/83, and central portion surrounded by lateral portions).
Chen does not teach wherein the first semiconductor channel sheets have a first channel length shorter than a second channel length of the second semiconductor channel sheets, or a top surface of the lateral portion is higher than a top surface of the central portion, or the gate contact is in direct contact with the lateral portion of the second gate structure.
Ramaswamy teaches a structure (¶ 0026 & figs. 1A-1B among others: 100) including first semiconductor channel nanostructures (¶ 0027: 120) in a first region (112A) with a first channel length (¶ 0029: nanostructure channels 120 in region112A have channel length of LgA), and second semiconductor channel nanostructures (¶ 0027: 120) in a second region (112B) with a second channel length (¶ 0029: nanostructure channels 120 in region112B have channel length of LgB), wherein the first channel length is shorter than the second channel length (¶ 0029 & fig. 1A: LgA shorter than LgB).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first semiconductor channel sheets of Chen with a shorter channel length, as a means to provide a high-speed transistor (Ramaswamy, ¶ 0025), improving functionality and/or performance of the device in the first region.
Chen in view of Ramaswamy as modified above does not teach the second gate structure configured such that the top surface of the lateral portion is higher than the top surface of the central portion, or the gate contact is in direct contact with the lateral portion of the second gate structure.
Chang teaches a structure (¶ 0088 & fig. 22: 300B) including sidewall spacers (¶ 0036: 702 and/or 704) and a gate structure (¶ 0088: 1520D), the gate structure configured such that a top surface of a lateral portion proximal to the sidewall spacer is higher than a top surface of a central portion surrounded by the lateral portion (fig. 22: 1520D has concave top surface, such that top surface of portion 1102 proximal to 702/704 is higher than top surface of central portion of 1104), wherein a gate contact (¶ 0051: 1600) is in direct contact with the lateral portion of the gate structure (fig. 22: 1600 directly contacts lateral portion 1102).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second gate structure of Chen in view of Ramaswamy with the shape of Chang, as a means to provide a long-channel transistor (Chang, ¶ 0089), allowing for improved device integration and/or device functionality.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02.
Regarding claim 12, Chen in view of Ramaswamy and Chang teaches the structure of claim 11, wherein each of the first sidewall spacers includes a first sub-spacer (Chen, ¶ 0041: 81) and a second sub-spacer (Chen, ¶ 0041: 83) disposed on the first spacer (Chen, fig. 17B: 83 disposed on 81 in region 50N), and the first sub-spacers have slant sidewalls (Chen, fig. 17B: 81 in region 50N comprises slant sidewalls).
Regarding claim 13, Chen in view of Ramaswamy and Chang teaches the structure of claim 12, wherein the first gate structure that is located above the first semiconductor channel sheets is in physical contact with the slant sidewalls of the first sub-spacers (Chen, figs. 15G, 17B: top portion of 112/114 above 55N in contact with slant sidewalls of 81).
Regarding claim 14, Chen in view of Ramaswamy and Chang teaches the structure of claim 12, wherein the first gate structure that is located above the first semiconductor channel sheets is in physical contact with the slant sidewalls of the first sub-spacers and the second sub-spacers (Chen, figs. 15G, 17B: top portion of 112/114 above 55N in contact with slant sidewalls of 81and 83).
Regarding claim 15, Chen in view of Ramaswamy and Chang teaches the structure of claim 11, wherein the first gate structure that is located above the first semiconductor channel sheets has a maximum width larger than that of the first gate structure that is located below the first semiconductor channel sheets (Chen, figs. 15G, 17B: top portion of 112/114 above 55N has a maximum width larger than that of bottom portion of 112/114 around/below 55N).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ramaswamy and Chang as applied to claim 11 above, and further in view of Min.
Regarding claim 16, Chen in view of Ramaswamy and Chang teaches the structure of claim 11, the first gate structure that is located above the first semiconductor channel sheets, and the first gate structure that is located below the first semiconductor channel sheets has a second maximum width (Chen, figs. 15G, 17B: top portion of 112/114 has a first maximum width, lower portion of 112/114 has a second maximum width).
Chen in view of Ramaswamy and Chang does not teach the first maximum width is substantially equivalent to the second maximum width.
Min teaches a structure (fig. 2B among others) including a top gate electrode structure (¶¶ 0064-0065: top portion of 120/130) has a first maximum width substantially equivalent to a second maximum width of lower gate electrode structures (fig. 2B: maximum width of top portion of 120/130 substantially equivalent to maximum with of lower portions of 120/130).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the top gate electrode of Chen in view of Ramaswamy and Chang with equivalent width to the lower gate electrode, as a means to allow for a wider lower gate electrode structure, improving current control capability of the semiconductor channels.
Furthermore, the Examiner notes that the limitation of claim 16 (“the first gate structure that is located above the first semiconductor channel sheets has a maximum width substantially equivalent to that of the first gate structure that is located below the first semiconductor channel sheets”) is mutually exclusive to the limitation of claim 15 (“the first gate structure that is located above the first semiconductor channel sheets has a maximum width larger than that of the first gate structure that is located below the first semiconductor channel sheets”). Should the Applicant traverse on the grounds that the proposed modification is non-obvious, Applicant should submit evidence or identify such evidence now of record showing the inventions of claims to be non-obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a Restriction/Election Requirement. Where two or more related inventions are claimed, the principal question to be determined in connection with a requirement to restrict is whether or not the inventions as claimed are distinct. If they are distinct, restriction may be proper. See MPEP § 806.05 [R-08.2012].
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ramaswamy and Greene.
Regarding claim 21, Chen teaches a device structure (figs. 1 & 17A-17B among others), comprising:
a substrate (¶ 0012: 50) having a first region and a second region (¶ 0058 & fig. 17B: regions 50N, 50P);
first semiconductor channel sheets (¶¶ 0011, 0056: nano-structures 55N) disposed over the substrate and in the first region (fig. 17B: 55N disposed over 50 in region 50N);
second semiconductor channel sheets (¶¶ 0011, 0056: nano-structures 55P) disposed over the substrate and in the first region (fig. 17B: 55P disposed over 50 in region 50P);
source and drain regions (¶ 0013: 92), located at opposite sides of the first semiconductor channel sheets and at opposite sides of the second semiconductor channel sheets (fig. 17B: 92 located at opposite ends of 55N and 55P);
a dielectric layer (¶¶ 0054, 0088: 96 and/or 118), disposed over the substrate and over the source and drain regions (fig. 17B: 96/118 disposed over 50 and over regions 92);
a first gate structure (¶ 0013: 112/114 in region 50N), disposed over and around the first semiconductor channel sheets (fig. 17B: 112/114 disposed over and around 55N);
first sidewall spacers (¶ 0041: 81 and/or 83) disposed between the first gate structure and the source and drain regions (fig. 17B: 81/83 disposed between 112/114 and 92 in region 50N), wherein the first sidewall spacers have slant sidewalls extending from a topmost channel sheet of the first semiconductor channel sheets to tops of the first sidewall spacers (figs. 15G, 17B: 81 and/or 83 include slated sidewalls and extend from topmost 55N to tops of 81/83);
a second gate structure (¶ 0013: 112/114 in region 50P), disposed over and around the second semiconductor channel sheets (fig. 17B: 112/114 disposed over and around 55P); and
second sidewall spacers (¶ 0041: 81 and/or 83) disposed between the second gate structure and the source and drain regions (fig. 17B: 81/83 disposed between 112/114 and 92 in region 50P), wherein the second sidewall spacers have slant sidewalls with inner slant sidewall surfaces and extending from a topmost channel sheet of the second semiconductor channel sheets to tops of the second sidewall spacer (figs. 15G, 17B: 81 and/or 83 include slated inner sidewall surfaces and extend from topmost 55P to tops of 81/83).
Chen does not explicitly teach wherein channel lengths of the first semiconductor channel sheets and the second semiconductor channel sheets are different, or the slant inner sidewall surfaces including a continuous slant from the topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers and outer vertical sidewall surfaces.
Ramaswamy teaches a structure (¶ 0026 & figs. 1A-1B among others: 100) including first semiconductor channel nanostructures (¶ 0027: 120) in a first region (112A) with a first channel length (¶ 0029: nanostructure channels 120 in region112A have channel length of LgA), and second semiconductor channel nanostructures (¶ 0027: 120) in a second region (112B) with a second channel length (¶ 0029: nanostructure channels 120 in region112B have channel length of LgB), wherein the first channel length is different than the second channel length (¶ 0029 & fig. 1A: LgA shorter than LgB).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first and second semiconductor channel sheets of Chen with different channel lengths, as a means to provide a high-speed transistor (Ramaswamy, ¶ 0025), improving functionality and/or performance of the device in the first region.
Chen in view of Ramaswamy does not explicitly teach the slant inner sidewall surfaces including a continuous slant from the topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers and outer vertical sidewall surfaces.
Greene teaches a semiconductor device structure (figs. 9A-9D among others) including gate sidewall spacers (¶ 0060: 3, including dielectric material formed on a gate sidewall), the sidewall spacers including slant inner sidewall surfaces being slant and extending slantingly from a topmost channel region to tops of the sidewall spacers (figs. 9B, 9D: 3 includes slant extending continuously from height of 15 to tops of 3).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the slant inner spacer sidewall of Chen in view of Ramaswamy from the topmost channel sheet of the semiconductor channel sheets to tops of the sidewall spacers, as a means to prevent pinching off a replacement gate metal layer and generating voids, eliminating the formation of a passageway through the gate structure that can transmit processing chemicals from one region of a substrate to another. (Greene, ¶ 0050).
Regarding claim 22, Chen in view of Ramaswamy and Greene teaches the structure of claim 21, further comprising first sub-spacers (Chen, 81 and/or 94) located between the first sidewall spacers and the dielectric layer (Chen, fig. 17B: 81 and/or 94 located between 83 and 96), wherein the first sidewall spacers are sandwiched between the first sub-spacers and the first gate structure (Chen, fig. 17B: 83 sandwiched between 81/94 and 114/112).
Regarding claim 23, Chen in view of Ramaswamy and Greene teaches the structure of claim 21, wherein the first gate structure includes a first top gate electrode structure disposed above the first semiconductor channel sheets (Chen, fig. 17B: 12/114 comprises top portion disposed above 55N), and first lower gate electrode structures disposed between the first semiconductor channel sheets (Chen, fig. 17B: 112/114 comprises lower portions between 55N), and the first top gate structure is in physical contact with the first sidewall spacers (Chen, fig. 17B: top portion of 112/114 physically contacts 83).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ramaswamy and Greene as applied to claim 23 above, and further in view of Chang.
Regarding claim 24, Chen in view of Ramaswamy and Greene teaches the structure of claim 21, wherein the first top gate structure has a top surface (Chen, fig. 15G among others).
Chen in view of Ramaswamy and Greene fails to teach wherein the top surface of the first top gate structure is non-planar.
Chang teaches a structure (fig. 22: 300B) including sidewall spacers (¶ 0083: 702/704) and a gate structure (¶ 0089: 1520D), the gate structure including a non-planar top surface (¶ 0089 & fig. 22: 1520D has u-shaped cross-section).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first gate structure of Chen in view of Ramaswamy and Greene with a non-planar top surface, as a means to as a means to provide a long-channel transistor (Chang, ¶ 0089), allowing for improved device integration and/or device functionality.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 and 21-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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