Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments to claims 1, 3, 9, 10, and 16-18 to specify the spacers as “gate spacers” is acknowledged and is determined to overcome the rejection under 35 U.S.C. § 112(b) made in the previous office action dated 07/01/2025. Therefore, the rejection has been withdrawn.
Response to Arguments
Applicant's arguments filed 10/01/2025 have been fully considered but they are not persuasive.
Regarding the rejections of claims 1 and 12, the applicant argues in pg. 12 that the side portion of Wang fails to abut the gate dielectric. However, upon further consideration, Wang discloses that the capping layer comprises one or more of the following: “HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials” (Wang [0021]). These are high-k dielectric materials that are also known to serve as gate dielectric materials. The examiner therefore considers that capping layer 140 as part of the gate dielectric layer as it is materially, structurally, and functionally similar in nature.
The applicant further argues in pg. 7 of applicant’s remarks that the examiner’s application of MPEP 2144.05 or “routine optimization” is improper, citing that the argument is limited to the discussion of ranges. However, the examiner maintains the application of MPEP 2144.05 to be proper as this section of the MPEP is meant to apply to any result-effective variable. A claim falls under routine optimization when a known parameter (thickness, composition, or geometry) has a predictable relationship with another variable or goal (tuning of effective work function, affecting threshold voltages, device reliability, etc.). In this case, Erben discloses that the tuning of the work function of a gate stack is known in the art, and Wang teaches the ability to modify the lateral geometry of the gate stack in order to modify the work function of the gate stack, therefore, any adjustments made to the profile of the side portions to obtain a predictable result (fine tuning of desired work functions) is considered by the examiner to be within the scope of routine optimization and experimentation.
Regarding the use of both P-type and N-type metals in the same stack as recited in claims 4, 14, and 22, the examiner reiterates that Wang discloses the use of multiple work function metal layers for a metallic gate stack, where the work function of the metal layers can be distinct (Wang [0022]-[0023]). Upon further consideration and discussion, the office determines that the use of both P-type and N-type metals in the same gate stack raises some technical issues that may need correction as indicated in this office action.
Drawings
The drawings are objected to because Fig. 1 shows slice A-A to be directly intersecting the semiconductor fin 104, while Fig. 7 which is supposed to show the cross-sectional planar view along slice A-A shows details the suggest that slice A-A must be offset away from the semiconductor fin in order to show details of the gate structure 110 of Fig. 1 or gate structures of 600A, 600B, and 600C of Fig. 7. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claims 1-18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re: Claim 1, 6, and 11
The term “substantially” in claims 1, 6, and 11 is a relative term which renders the claims indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term substantial is defined as “being largely but not wholly that which is specified”. The term “substantially” modifies a target, implicitly requiring boundaries at some maximum value above said target and at some minimum value below said target beyond which one is no longer within the “substantially” range. As the Applicant has not provided a definition for these boundaries in the originally filed claims or the originally filed specification, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01%, 0.1%, 1%, 10%, etc.) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. Therefore the term is subjective and therefore unclear, and so the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
Re: Claim 1
Claim 1 recites the limitations “first distance” and “second distance” which refers to the extension of the interface between the metal gate structure and the gate electrode towards the semiconductor fin, where the first distance is understood to refer to the length of the extension of the side portion of the interface, while the second distance refers to the length of the central portion of the interface (Applicant’s disclosure, Fig. 17). However, it is unclear from where the distance is measured with respect to the semiconductor fin (as in with respect to what reference point?). In this case, Fig. 17, which is understood to be a slice of line A-A in Fig. 1, should have all the depicted elements be equidistant from the semiconductor fin, and therefore the side portion and central portions of the interface should have the same interface extension lengths, as this represents a plane of fixed distance from the semiconductor fin as shown in Fig. 1. Accordingly, the scope of the claim cannot be determined with reasonable certainty. For examination purposes, the distance of the side portion and central portion of the interface (first and second distance respectively), is interpreted as being similar to each other consistent with the applicant’s disclosure.
Claims 4, 14, and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999).
The terms “p-type work function metal” and “n-type work function metal” in claims 4 and 22 is used by the claim to mean “a metal of different work function values,” while the accepted meaning is “metal deposited on either a p-type or n-type semiconductor.” The term is indefinite because the specification does not clearly redefine the term.
The term “conductive types” in claim 14 is used by the claim to mean “a metal of different work function values,” while the accepted meaning is “metal deposited on either a p-type or n-type semiconductor.” The term is indefinite because the specification does not clearly redefine the term.
Re: Claims 4 and 22.
Claims 4 and 22 recite the limitations “p-type work function metal” and “n-type work function metal.” The examiner fails to comprehend what this means as metals are conductors whose main charge carriers are always going to be electrons and cannot be doped in order to modify or alter the main charge carriers. The terms "n-type” and “p-type" refer to doping polarities in semiconductors and as metals cannot be doped to be "n-type" or "p-type" it is unclear what is required of the claimed "n-type work function metal" and "p-type work function metal". All materials have a work function and the work function of a metal is a characteristic of the metal composition and its surface orientation. The work function of semiconductors can be altered by n-type or p-type doping because semiconductors have a band gap and doping with either n-type or p-type dopants will introduce energy states within the band gap that alter the work function of the semiconductor material to be closer to the conduction band edge (n-type doping with donor ions) or closer to the valence band edge (p-type doping with acceptor ions). Metals do not have a band gap so are incapable of work function tuning using n-type or p-type dopants. Thus it is unclear what applicant means when claiming "n-type work function metal" and "p-type work function metal.
For examination purposes, the examiner interprets these limitation to mean that the metal stack are deposited on either an n-type or p-type semiconductor, consistent with the usage as known in the art. Therefore, it would also be impossible to have both p-type and n-type metals on the same semiconductor channel as the channel must either be p-type or n-type and not simultaneously both.
Re: Claim 14.
Claim 14 recites the limitation “conductive types” where it is unclear what other conductive types a metal would have. For examination purposes, “conductive types” is interpreted by the examiner to mean different “metal work function” values.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
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Claims 1-5, and 8-10 are rejected under 35 U.S.C. 102(a) as being anticipated by Wang et al. (US 20210167179 A1), hereinafter referred to as Wang.
[AltContent: textbox (Exhibit 1: Fig. 2 of Wang showing a semiconductor device with semiconductor fin 204, first gate spacers 228, metal gate structure 224, gate electrode 226, and gate dielectric 222.)]
Regarding the independent Claim 1:
Wang teaches a semiconductor device, comprising: a semiconductor fin (Wang fig. 2, semiconductor fin 204);
first gate spacers over the semiconductor fin (Wang Fig. 2, first gate spacers 228);
a metal gate structure over the semiconductor fin (Wang fig. 2, metal gate structure 224 over semiconductor fin 204),
that is sandwiched at least by the first gate spacers (Wang Fig. 2, metal gate structure 224, gate spacers 228);
and a gate electrode contacting the metal gate structure (Wang Fig. 2, gate electrode 226).;
wherein an interface between the metal gate structure and the gate electrode has side portions abutting the gate dielectric and extending toward the semiconductor fin with a first distance (Wang Fig. 2, where side portion of interface between gate electrode 226 and metal gate structure 224 abuts gate dielectric 222 and extends towards the semiconductor fins 204 with a first distance.)
and a central portion extending toward the semiconductor fin with a second distance (Wang Fig. 2, where a central portion of interface between gate electrode 226 and metal gate structure 224 extends towards the semiconductor fins 204 with a second distance),
[AltContent: textbox (Exhibit 2: Fig. 11A of Wang, depicting a first work function metal 150, and a second work function metal 152.)]the first distance being substantially less than the second distance (Wang Fig. 2).
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Regarding Claim 2: Wang teaches the semiconductor device of claim 1.
Wang further teaches the device wherein the metal gate structure comprises: a first work function metal; and a second work function metal (Wang Fig. 11A, (150, 152), [0022]-[0023], “The gate electrode 124 may include one or more metal layers, such as work function metal (WFM) layer(s)… the metal layers 150 and 152 may be two distinct WFM layers”).
Regarding Claim 3: Wang teaches the semiconductor device of claim 2.
Wang further teaches the device wherein a lower boundary of the side portions are, defined by a lowest portion of top surfaces of the first work function metal, wherein the second work function (Wang Fig. 11A, [0022]-[0023], side portions lower boundary defined by lowest portion of top surface of the first work function metal.).
Regarding Claim 4: Wang teaches the semiconductor device of claim 2.
Wang further teaches the device wherein the first work function metal has a p-type work function metal, and the second work function metal has an n-type work function metal (Wang [0022], “The WFM layer may be a p-type or an n-type work function layer depending on the type of the device (PMOS or NMOS) desired... the metal layers 150 and 152 may be two distinct WFM layers,”).
Regarding Claim 5: Wang teaches the semiconductor device of claim 2.
Wang further teaches the device wherein the first work function metal has a first U-shaped profile, and the second work function metal has a second U-shaped profile at least partially enclosed by the first U-shaped profile (Wang Fig. 11A, U-shaped work function metal layers, 150 and 152, where second work function metal layer 152 is at least partially enclosed by first work function metal layer 150)
Regarding Claim 8: Wang teaches the semiconductor device of claim 1.
Wang further teaches the semiconductor device wherein the metal gate structure comprises a plurality of work functions metals that have respectively different conductive type (Wang [0022]-[0023], “The gate electrode 124 may include one or more metal layers, such as work function metal (WFM) layer(s)… the metal layers 150 and 152 may be two distinct WFM layers”),
and the gate electrode includes tungsten (Wang [0047], gate electrode 126, referred to as a conductive layer by Wang, “In some embodiments, the conductive layer includes metallic tungsten.)
Regarding Claim 9: Wang teaches the semiconductor device of claim 1.
Wang further teaches the device further comprising: second gate spacers over the semiconductor fin, the second gate spacers extending farther from the semiconductor fin than the first gate spacers; wherein the first gate spacers are further sandwiched by the second gate spacers (Wang Fig. 11A, second gate spacers 110 sandwiching first gate spacers ).
Regarding Claim 10: Wang teaches the semiconductor device of claim 9.
Wang further teaches the gate electrode has its sidewalls in direct contact with inner sidewalls of the first spacers, respectively (Wang Fig. 11A, gate electrode 126 in contact with inner sidewalls of first gate spacer 128. The examiner broadly interprets “contact” to include other kinds of contact such as indirect contact or thermal contact.).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6-7, 11-18, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang and in further view of Erben et al. (http://dx.doi.org/10.5772/intechopen.78335, 2018), hereinafter referred to as Erben.
Regarding Claim 6: Wang teaches the semiconductor device of claim 1.
Wang further teaches the device wherein the gate electrode includes a first height extending from the side to a top surface of the gate electrode (Wang Fig. 13B gate electrode 126 with sides 176 and 178 includes a first height),
and a second height extending from the central portion to the top surface of the gate electrode (Wang Fig. 13B gate electrode 126 with central portion includes a second height),
and wherein the first height is substantially greater than the second height (Wang Fig. 13B side portion 176 and 178 have first height greater than second height. The height in this is case is interpreted by the examiner as referring to the thickness of the gate electrode 126.).
Wang fails to teach the first height being measured from the side portion of the gate electrode.
However, in a related field of endeavor, Erben teaches that work function of a metal gate can be tuned by changing the composition, thickness, or deposition techniques of the metal gate (Erben pg. 32 “Aluminum with a work function of 4.1 eV is a suitable material for NMOS transistors. One possible material for PMOS transistors is TiN. The work function of TiN can be tuned close to 5 eV depending on the detailed composition of TiN, like the Ti to N ratio, the TiN thickness, and the deposition techniques.”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Erben to the disclosure of Wang, to understand that the process of Wang, which can control the lateral etching rates of specific metal layers to produce various lateral profiles for the metal gate structure, could be further adjusted to specifically target the side portion of the metal gate structure that is closest to the gate dielectric in order to modify the work function of the metal gate structure. This is obvious to try as Erben teaches that the work function of the metal gate structure directly affects the device threshold voltage and therefore affect the performance characteristics of the semiconductor device (Erben Introduction “required gate voltage to turn the transistor on (to form the inversion channel)—the threshold voltage Vt—is defined by the work functions of the transistor channel semiconductor and the gate electrode”).
Furthermore, since the disclosure of Wang teaches that the lateral profile of the metal gate structure can be modified with known methods as disclosed, and the disclosure of Erben teaches that the geometry of the gate is known in the art to affect the threshold voltage of the device, the examiner considers the modification of the device structure, using known methods in the art, to achieve a desired geometry to fine tune the work function of the metal gate structure as a routine optimization of a result-effective variable with a reasonable expectation of success.
Regarding Claim 7: The combined disclosure of Wang and Erben teaches the semiconductor device of claim 6.
Wang further teaches the device wherein a ratio of the second height to the first height is about 1.8 (Wang Fig. 13B, [0039] “T1 measures between about 1 nm and about 3mn, while T2 measures between about 2 nm and about 8 nm.”).
Here the examiner refers to T1 and T2 of fig. 13B of Wang’s disclosure. The examiner interprets the first height to equal T1 + T2 (H1 = T1 +T2), and the second height to equal T1 (H2 = T1). Since the ratio is greater than 1 and H2 is less than H1, the proper form of the ratio is H1/H2. Using the disclosure of Wang, letting T1 = 3 nm and T2 = 2.4 nm, we can get the ratio H1/H2 = 1.8.
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Exhibit 3: Fig. 13A and 13B of Wang depicting the ability to control the etch rates of specific metals and the ability to modify the lateral profile of the gate metal structure comprising of 150, 152, 154. The dielectric layer comprising of 140 and 122.
Regarding the independent Claim 11:
Wang teaches a semiconductor device comprising a semiconductor fin (Wang fig. 2, semiconductor fin 204);
A gate dielectric (Wang fig. 2, gate dielectric 222)
A metal gate structure, in contact with the gate dielectric disposed over the semiconductor fin (Wang Fig. 2, metal gate structure 224 in contact with gate dielectric 222, disposed over fin 204);
and a gate electrode having a bottom surface contacting an upper surface of the metal gate structure (Wang Fig. 2, gate electrode 226 contacting upper surface of metal gate structure 224.);
wherein the gate electrode has side portions abutting the gate dielectric and extending from its top surface toward the semiconductor fin with a first depth (Wang Fig. 2, gate electrode 226, with side portions abutting the gate dielectric 222, and extends towards semiconductor fin with a first depth where the examiner interprets side portions as any portion of the element that is off-center);
and a central portion extending from its top surface toward the semiconductor fin with a second depth (Wang Fig. 2, central portion gate electrode 226 extending toward semiconductor fin with a second depth wherein the examiner interprets the central portion as the portion that is aligned with the center.);
the first depth being substantially greater than the second depth (Wang Fig. 13B where side portions of the 176 and 178 of gate electrode 126 have greater depth than the central portion of gate electrode 126.).
Wang fails to teach wherein the side portion that is abutting the gate dielectric has the first depth greater than the second depth.
However, in a related field of endeavor, Erben teaches that work function of a metal gate can be tuned by changing the composition, thickness, or deposition techniques of the metal gate (Erben pg. 32 “Aluminum with a work function of 4.1 eV is a suitable material for NMOS transistors. One possible material for PMOS transistors is TiN. The work function of TiN can be tuned close to 5 eV depending on the detailed composition of TiN, like the Ti to N ratio, the TiN thickness, and the deposition techniques.”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Erben to the disclosure of Wang, to understand that the process of Wang, which can control the lateral etching rates of specific metal layers to produce various lateral profiles for the metal gate structure, could be further adjusted to specifically target the side portion of the metal gate structure that is abutting the gate dielectric in order to modify the work function of the metal gate structure. This is obvious to try as Erben teaches that the work function of the metal gate structure directly affects the device threshold voltage and therefore affect the performance characteristics of the semiconductor device (Erben Introduction “required gate voltage to turn the transistor on (to form the inversion channel)—the threshold voltage Vt—is defined by the work functions of the transistor channel semiconductor and the gate electrode”).
Furthermore, since the disclosure of Wang teaches that the lateral profile of the metal gate structure can be modified with known methods, and the disclosure of Erben teaches that the geometry of the gate is known in the art to affect the threshold voltage of the device, the examiner considers the modification of the device structure, using known methods in the art, to achieve a desired geometry to fine tune the work function of the metal gate structure as a routine optimization of a result-effective variable with a reasonable expectation of success.
Regarding Claim 12: The combined disclosure of Wang and Erben teach the semiconductor device of claim 11.
Wang further teaches the device wherein the metal gate structure comprises: a first work function metal having a first U-shaped profile (Wang Fig. 4A, U-shaped first work function metal (150), [0022]-[0023], “The gate electrode 124 may include one or more metal layers, such as work function metal (WFM) layer(s)… the metal layers 150 and 152 may be two distinct WFM layers”);
and a second work function metal having a second U-shaped profile (Wang Fig. 4A, U-shaped second work function metal (152), [0022]-[0023]),
wherein the second work function metal is at least partially enclosed by the first work function metal (Wang Fig. 4A, U-shaped work function metal layers, 150 and 152, where second work function metal layer 152 is at least partially enclosed by first work function metal layer 150).
Regarding Claim 14: The combined disclosure of Wang and Erben teach the semiconductor device of claim 12.
Wang further teaches the device wherein the first work function metal and second work function metal have respectively different conductive types (Wang [0022], “The WFM layer may be a p-type or an n-type work function layer depending on the type of the device (PMOS or NMOS) desired... the metal layers 150 and 152 may be two distinct WFM layers,”).
The examiner interprets the disclosure of Wang as an indication that being able to modify and combine distinct work function metal layers is known in the art, and the process of attaining the desirable operating characteristics such as the desirable threshold voltage, is attainable via routine optimization and experimentation.
Regarding Claim 15: The combined disclosure of Wang and Erben teach the semiconductor device of claim 11.
Wang further teaches the device wherein a ratio of the second depth to the first depth is about 1.8 (Wang Fig. 13B, [0039] “T1 measures between about 1 nm and about 3mn, while T2 measures between about 2 nm and about 8 nm.”).
Here the examiner refers to T1 and T2 of fig. 13B of Wang’s disclosure. The examiner interprets the first height to equal T1 + T2 (H1 = T1 +T2), and the second height to equal T1 (H2 = T1). Since the ratio is greater than 1 and H2 is less than H1, the proper form of the ratio is H1/H2. Using the disclosure of Wang, letting T1 = 3 nm and T2 = 2.4 nm, we can get the ratio H1/H2 = 1.8.
Regarding Claim 16: The combined disclosure of Wang and Erben teach the semiconductor device of claim 11.
Wang further teaches the device comprising first gate spacers sandwiching the metal gate structure and the gate electrode (Wang Fig. 2, spacers 228 sandwiching metal gate 220).
Regarding Claim 17: The combined disclosure of Wang and Erben teach the semiconductor device claim 16.
Wang further teaches the device wherein the gate electrode has its sidewalls in direct contact with inner sidewalls of the first gate spacers, respectively (Wang Fig. 9A, sidewalls of gate electrode 126 in direct contact with inner side walls of first gate spacers 122, where direct contact is interpreted by the examiner to include thermal contact, electrical contact or with intermediary elements of similar or different material composition.).
Regarding Claim 18: The combined disclosure of Wang and Erben teaches the semiconductor device of claim 16.
further comprising: second gate spacers further sandwiching the first gate spacers; wherein the second gate spacers extend farther from the semiconductor fin than the first gate spacers (Wang Fig. 9A, second gate spacers 128).
Regarding the independent Claim 21:
Wang teaches a system comprising: a semiconductor fin (Wang fig. 2, semiconductor fin 204);
A gate dielectric (Wang Fig. 2, gate dielectric 222)
a first work function metal, over the gate dielectric (Wang Fig. 13B, first work function metal 150 over the gate dielectric comprising of 140 and 122 where the examiner considers the capping layer 140 to be part of the gate dielectric.); ,
that includes a lateral portion coupling first vertical sidewalls at opposite ends of a first lateral direction (Wang Fig. 13B, first work function metal 150 has first vertical sidewalls on opposite sides in the lateral direction);
and a second work function metal, over the first work function metal, that includes a lateral portion coupling second vertical sidewalls at opposite ends of the first lateral direction (Wang Fig. 13B, second work function metal 152 has second vertical sidewalls on opposite sides in the lateral direction,
wherein an outer surface of the second vertical sidewalls are in contact with an inner surface of the first vertical sidewalls (Wang Fig. 13B, First work function metal 150 and second work function metal 152 in contact with each other.)
Wang fails to teach that the second vertical sidewalls extend above an uppermost portion of the first vertical sidewalls.
However, in a related field embodiment as depicted in Fig. 13A, Wang discloses a device wherein the deeper portion of the gate electrode is located at the central portion over the core metal layer 154 (Wang Fig. 13A). Therefore, Wang exhibits the ability to control where the location of the deeper portion of the gate electrode could be placed.
In a related field of endeavor, Erben teaches that the tuning of the effective work function of a metal gate material is dependent on the thickness of the material (Erben pg. 32, “One possible material for PMOS transistors is TiN. The work function of TiN can be tuned close to 5 eV depending on the … the TiN thickness…”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, that Wang could have modified the placement of deeper portions 176 and 178 such that the second vertical sidewalls extend above an uppermost portion of the first vertical sidewalls. This allows Wang to choose which metal work function layer to modify in order to be able to tune the effective work function of the gate stack. This is obvious to try, as Erben discloses that modifying the thickness of a metal gate material allows for the tuning of the work function of the metal layer (Erben pg. 32).
Regarding Claim 22: The combined disclosure or Wang and Erben teaches the system of claim 21.
Wang further teaches the system wherein the first work function metal is a p-type work function metal, and the second work function metal is an n-type work function metal (Wang [0022], “The WFM layer may be a p-type or an n-type work function layer depending on the type of the device (PMOS or NMOS) desired... the metal layers 150 and 152 may be two distinct WFM layers,”).
The examiner interprets the disclosure of Wang as an indication that being able to modify and combine work function metal layers of a various types (P-type or N-type), is known in the art, and the process of attaining the desirable operating characteristics such as the desirable threshold voltage, is attainable via routine optimization and experimentation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899