DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 17.
Pending: 1-20.
Withdrawn: 11-20.
Response to Amendment
The Amendment filed on 12/18/2025 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment"
with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 12/18/2025, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 10930745 B1A1 to Lin, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,4,6,9 and 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 20200176457 A1, of the record), in view of Chan et al. (Extraction of bulk and interface trap densities in amorphous InGaZnO thin-film transistors, 2016, J. Vac. Sci. Technol. B 34, 060601, of the record) in view of Izmailov et al. (Deep electron traps in HfO2-based ferroelectrics: (Al/Si-doped) HfO2 versus HfZrO4, 2022, Solid-State Electronics, Volume 194, 108388, of the record) and further in view of Lin et al. (US 10930745 B1).
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Re: Independent Claim 1, Sharma discloses a transistor, comprising:
Sharma’s Figure 1-Annotated.
a first gate electrode (110 a first gate electrode in [0024], Fig. 1);
a ferroelectric layer (120 a ferroelectric layer in [0027], Fig. 1) disposed over the first gate electrode (110);
a channel layer (130 a channel layer with source and drain regions made of IGZO in [0028], Fig. 1) disposed on the ferroelectric layer (120);
a second gate electrode (170 a second gate electrode in [0033], Fig. 1) disposed over the channel layer (130); and
a hole supply layer (160 a gate dielectric made of high-κ dielectric material such as hafnium dioxide in [0032], Fig. 1) located between the second gate electrode (170) and the channel layer (130); and
a metal layer (a diffusion barrier as part of 110 made of a metal in [0025], Fig. 1) sandwiched between the ferroelectric layer (120, Fig. 1) and the first gate electrode (110, Fig. 1),
Sharma does not expressly disclose wherein an electron trap density of the hole supply layer (160, HfO2) is higher than an electron trap density of the channel layer (130, IGZO) and wherein the metal layer and the first gate electrode have different widths.
However, in the same semiconductor device field of endeavor, Chan discloses an electron trap density of IGZO of 6.27x 1017 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chan’s feature of an electron trap density of IGZO of 6.27x 1017 to Sharma’s device to tune the electrical properties of the transistor (Pag. 1, Col. 1, lines 2-7, Chan).
In addition, in the same semiconductor device field of endeavor, Izmailov discloses an electron trap density of HfO2 in order of 1019 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Izmailov’s feature of an electron trap density of HfO2 in order of 1019 to Sharma’s device to facilitate electron injection and trapping (Pag. 1, Col. 1, lines 5-7, Izamailov).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chan and Izmailov features to Sharma’s device to an electron trap density of the hole supply layer is higher than an electron trap density of the channel layer to tune the electrical properties of the transistor (Pag. 1, Col. 1, lines 2-7, Chan).
Still, Sharma modified by Chan and Izmailov does not expressly disclose wherein the metal layer and the first gate electrode have different widths.
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Lin’s Figure 2-Annotated.
However, in the same semiconductor device field of endeavor, Lin discloses a metal layer (122 gate metal layer in Col. 4, lines 40-41, Fig. 2) and the first gate electrode (121 gate electrode in Col. 4, line 40) have different widths (122 has a width greater than 121, Fig. 2-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature wherein the metal layer and the first gate electrode have different widths to Sharma’s device to reduce the risk of high electric fields on gate structure, and to optimize the electric field distribution and effectively reduce the gate-to-drain capacitance (Col. 3, lines 18-22, Lin).
Re: Claim 2, Sharma modified by Chan, Izmailov and Lin discloses the transistor of claim 1, wherein the metal layer (122 in Fig. 2, Lin) has a width greater (W122 is greater W121, Fig. 2-Annotated) than a width of the first gate electrode (121 in Fig. 2, Lin).
Re: Claim 4, Sharma modified by Chan, Izmailov and Lin discloses the transistor of claim 1, further comprising source/drain contacts (140-150 source electrode 140 and drain electrode 150 in [0033], Fig. 1, Sharma) disposed aside the second gate electrode (170, Sharma) and the hole supply layer (160, Sharma), wherein the source/drain contacts (140-150, Sharma) are in physical contact with the channel layer (source and drain regions included in channel layer 130, Fig. 1, Sharma).
Re: Claim 6, Sharma modified by Chan, Izmailov and Lin discloses the transistor of claim 4, wherein the source/drain contacts (140-150, Sharma) are located within a span (Fig. 1, Sharma) of the first gate electrode (110, Sharma).
Re: Claim 9, Sharma modified by Chan, Izmailov and Lin discloses the transistor of claim 1, wherein a bandgap of the hole supply layer (160, Sharma) ranges from about 4 eV to about 6 eV (bandgap of HfO2 in a range of 5.3 to 6eV, Sharma).
Re: Claim 10, Sharma modified by Chan, Izmailov and Lin discloses the
transistor of claim 1, wherein a material of the hole supply layer (160, Sharma) comprises HfO2, TiO2, A1203, Si3N4, and Ta2O5 (160 made of HFO2, Sharma).
Claim(s) 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sharma, in view of Chan in view of Izmailov in view of Lin and further in view of Yuan et al. (US 20210257393 A1, of the record).
Re: Claim 3, Sharma modified by Chan, Izmailov and Lin discloses the
transistor of claim 1,
Sharma modified by Chan, Izmailov and Lin does not expressly disclose wherein the second gate electrode extends beyond one edge of the first gate electrode.
However, in the same semiconductor device field of endeavor, Yuan discloses
the second gate electrode (3 gate electrode in [0041], Fig. 3) extends beyond one edge (Fig. 3) of the first gate electrode (1 gate electrode in [0041], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yuan’s feature wherein the second gate electrode extends beyond one edge of the first gate electrode to the combination of Sharma, Chan, Izmailov and Lin to tune the area occupied of the transistor in a device ([0005], Yuan).
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sharma, in view of Chan in view of Izmailov in view of Lin and further in view of Zhu et al. (US 20200194557 A1, of the record).
Re: Claim 5, Sharma modified by Chan, Izmailov and Lin discloses the
transistor of claim 4,
Sharma modified by Chan, Izmailov and Lin does not expressly disclose
wherein the source/drain contacts are located outside of a span of the first gate electrode.
However, in the same semiconductor device field of endeavor, Zhu discloses
wherein the source/drain contacts (122-124 source terminal 122 and drain terminal 124 in [0024], Fig. 1C) are located outside of a span of the first gate electrode (316 bottom gate 124 in [0026], Fig. 1C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zhu’s feature of the source/drain contacts are located outside of a span of the first gate electrode to the combination of Sharma, Chan, Izmailov and Lin to isolate the embedded bottom gate ([0026], Zhu).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sharma, in view of Chan in view of Izmailov in view of Lin and further in view of Miyake (US 20200052129 A1, of the record).
Re: Claim 7, Sharma modified by Chan, Izmailov and Lin discloses the
transistor of claim 4,
Sharma modified by Chan, Izmailov and Lin does not expressly disclose
wherein one of the source/drain contacts is located within a span of the first gate electrode, and another one of the source/drain contacts is located outside of the span of the first gate electrode.
However, in the same semiconductor device field of endeavor, Miyake discloses wherein one of the source/drain contacts (30 source wiring 30 in [0042], Fig. 4) is located within (Fig. 4) a span of the first gate electrode (16 gate electrode in [0038], Fig. 4), and another one of the source/drain contacts (32 drain wiring 32 in [0042], Fig. 4) is located outside of the span of the first gate electrode (16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Miyake’s feature of one of
the source/drain contacts is located within a span of the first gate electrode, and another one of the source/drain contacts is located outside of the span of the first gate electrode to the combination of Sharma, Chan/Izmailov to suppress change in the characteristics of the thin film transistor ([0038], Miyake).
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sharma, in view of Chan in view of Izmailov in view of Lin and further in view of Wu et al. (US 20230360971 A1, of the record).
Re: Claim 8, Sharma modified by Chan, Izmailov and Lin discloses the
transistor of claim 1,
Sharma modified by Chan, Izmailov and Lin does not expressly disclose wherein the hole supply layer covers a bottom surface and sidewalls of the second gate electrode.
However, in the same semiconductor device field of endeavor, Wu discloses
wherein the hole supply layer (622 gate dielectric made of HfO2 in [0041,0046], Fig. 11A) covers a bottom surface and sidewalls of the gate electrode (621, [0045], Fig.11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wu’s feature wherein the hole supply layer covers a bottom surface and sidewalls of the second gate electrode to the combination of Sharma, Chan, Izmailov and Lin to isolate the gate electrode (Fig. 11A, Wu).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sharma (US 20210066509 A1) teaches “MULTI-GATE THIN FILM TRANSISTOR MEMORY”. This document is related to a transistor having a double gate electrode and one of the gate dielectrics made of high-k dielectric material.
Vega et al. (US 20220209018 A1) teaches “FIELD EFFECT TRANSISTOR (FET) DEVICES”. This document is related to a field effect transistor (FET) having an isolation region that separates a first back gate from a second back gate, a gate dielectric layer on a first channel region and a second channel region and a ferroelectric layer on the gate dielectric layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898