DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/23/2026 has been entered.
Response to Amendment
The Amendment filed on 04/23/2026 has been entered.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment"
with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 04/23/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20230411390 A1 to O'Brien, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,9 and 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O'Brien et al. (US 20230411390 A1), in view of Chan et al. (Extraction of bulk and interface trap densities in amorphous InGaZnO thin-film transistors, 2016, J. Vac. Sci. Technol. B 34, 060601, of the record) and further in view of Izmailov et al. (Deep electron traps in HfO2-based ferroelectrics: (Al/Si-doped) HfO2 versus HfZrO4, 2022, Solid-State Electronics, Volume 194, 108388, of the record).
Re: Independent Claim 1, O'Brien discloses a transistor, comprising:
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O'Brien’s Figure 1A-Annotated.
a first gate electrode (116 a back gate electrode in [0011], Fig. 1A);
a ferroelectric layer (104 a layer formed a HfO.sub.2 as a ferroelectric material in [0010], Fig. 1A) disposed over the first gate electrode (116);
a channel layer (108 a channel layer made of IGZO in [0011], Fig. 1A) disposed on the ferroelectric layer (104);
a second gate electrode (114 a top gate electrode in [0011], Fig. 1A) disposed over the channel layer (108); and
a hole supply layer (110 a gate dielectric made of high-κ dielectric material such as hafnium dioxide in [0011], Fig. 1A) located between the second gate electrode (114) and the channel layer (108); and
a metal layer (102 a metal layer in [0011], Fig. 1A) sandwiched between the ferroelectric layer (104, Fig. 1A) and the first gate electrode (116, Fig. 1A), wherein the metal layer (102) has a width along a first direction (x-direction-horizontal- Fig. 1A-Annotated) greater (Fig. 1A) than a width of the first gate electrode (116) along the first direction (x-direction).
O'Brien does not expressly disclose wherein an electron trap density of the hole supply layer (110, HfO2) is higher than an electron trap density of the channel layer (108, IGZO).
However, in the same semiconductor device field of endeavor, Chan discloses an electron trap density of IGZO of 6.27x 1017 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chan’s feature of an electron trap density of IGZO of 6.27x 1017 to O'Brien’s device to tune the electrical properties of the transistor (Pag. 1, Col. 1, lines 2-7, Chan).
In addition, in the same semiconductor device field of endeavor, Izmailov discloses an electron trap density of HfO2 in order of 1019 (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Izmailov’s feature of an electron trap density of HfO2 in order of 1019 to O'Brien’s device to facilitate electron injection and trapping (Pag. 1, Col. 1, lines 5-7, Izamailov).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chan and Izmailov features to O'Brien’s device to an electron trap density of the hole supply layer is higher than an electron trap density of the channel layer to tune the electrical properties of the transistor (Pag. 1, Col. 1, lines 2-7, Chan).
Re: claim 2, O'Brien modified by Chan and Izmailov discloses the transistor of claim 1,
O'Brien modified by Chan and Izmailov does not disclose wherein a length of the metal layer along a second direction is less than a length of the first gate electrode along the second direction.
However, the Applicant has not presented persuasive evidence that the claimed
“length of the metal layer along a second direction less than a length of the first gate electrode along the second direction” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed length of the metal layer along a second direction less than a length of the first gate electrode along the second direction). Also, the applicant has not shown that the claimed “difference of a length of the metal layer along a second direction less than a length of the first gate electrode along the second direction” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, O'Brien discloses “a length of the metal layer along a second direction similar than a length of the first gate electrode along the second direction”, therefore, the length is a result effective variable. It has been held that is not inventive to discover the optimum length relation between the metal layer and the first gate electrode by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a length of the metal layer along a second direction less than a length of the first gate electrode along the second direction to the rest of the claimed invention to tune the design characteristics of the device.
Re: Claim 9, O’Brien modified by Chan and Izmailov discloses the transistor of claim 1, wherein a bandgap of the hole supply layer (110, O’Brien) ranges from about 4 eV to about 6 eV (bandgap of HfO2 in a range of 5.3 to 6eV, O’Brien).
Re: Claim 10, O’Brien modified by Chan and Izmailov discloses the transistor of claim 1, wherein
a material of the hole supply layer (110, O’Brien) comprises HfO2, TiO2, A1203, Si3N4, and Ta2O5 (110 made of HFO2, O’Brien).
Claim(s) 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O’Brien, in view of Chan in view of Izmailov and further in view of Yuan et al. (US 20210257393 A1, of the record).
Re: Claim 3, O’Brien modified by Chan and Izmailov discloses the transistor of claim 1,
O’Brien modified by Chan and Izmailov does not expressly disclose wherein the second gate electrode extends beyond one edge of the first gate electrode.
However, in the same semiconductor device field of endeavor, Yuan discloses
the second gate electrode (3 gate electrode in [0041], Fig. 3) extends beyond one edge (Fig. 3) of the first gate electrode (1 gate electrode in [0041], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yuan’s feature wherein the second gate electrode extends beyond one edge of the first gate electrode to the combination of O’Brien, Chan and Izmailov to tune the area occupied of the transistor in a device ([0005], Yuan).
Claim(s) 4 and 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O’Brien, in view of Chan in view of Izmailov and further in view of Sharma et al. (US 20200176457 A1, of the record).
Re: Claim 4, O’Brien modified by Chan and Izmailov discloses the transistor of claim 1, further comprising source/drain contacts (112A-B source/drain regions made of metal in [0011], Fig. 1A, O’Brien) disposed aside the hole supply layer (110, O’Brien), wherein the source/drain contacts (112A-B, O’Brien) are in physical contact with the channel layer (source and drain regions included in channel layer 108, Fig. 1A, O’Brien).
O’Brien modified by Chan and Izmailov does not expressly disclose source/drain contacts (112A-B source/drain regions made of metal in [0011], Fig. 1A, O’Brien) disposed aside the second gate electrode (114, O’Brien).
However, in the same semiconductor device field of endeavor, Sharma discloses
source/drain contacts (140-150 source electrode 140 and drain electrode 150 in [0033], Fig. 1, Sharma) disposed aside the second gate electrode (170, Sharma).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Sharma’s feature wherein source/drain contacts disposed aside the second gate electrode to the combination of O’Brien, Chan and Izmailov to better current on-off ratio, which helps with detectability of separate states when used as a memory system ([0012], Sharma).
Re: Claim 6, O'Brien modified by Chan, Izmailov and Sharma discloses the transistor of claim 4,
O’Brien modified by Chan, Izmailov and Sharma does not expressly disclose wherein the source/drain contacts are located within a span of the first gate electrode.
However, in the same semiconductor device field of endeavor, Sharma discloses wherein the
source/drain contacts (140-150, Sharma) are located within a span (Fig. 1, Sharma) of the first gate electrode (110, Sharma).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Sharma’s feature wherein the source/drain contacts are located within a span of the first gate electrode to the combination of O’Brien, Chan and Izmailov to better current on-off ratio, which helps with detectability of separate states when used as a memory system ([0012], Sharma).
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O’Brien, in view of Chan in view of Izmailov in view of Sharma and further in view of Zhu et al. (US 20200194557 A1, of the record).
Re: Claim 5, O’Brien modified by Chan, Izmailov and Sharma discloses the transistor of claim 4,
O’Brien modified by Chan, Izmailov and Sharma does not expressly disclose wherein the
source/drain contacts are located outside of a span of the first gate electrode.
However, in the same semiconductor device field of endeavor, Zhu discloses
wherein the source/drain contacts (122-124 source terminal 122 and drain terminal 124 in [0024], Fig. 1C) are located outside of a span of the first gate electrode (316 bottom gate 124 in [0026], Fig. 1C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zhu’s feature of the source/drain contacts are located outside of a span of the first gate electrode to the combination of O’Brien, Chan and Izmailov to isolate the embedded bottom gate ([0026], Zhu).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O’Brien, in view of Chan in view of Izmailov in view of Sharma and further in view of Miyake (US 20200052129 A1, of the record).
Re: Claim 7, O’Brien modified by Chan, Izmailov and Sharma discloses the transistor of claim 4,
O’Brien modified by Chan, Izmailov and Sharma does not expressly disclose wherein one of the
source/drain contacts is located within a span of the first gate electrode, and another one of the source/drain contacts is located outside of the span of the first gate electrode.
However, in the same semiconductor device field of endeavor, Miyake discloses wherein one of the source/drain contacts (30 source wiring 30 in [0042], Fig. 4) is located within (Fig. 4) a span of the first gate electrode (16 gate electrode in [0038], Fig. 4), and another one of the source/drain contacts (32 drain wiring 32 in [0042], Fig. 4) is located outside of the span of the first gate electrode (16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Miyake’s feature of one of the source/drain contacts is located within a span of the first gate electrode, and another one of the source/drain contacts is located outside of the span of the first gate electrode to the combination of O’Brien, Chan and Izmailov to suppress change in the characteristics of the thin film transistor ([0038], Miyake).
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over O’Brien, in view of Chan in view of Izmailov and further in view of Wu et al. (US 20230360971 A1, of the record).
Re: Claim 8, O’Brien modified by Chan and Izmailov discloses the transistor of claim 1,
O’Brien modified by Chan and Izmailov does not expressly disclose wherein the hole supply layer covers a bottom surface and sidewalls of the second gate electrode.
However, in the same semiconductor device field of endeavor, Wu discloses
wherein the hole supply layer (622 gate dielectric made of HfO2 in [0041,0046], Fig. 11A) covers a bottom surface and sidewalls of the gate electrode (621, [0045], Fig.11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wu’s feature wherein the hole supply layer covers a bottom surface and sidewalls of the second gate electrode to the combination of O’Brien, Chan and Izmailov to isolate the gate electrode (Fig. 11A, Wu).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fan et al. (US 20230084510 A1) teaches “THIN FILM TRANSISTOR”. This document is related to a thin film transistor including a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.
Shima et al. (US 20210020782 A1) teaches “SEMICONDUCTOR DEVICE”. This document is related to a semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The first insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The second insulating layer includes an oxide. The third insulating film includes a part in contact with the semiconductor layer. The first insulating film includes silicon and nitrogen. The second insulating film includes silicon, nitrogen, and oxygen. The third insulating film includes silicon and oxygen. The semiconductor layer includes indium and oxygen.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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