Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Amendment and Request for Reconsideration filed November 5, 2025 and Applicant’s Response to Notice of Non-Compliant Amendment filed February 23, 2026. Applicant’s amendment to the claims, filed February 23, 2026, have been entered into the record. Claims 1, 12 and 13 have been amended. Claims 6, 10, 11, and 17 have been canceled.
Claims 1-5, 7-9, 12-16, and 18-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 18, 2025 has been placed in the application file and is being considered by the examiner.
Response to Arguments
Applicant's arguments filed November 5, 2025 have been fully considered and are persuasive in view of Applicant’s amendments to independent claims 1 and 13. Specifically, Applicant persuasively argues on page 7 that Zhang does not explicitly disclose laser anneal to crystallize the amorphous fill material, and that Zhang is silent with respect to RTP anneal. Note that paragraph [0025] of Zhang, cited by Applicant in support of this argument, implicitly discloses that dopant activation occurs as a result of recrystallization of amorphous material by laser annealing, however this is not explicitly stated. Therefore, the 35 U.S.C. 102(a)(1) rejection of claims 1-20 set forth in the previous Office Action has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Sharma et al., US 2015/0064933 A1 (hereinafter Sharma), which explicitly teaches the use of laser anneal and RTP anneal to recrystallize amorphous fill material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al., US 2020/0350215 A1 (hereinafter Zhang) in view of Sharma et al., US 2015/0064933 A1 (hereinafter Sharma).
Regarding claim 1, Zhang discloses: A method of forming a semiconductor device, the method comprising: forming a gate structure (Zhang, FIGs. 1-8, “dummy gate structure including a dummy gate liner 150, a dummy gate fill 160, and a dummy gate cap 170,” [0036]) on a superlattice structure (Zhang, FIGs. 1-8 show dummy gate liner 150, a dummy gate fill 160, and a dummy gate cap 170 [the gate structure] on structure of alternating sacrificial layers 120 and semiconductor nanosheet layers 130 arranged in stacked pairs [the superlattice structure], [0031]; Applicant’s specification defines a superlattice structure as “a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs,” [0007]), the superlattice structure on a top surface of a semiconductor substrate (Zhang, FIGs. 1-8 show structure of alternating sacrificial layers 120 and semiconductor nanosheet layers 130 arranged in stacked pairs [the superlattice structure] on top surface of dielectric layer 115 [the bottom dielectric isolation layer] of substrate 110, [0031]) and comprising a plurality of horizontal channel layers (Zhang, semiconductor nanosheet layers 130, [0030]) and a corresponding plurality of semiconductor material layers (Zhang, sacrificial layers 120, [0030]) alternatingly arranged in a plurality of stacked pairs (Zhang, see FIGs. 1-8, [0004]); depositing a dielectric layer on the gate structure and on the superlattice structure (Zhang, FIG. 1, gate sidewall spacer 140, “a dielectric material,” [0033]); removing a portion of the dielectric layer to expose the superlattice structure (Zhang, FIG. 2 shows remaining portion of gate sidewall spacer 140 [the dielectric layer] following etch process to expose alternating sacrificial layers 120 and semiconductor nanosheet layers 130 [the superlattice structure], [0035]); forming a source trench and a drain trench adjacent to the superlattice structure (Zhang, FIG. 3 shows source/drain trenches adjacent to and on opposite sides of the stacked pairs of alternating sacrificial layers 120 and semiconductor nanosheet layers 130, i.e., adjacent to the superlattice structure, [0004; 0047]); forming a bottom dielectric isolation layer under the source trench and the drain trench and under the superlattice structure (Zhang, FIGs. 1-15, dielectric layer 115, [0031]); forming an inner spacer layer on the superlattice structure (Zhang, FIG. 3, inner spacers 180, [0043-0045]); depositing a template material on the superlattice structure, on the dielectric layer, and in the source trench and in the drain trench (Zhang, FIG. 4, amorphous source/drain fill 190, [0047]); removing the template material from the dielectric layer (Zhang, FIGs. 4-5 show amorphous source/drain fill 190 removed from gate sidewall spacers 140 [the dielectric layer], [0051]); crystallizing the template material (Zhang, “A reliability anneal or other anneal process above a predetermined temperature can recrystallize the amorphous Si or SiGe through solid phase epitaxy to form epitaxial or poly-crystalline material which can lower S/D resistance,” i.e., crystallizing the template material, [0025]; see also [0068]) and a drain region (Zhang, FIG. 12, recrystallized source/drains 195, “the amorphous source/drain fills 190 [the template material] … can be heat treated to cause recrystallization of the amorphous source/drain fills 190 [the template material]. In various embodiments, the recrystallization treatment can be conducted in a temperature range of about 800° C. to about 1100° C., or about 900° C. to about 1000° C. to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase source/drain 195 [the source region and the drain region],” [0068; 0076]).
Although Zhang teaches that anneal process above a predetermined temperature can recrystallize the amorphous material, and Zhang teaches the use of laser annealing, Zhang does not explicitly teach that one or more of rapid thermal processing (RTP) anneal or laser anneal is used to crystallize the template material. Applicant discloses that “the amorphous template material 126 may be crystallized by any suitable means known to the skilled artisan,” and then provides examples of crystallizing the amorphous template by rapid thermal processing (RTP) or laser anneal, each of which are processes previously known in the art.
For example, Sharma, in the same field of endeavor, teaches a method for crystallizing amorphous semiconductor material by laser anneal and by Rapid Thermal Processing (RTP) (Sharma, [0003-0005]). Sharma teaches that large grain crystals have lower resistivity than smaller grain crystals, and that the size and depth of the resulting crystal growth can be predictably controlled by using laser anneal and/or Rapid Thermal Processing (RTP) (Sharma, [0003-0005]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Sharma, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Sharma, to predictably control crystal size, thereby reducing resistivity, thus improving device performance and reliability.
Regarding claim 2, Zhang in view of Sharma teaches: The method of claim 1, wherein the template material is amorphous (Zhang, FIG. 4, amorphous source/drain fill 190, “doped amorphous silicon (Si) or silicon-germanium (SiGe) can be used as source/drain (S/D) material [the template material] at the beginning of fabrication to ensure uniform fill volume and size of S/D material, and the amorphous material subsequently recrystallized,” [0024; see also 0047]).
Regarding claim 3, Zhang in view of Sharma teaches: The method of claim 2, wherein the template material (Zhang, FIG. 4, amorphous source/drain fill 190) comprises one or more of silicon (Si), silicon germanium (SiGe) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be phosphorus-doped silicon (Si:P) to form an n-type source/drain (S/D) or a boron-doped silicon germanium (SiGe:B) to form a p-type S/D, [0048]), titanium (Ti), zirconium (Zr), and hafnium (Hf).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Zhang include one or more of Applicant’s claimed alternative elements, for example: silicon (Si), silicon germanium (SiGe).
Regarding claim 4, Zhang in view of Sharma teaches: The method of claim 2, wherein the template material (Zhang, FIG. 4, amorphous source/drain fill 190) has a thickness in a range of from 2 nm to 50 nm (Zhang, “the amorphous source/drain fill 190 [the template material] can extend away from the adjoining face of the stack of sacrificial layers 120 and semiconductor nano sheet layers 130 by a distance [a thickness] in a range of about 20 nm to about 200 nm,” [0049]).
Regarding claim 5, Zhang in view of Sharma teaches: The method of claim 1, wherein the plurality of semiconductor material layers (Zhang, sacrificial layers 120, [0030]) and the plurality of horizontal channel layers (Zhang, semiconductor nanosheet layers 130, [0030]) independently comprise one or more of silicon germanium (SiGe) and silicon (Si) (Zhang, “The sacrificial layers 120 can be, for example, silicon-germanium (SiGe) and the semiconductor nanosheet layers 130 can be silicon (Si), or the materials can be reversed,” [0030]).
Regarding claim 7, Zhang in view of Sharma teaches: The method of claim 1, wherein forming the source region and the drain region (Zhang, FIG. 12, recrystallized source/drains 195, [0068]) comprises growing an epitaxial layer thereon (Zhang, recrystallized source/drains 195 [the source region and the drain region] formed by heat treating amorphous source/drain fills 190 [the template material] “to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase source/drain 195, for example, through solid-phase epitaxy,” [0068]).
Regarding claim 8, Zhang in view of Sharma teaches: The method of claim 1, wherein the source region and the drain region (Zhang, FIG. 12, recrystallized source/drains 195 [the source region and the drain region] formed by crystallizing the amorphous source/drain fill 190 [the template material], [0068]) are independently doped with one or more of phosphorus (P) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be phosphorus-doped silicon (Si:P) to form an n-type source/drain (S/D),” [0048]), arsenic (As), boron (B) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be … a boron-doped silicon germanium (SiGe:B) to form a p-type S/D,” [0048]), and gallium (Ga).
Regarding claim 9, Zhang in view of Sharma teaches: The method of claim 1, wherein the bottom dielectric isolation layer (Zhang, FIGs. 1-15, dielectric layer 115, [0031]) comprises one or more of silicon oxide (SiOx) (Zhang, “the dielectric layer 115 can be … silicon oxide (SiO),” [0032]), silicon nitride (SiN) (Zhang, “the dielectric layer 115 can be … silicon nitride (SiN),” [0032]), silicon carbide (SiC) (Zhang, “the dielectric layer 115 can be … silicon carbonitride (SiCN),” [0032]), and a high-K material.
Regarding claim 12, Zhang in view of Sharma teaches: The method of claim 1, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAI), and N doped polysilicon. (Zhang, FIG. 15, gate structure includes conductive gate fill 250, “conductive gate fill 250 can be a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conducting metallic compound material (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g. Ti3Al, ZrAl), tantalum magnesium carbide (TaMgC), carbon nanotubes (CNT), conductive carbon, graphene, or any suitable combination of these materials,” emphasis added, [0071-0074]).
Regarding claim 13, Zhang discloses: A method of forming a semiconductor device, the method comprising: forming a superlattice structure on a top surface of a bottom dielectric isolation layer on a substrate (Zhang, FIGs. 1-8 show structure of alternating sacrificial layers 120 and semiconductor nanosheet layers 130 arranged in stacked pairs and formed on top surface of dielectric layer 115 [the bottom dielectric isolation layer] of substrate 110, [0031]), the superlattice structure comprising a plurality of horizontal channel layers (Zhang, semiconductor nanosheet layers 130, [0030]) and a corresponding plurality of semiconductor material layers (Zhang, sacrificial layers 120, [0030]) alternatingly arranged in a plurality of stacked pairs (Zhang, see FIGs. 1-8, [0004]); forming a gate structure on a top surface of the superlattice structure (Zhang, FIGs. 1-8, “dummy gate structure including a dummy gate liner 150, a dummy gate fill 160, and a dummy gate cap 170,” [0036]; shown on a top surface of alternating sacrificial layers 120 and semiconductor nanosheet layers 130 arranged in stacked pairs [the superlattice structure]); forming a dielectric layer on the gate structure and on the superlattice structure (Zhang, FIG. 1, gate sidewall spacer 140, “a dielectric material,” [0033]); forming a source trench and a drain trench adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate (Zhang, FIG. 3 shows source/drain trenches adjacent to and on opposite sides of the stacked pairs of alternating sacrificial layers 120 and semiconductor nanosheet layers 130, i.e., adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate, [0004; 0047]); depositing a template material on the superlattice structure, on the dielectric layer, and in the source trench and in the drain trench (Zhang, FIG. 4, amorphous source/drain fill 190 [the template material], [0047]); removing the template material from the dielectric layer (Zhang, FIGs. 4-5 show amorphous source/drain fill 190 removed from gate sidewall spacers 140 [the dielectric layer], [0051]); annealing the substrate to crystallize the template material (Zhang, “A reliability anneal or other anneal process above a predetermined temperature can recrystallize the amorphous Si or SiGe through solid phase epitaxy to form epitaxial or poly-crystalline material which can lower S/D resistance,” i.e., crystallizing the template material, [0025]; see also [0068]) (Zhang, FIG. 12, recrystallized source/drains 195, “the amorphous source/drain fills 190 [the template material] … can be heat treated to cause recrystallization of the amorphous source/drain fills 190 [the template material]. In various embodiments, the recrystallization treatment can be conducted in a temperature range of about 800° C. to about 1100° C., or about 900° C. to about 1000° C. to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase source/drain 195 [the source region and the drain region],” [0068; 0076]).
Although Zhang teaches that anneal process above a predetermined temperature can recrystallize the amorphous material, and Zhang teaches the use of laser annealing, Zhang does not explicitly teach that one or more of rapid thermal processing (RTP) anneal or laser anneal is used to crystallize the template material.
However, Sharma, in the same field of endeavor, teaches a method for crystallizing amorphous semiconductor material by laser anneal and by Rapid Thermal Processing (RTP) (Sharma, [0003-0005]). Sharma teaches that large grain crystals have lower resistivity than smaller grain crystals, and that the size and depth of the resulting crystal growth can be predictably controlled by using laser anneal and/or Rapid Thermal Processing (RTP) (Sharma, [0003-0005]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Sharma, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Sharma, to predictably control crystal size, thereby reducing resistivity, thus improving device performance and reliability.
Regarding claim 14, Zhang in view of Sharma teaches: The method of claim 13, wherein the template material is amorphous (Zhang, FIG. 4, amorphous source/drain fill 190, “doped amorphous silicon (Si) or silicon-germanium (SiGe) can be used as source/drain (S/D) material [the template material] at the beginning of fabrication to ensure uniform fill volume and size of S/D material, and the amorphous material subsequently recrystallized,” [0024; see also 0047]) and has a thickness in a range of from 2 nm to 50 nm (Zhang, “the amorphous source/drain fill 190 [the template material] can extend away from the adjoining face of the stack of sacrificial layers 120 and semiconductor nano sheet layers 130 by a distance [a thickness] in a range of about 20 nm to about 200 nm,” [0049]).
Regarding claim 15, Zhang in view of Sharma teaches: The method of claim 14, wherein the template material (Zhang, FIG. 4, amorphous source/drain fill 190) comprises one or more of silicon (Si), silicon germanium (SiGe) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be phosphorus-doped silicon (Si:P) to form an n-type source/drain (S/D) or a boron-doped silicon germanium (SiGe:B) to form a p-type S/D, [0048]), titanium (Ti), zirconium (Zr), and hafnium (Hf).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Zhang include one or more of Applicant’s claimed alternative elements, for example: silicon (Si), silicon germanium (SiGe).
Regarding claim 16, Zhang in view of Sharma teaches: The method of claim 13, wherein the plurality of semiconductor material layers (Zhang, sacrificial layers 120, [0030]) and the plurality of horizontal channel layers (Zhang, semiconductor nanosheet layers 130, [0030]) independently comprise one or more of silicon germanium (SiGe) and silicon (Si) (Zhang, “The sacrificial layers 120 can be, for example, silicon-germanium (SiGe) and the semiconductor nanosheet layers 130 can be silicon (Si), or the materials can be reversed,” [0030]).
Regarding claim 18, Zhang in view of Sharma teaches: The method of claim 13, wherein forming the source region and the drain region (Zhang, FIG. 12, recrystallized source/drains 195, [0068]) comprises growing an epitaxial layer thereon (Zhang, recrystallized source/drains 195 [the source region and the drain region] formed by heat treating amorphous source/drain fills 190 [the template material] “to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase source/drain 195, for example, through solid-phase epitaxy,” [0068]).
Regarding claim 19, Zhang in view of Sharma teaches: The method of claim 13, wherein the source region and the drain region (Zhang, FIG. 12, recrystallized source/drains 195 [the source region and the drain region] formed by crystallizing the amorphous source/drain fill 190 [the template material], [0068]) are independently doped with one or more of phosphorus (P) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be phosphorus-doped silicon (Si:P) to form an n-type source/drain (S/D),” [0048]), arsenic (As), boron (B) (Zhang, FIG. 4, “the amorphous source/drain fill 190 [the template material] can be … a boron-doped silicon germanium (SiGe:B) to form a p-type S/D,” [0048]), and gallium (Ga).
Regarding claim 20, Zhang in view of Sharma teaches: The method of claim 13, wherein the bottom dielectric isolation layer (Zhang, FIGs. 1-15, dielectric layer 115, [0031]) comprises one or more of silicon oxide (SiOx) (Zhang, “the dielectric layer 115 can be … silicon oxide (SiO),” [0032]), silicon nitride (SiN) (Zhang, “the dielectric layer 115 can be … silicon nitride (SiN),” [0032]), silicon carbide (SiC) (Zhang, “the dielectric layer 115 can be … silicon carbonitride (SiCN),” [0032]), and a high-K material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.L.N./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899