DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 - 4, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (11,393,408) in view of Wang et al. (10424602) and further in view of Tsai et al. (2019/0317372).
With regard to claim 1, Li et al. disclose a display device (for example, fig. 4, 7) comprising:
a substrate (for example, see claim 1) that includes a display area (AA) and a non-display area (NA) disposed at a side of the display area, and the display area including:
a first area including an antistatic circuit (electrostatic discharge circuits 50, fig. 7 functioning as an antistatic circuit);
a second area including a fanout line (11);
a third area including a demultiplexer (20); and
a fourth area including a pixel circuit (a pixel circuit 80 forming in the display area AA, fig. 4 or 5),
a first sub-area (referred to as “80A” by examiner’s annotation shown in fig. 5 below) adjacent to at least one of the first area (area having fanout line 11); and a second sub-area (referred to as “80B” by examiner’s annotation shown in fig. 5 below) excluding the first sub-area (80A), and
the second sub-area (80B) includes: unit pixel rows respectively comprising a pair of pixel rows;
first pixels (referred to as “80B1” by examiner’s annotation shown in fig. 5 below) disposed in a first direction (for example, X-direction) in a first pixel row;
second pixels (referred to as “80B2” by examiner’s annotation shown in fig. 5 below) disposed in the first direction in a second pixel row that is a next row of the first pixel row, the second pixels (80B2) being spaced apart from the first pixels (80B1);
a clock line (referred to as “21A” by examiner’s annotation shown in fig. 5 below; wherein the clock line 21A made from the clock line 21) extending in a second direction (Y direction) intersecting the first direction (X-direction).
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Li et al. do not clearly disclose a gate driver including: a first stage disposed left of the clock line in a plan view; or a second stage disposed right of the clock line in a plan view, wherein at least one of the first stage and the second stage is disposed directly between two pixels wherein the first stage and the second stage are disposed between two adjacent ones of the unit pixel rows in the second direction, and are respectively disposed between two respective adjacent pixel columns in the first direction.
However, Wang et al. discloses a gate driver (a gate driver circuit has a plurality of first driving units 200A, the second driving units 200B and the third driving units 200C wherein the gate driver circuit is formed as multi-stage driving unit with a plurality of driving units 200; for example, see column 7, lines 33 – 35; column 8, lines 23 - 26) including: a first stage (referred to as “200A1” by examiner’s annotation shown in fig. 4A below; wherein the middle stage unit 200A1 is among stage units in the region 200A) disposed left of the clock line (CK as shown in fig. 4A below) in a plan view; and a second stage (referred to as “200C1” by examiner’s annotation shown in fig. 4A below; wherein the middle stage unit 200C1 is among stage units in the region 200C) disposed right of the clock line (CK as shown in fig. 4A below) in a plan view, wherein at least one of the first stage (200A1) is disposed directly between two pixels (referred to as “102A” and “102B” by examiner’s annotation shown in fig. 4A below; wherein the two pixels 102A and 102B are pixels 102) wherein the first stage (200A1) and the second stage (200C1) are disposed between two adjacent ones of the unit pixel rows (for example, see rows 1, 3 as shown in fig. 4A below) in the second direction, and are respectively disposed between two respective adjacent pixel columns (referred to as “C1” by examiner’s annotation shown in fig. 4A below) in the first direction. (for example, see fig. 4A).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Li et al.’s device to have a gate driver including: a first stage disposed left of the clock line in a plan view; or a second stage disposed right of the clock line in a plan view, wherein at least one of the first stage and the second stage is disposed directly between two pixels wherein the first stage and the second stage are disposed between two adjacent ones of the unit pixel rows in the second direction, and are respectively disposed between two respective adjacent pixel columns in the first direction as taught by Wang et al. in order to output the gate signal efficiency of the device to pixels and for enhancing a stability operation of the semiconductor device and prevent damage to the semiconductor patterns and enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Li et al. and Wang et al. do not clearly disclose the substrate being made of glass.
However, Tsai et al. discloses the substrate (100) being made of glass. (for example, see paragraph [0026], fig. 4).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Li et al. and Wang et al.’s device to incorporate the substrate being made of glass as taught by Tsai et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device and prevent damage to the semiconductor patterns and enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 3, Wang et al. disclose the first stage (200A1) and the second stage (200C1) are provided in plural (plurality stages forming in the regions 200A, 200C), and one of the first stages (200A1) and one of the second stages (200C1) are disposed between the two adjacent ones of the unit pixel rows (a gate driver circuit has a plurality of first driving units 200A, the second driving units 200B and the third driving units 200C wherein the gate driver circuit is formed as multi-stage driving unit with a plurality of driving units 200 inherently including multi-rows; for example, see column 7, lines 33 – 35; column 8, lines 23 - 26).
With regard to claim 4, Wang et al. disclose the one (200A1) of the first stages and the one (200C1) of the second stages are disposed between the second pixel row (one of pixel row including pixels 102) of a first unit pixel row and the first pixel row (one of pixel row including pixels 102) of a second unit pixel row, among the two adjacent ones of the unit pixel rows (a gate driver circuit has a plurality of first driving units 200A, the second driving units 200B and the third driving units 200C wherein the gate driver circuit is formed as multi-stage driving unit with a plurality of driving units 200 inherently including multi-rows; for example, see column 7, lines 33 – 35; column 8, lines 23 - 26).
With regard to claim 20, Li et al. disclose a tiled display device comprising: display devices disposed in a matrix format, each of the display devices (for example, fig. 4, 7) comprising:
a substrate (for example, see claim 1) that includes a display area (AA) and a non-display area (NA) disposed at a side of the display area, and the display area including:
a first area including an antistatic circuit (electrostatic discharge circuits 50, fig. 7 functioning as an antistatic circuit);
a second area including a fanout line (11);
a third area including a demultiplexer (20); and
a fourth area including a pixel circuit (a pixel circuit 80 forming in the display area AA, fig. 4 or 5),
a first sub-area (referred to as “80A” by examiner’s annotation shown in fig. 5 below) adjacent to at least one of the first area (area having fanout line 11); and a second sub-area (referred to as “80B” by examiner’s annotation shown in fig. 5 below) excluding the first sub-area (80A), and
the second sub-area (80B) includes: unit pixel rows respectively comprising a pair of pixel rows;
first pixels (referred to as “80B1” by examiner’s annotation shown in fig. 5 below) disposed in a first direction (for example, X-direction) in a first pixel row;
second pixels (referred to as “80B2” by examiner’s annotation shown in fig. 5 below) disposed in the first direction in a second pixel row that is a next row of the first pixel row, the second pixels (80B2) being spaced apart from the first pixels (80B1);
a clock line (referred to as “21A” by examiner’s annotation shown in fig. 5 below; wherein the clock line 21A made from the clock line 21) extending in a second direction (Y direction) intersecting the first direction (X-direction).
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Li et al. do not clearly disclose a gate driver including: a first stage disposed left of the clock line in a plan view; or a second stage disposed right of the clock line in a plan view, wherein at least one of the first stage and the second stage is disposed directly between two pixels wherein the third stage is between two adjacent ones of the unit pixel rows in the second direction, and between two adjacent pixel columns in the first direction.
However, Wang et al. discloses a gate driver (a gate driver circuit has a plurality of first driving units 200A, the second driving units 200B and the third driving units 200C wherein the gate driver circuit is formed as multi-stage driving unit with a plurality of driving units 200; for example, see column 7, lines 33 – 35; column 8, lines 23 - 26) including: a first stage (referred to as “200A1” by examiner’s annotation shown in fig. 4A below; wherein the middle stage unit 200A1 is among stage units in the region 200A) disposed left of the clock line (CK as shown in fig. 4A below) in a plan view; and a second stage (referred to as “200C1” by examiner’s annotation shown in fig. 4A below; wherein the middle stage unit 200C1 is among stage units in the region 200C) disposed right of the clock line (CK as shown in fig. 4A below) in a plan view, wherein at least one of the first stage (200A1) is disposed directly between two pixels (referred to as “102A” and “102B” by examiner’s annotation shown in fig. 4A below; wherein the two pixels 102A and 102B are pixels 102) wherein the third stage (referred to as “200C2” by examiner’s annotation shown in fig. 4A below; wherein the stage unit 200C2 is among stage units in the region 200C) is between two adjacent ones of the unit pixel rows (rows as shown in fig. 4A) in the second direction, and between two adjacent pixel columns (columns C1 as shown in fig. 4A) in the first direction. (for example, see fig. 4A).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Li et al.’s device to have a gate driver including: a first stage disposed left of the clock line in a plan view; or a second stage disposed right of the clock line in a plan view, wherein at least one of the first stage and the second stage is disposed directly between two pixels wherein the first stage and the second stage are disposed between two adjacent ones of the unit pixel rows in the second direction, and are respectively disposed between two respective adjacent pixel columns in the first direction as taught by Wang et al. in order to output the gate signal efficiency of the device to pixels and for enhancing a stability operation of the semiconductor device and prevent damage to the semiconductor patterns and enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Li et al. and Wang et al. do not clearly disclose the substrate being made of glass.
However, Tsai et al. discloses the substrate (100) being made of glass. (for example, see paragraph [0026], fig. 4).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Li et al. and Wang et al.’s device to incorporate the substrate being made of glass as taught by Tsai et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device and prevent damage to the semiconductor patterns and enhancing the reliability of the electrical connection between the vias and the semiconductor patterns for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
3. Claims 5 - 19 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a gap between the first stage and the clock line in the first direction and a gap between the second stage and the clock line in the first direction are same as recited in claim 5.
Response to Amendment
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812