DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gracias (US 2004/0023515) in view of KR’223 (KR 20210065223, cited in IDS, Machine Translation is provided) and Clevenger (US 2005/0230831).
Regarding claim 1, Gracias discloses a semiconductor processing method comprising: forming a layer of low dielectric constant material (Fig.1, numeral 101; [0022]) on the semiconductor substrate (100); subsequent to forming the laver of low dielectric constant material on the semiconductor substrate, providing an oxygen-containing precursor to the processing region prior to forming the interface layer (Fig.3, numeral 301; claim 7); contacting the laver of low-dielectric constant material with the oxygen-containing precursor (Fig.3, numeral 301; [0026]) to form an interface layer (103) on the layer of low dielectric constant material (101); and forming a cap layer (105) on the interface layer (103).
Gracias does not disclose (1) providing one or more deposition precursors to a processing region of a semiconductor processing chamber wherein a semiconductor substrate is positioned within the processing region; (2) wherein an adhesion value between the layer of low dielectric constant material and the cap layer is greater than or about 3.0 J/m²
Regarding element (1), Gracias however discloses forming a low-k dielectric layer (101). And KR’223 discloses forming a low-k dielectric layer ([0024]) by providing one or more deposition precursors to a processing region of a semiconductor processing chamber ([0047]) wherein a semiconductor substrate is positioned within the processing region ([0044]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Gracias with KR’223 to provide one or more deposition precursors to a processing region of a semiconductor processing chamber wherein a semiconductor substrate is positioned within the processing region for the purpose of forming a low-k dielectric layer.
Regarding element (2) Clevenger discloses wherein an adhesion value between the layer of low dielectric constant material and the cap layer is greater than or about 3.0 J/m² ([0044]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Gracias with Clevenger to have an adhesion value between the layer of low dielectric constant material and the cap layer is greater than or about 3.0 J/m² for the purpose of improving adhesion between layers (Clevenger, [0044]).
Regarding claim 2, KR’223 discloses wherein the semiconductor substrate is maintained at a temperature less than or about 550 °C during the semiconductor processing method ([0038]).
Regarding claim 3, KR’223 discloses purging the processing region of the one or more deposition precursors, wherein a plasma power is maintained at less than or about 750 W while purging the processing region ([0050]; [0058]).
Regarding claim 4, KR’223 discloses (halting a flow of the one or more deposition precursors prior to forming the interface layer ([0050]).
Regarding claim 6, Gracias does not disclose wherein a flow rate of the oxygen-containing precursor is less than or about 750 sccm.
Gracias however discloses flowing oxygen gas to oxides the surface of a low-k dielectric film (Fig.3, numeral 301; [0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to adjust the flow of oxygen to be in the claimed range for the purpose of optimizing the oxidation process.
Regarding claim 8, Clevenger discloses wherein an adhesion value between the layer of low dielectric constant material and the cap layer is greater than or about 4.0 J/m2 ([0044]).
Regarding claim 9, Gracias discloses a semiconductor processing method comprising: forming a layer of low dielectric constant material (Fig.1, numeral 101) on a semiconductor substrate (103); forming an interface layer (103) on the layer of low dielectric constant material (101); and forming a cap layer (105) on the interface layer (103).
Gracias does not disclose that the semiconductor substrate housed in a processing region of a semiconductor processing chamber, wherein a plasma power is maintained at a first plasma power level while forming the layer of low dielectric constant material; purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level.
KR’223 however discloses housed in a processing region of a semiconductor processing chamber, wherein a plasma power is maintained at a first plasma power level while forming the layer of low dielectric constant material ([0045]); purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level ([0050]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Gracias with KR’223 to have the semiconductor substrate housed in a processing region of a semiconductor processing chamber, wherein a plasma power is maintained at a first plasma power level while forming the layer of low dielectric constant material; purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level for the purpose of forming a low-k dielectric layer.
Regarding claim 10, Gracias discloses wherein the semiconductor substrate comprises silicon ([0022]).
Regarding claim 11, KR’223 discloses wherein the layer of low dielectric constant material is formed through plasma-enhanced chemical vapor deposition ([0002]).
Regarding claim 12, Gracias discloses wherein the interface layer (103) is characterized by a lower methyl incorporation than the layer of low dielectric constant material ([0026]).
Regarding claim 14, KR’223 discloses reducing a flow rate of one or more precursors used to form the layer of low dielectric constant material prior to purging the processing region ([0050]).
Regarding claim 15, Gracias discloses wherein a temperature and a pressure in the processing region while forming the layer of low dielectric constant material are maintained while forming the interface layer ([0031]).
Regarding claim 16, KR’223 discloses reducing a flow rate of a carrier gas prior to purging the processing region ([0050]).
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gracias in view of KR’223 and Clevenger as applied to claims 1 and 9 above, and further in view of Chhabra (US 2013/0344704).
Regarding claim 7, Gracias in view of KR’223 and Clevenger does not disclose densifying the layer of low dielectric constant material while purging the processing region of the one or more deposition precursors.
Chhabra however discloses densifying the layer of low dielectric constant material while purging the processing region of the one or more deposition precursors ([0036]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Gracias with Chhabra to densify the layer of low dielectric constant material while purging the processing region of the one or more deposition precursors for the purpose of improving properties of a low-k dielectric film (Chhabra, [0037]).
Regarding claim 13, Gracias does not disclose providing molecular oxygen to the processing region while purging the processing region.
Chhabra however discloses providing molecular oxygen to the processing region while purging the processing region ([0036]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Gracias with Chhabra provide molecular oxygen to the processing region while purging the processing region for the purpose of improving properties of a low-k dielectric film (Chhabra, [0037]).
Response to Arguments
Applicant's arguments filed 05/28/2026 have been fully considered but they are not persuasive.
Applicant’s arguments that Gracias does not disclose the limitations of amended claim 1 such as “subsequent to forming the laver of low dielectric constant material on the semiconductor substrate, providing an oxygen-containing precursor to the processing region prior to forming the interface layer contacting the laver of low-dielectric constant material with the oxygen-containing precursor to form an interface layer” are not persuasive because Gracias discloses subsequent to forming the laver of low dielectric constant material on the semiconductor substrate, providing an oxygen-containing precursor to the processing region prior to forming the interface layer (Fig.3, numeral 301; claim 7); contacting the laver of low-dielectric constant material with the oxygen-containing precursor (Fig.3, numeral 301; [0026]) to form an interface layer (103).
Applicant’s arguments that KR’223 does not disclose the limitations of claim 9 such as “purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level, “are not persuasive because KR’223 discloses that plasma during purging is turn-off with a time difference ([0051]). Thus, during purging that plasma atmosphere is maintained by the high-frequency power (see [0051]). Therefore, KR’223 discloses purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, and wherein the second plasma power level is less than or equal to the first plasma power level ([0050], [0051]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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