DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/8/2026 has been entered.
Claim Objections
Claim 8 is objected to because of the following informalities: The limitations in line 8 includes “subsequent one of the plurality of dipole layers; layers,…” . Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8-11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pao et al (US Publication no. 2021/0391439) in view of Chang et al (US Publication No. 2021/0399104).
Regarding claim 8, Pao discloses a method of manufacturing a semiconductor device, the method comprising: depositing an interfacial layer ¶0027 over a plurality of semiconductor fins Fig 4;sequentially depositing, annealing, and removing a plurality of dipole layers Fig 1, wherein each one of the sequentially depositing, annealing, and removing forms or modifies a dipole region within the interfacial layer Fig 1 and 6-7; wherein at least two of the plurality of dipole layers modifies at least one of the dipole regions within the interfacial layer Fig 9-12 ¶0034-0035;forming a gate dielectric layer ¶0028 over the interfacial layer ¶0028 over the plurality of semiconductor fins Fig 15; and forming a plurality of gate electrodes over the gate dielectric layer to form a plurality of transistors Fig 15, each of the plurality of transistors have a different threshold voltage ¶0039. Pao discloses all the limitations but silent on specific step of forming the dipole layers. Whereas Chang discloses wherein each of the removing the plurality of dipole layers fully removes a respective dipole layer after the annealing and before a deposition of a subsequent one of the plurality of dipole layers Fig 2. Pao and Chang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pao because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Wang and incorporate the teachings of Chang as an alternative method step to provide device isolation and improve device processing step.
Regarding claim 9, Pao discloses wherein the plurality of transistors is eight transistors ¶0042-0046.
Regarding claim 10, Pao discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers to a same thickness with a same material ¶0032 and wherein each of the sequentially annealing is performed ¶0056 and 0060. Pao discloses all the limitations but silent on the specific temperature. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify temperature, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Regarding claim 11, Pao discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers to a different thickness and wherein each of the sequentially annealing is performed at a same temperature ¶0056 and 0060.
Regarding claim 13, Pao discloses wherein the depositing the interfacial layer deposits the interfacial layer in physical contact with the plurality of semiconductor fins Fig 4.
Regarding claim 14, Pao discloses, wherein the plurality of dipole layers comprises at least two different dopant layers ¶0016, 0033-0036.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Pao et al (US Publication no. 2021/0391439) and Chang et al (US Publication No. 2021/0399104) and in further view of Wang et al (US Publication No. 2019/0148237).
Regarding claim 12, Pao discloses wherein each of the sequentially annealing is performed at a same temperature ¶0034. Pao discloses all the limitations but silent on the material. Whereas Wang discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers with a different material ¶0019, 0023-0025. Pao and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pao because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Pao and incorporate the teachings of Wang to improve/adjust device threshold voltage.
Allowable Subject Matter
Claims 1-7, 21-26 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response “wherein the forming the first dipole region comprises: applying a first dipole material: removing the first dipole material from over the first dielectric layer; [[and]] applying a second dipole material different from the first dipole material: and removing the second dipole material: and forming a second dipole region within the second dielectric layer, the second dipole region comprising a second dipole dopant and a second thickness, one of the second dipole dopant and the second thickness being different from the first dipole dopant and the first thickness, respectively, wherein the forming the second dipole region comprises: applying a third dipole material: removing the third dipole material: applying a fourth dipole material different from the first dipole material, the second dipole material, and the third dipole material: and removing the fourth dipole material”, as recited in independent claim 1 and “forming a fifth transistor comprising a fifth gate electrode separated from a fifth semiconductor fin by a fifth interfacial layer, the fifth interfacial layer comprising a fifth dipole region, the fifth transistor having a fifth threshold voltage; forming a sixth transistor comprising a sixth gate electrode separated from a sixth semiconductor fin by a sixth interfacial layer, the sixth interfacial layer comprising a sixth dipole region, the sixth transistor having a sixth threshold voltage; and forming a seventh transistor comprising a seventh gate electrode separated from a seventh semiconductor fin by a seventh interfacial layer, the seventh interfacial layer comprising a seventh dipole region, the seventh transistor having a seventh threshold voltage, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor has a different threshold voltage, wherein the forming the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises sequentially depositing, annealing, and removing a plurality of dipole layers to form at least seven different combinations of dopants and concentrations of dopants”, as recited in independent claim 21.
Claims 2-7, 22-26 are also allowed as being directly or indirectly dependent of the allowed independent base claims.
Response to Arguments
Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive.
Regarding the argument in claim 8 that the prior art of record does not teach the added claim limitations, the examiner disagrees and finds the argument unpersuasive. Pao discloses the added claimed limitations as fully described in the rejection above.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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