DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US Publication No. 2019/0148237) in view of Ji et al (US Publication No. 2016/0148934) and Chang et al (US Publication No. 2021/0399104).
Regarding claim 1, Wang discloses a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer ¶0018 over a first semiconductor fin ¶0021;forming a second dielectric layer over a second semiconductor fin Fig 2D ¶0019;forming a first dipole region within the first dielectric layer Fig 2D, 240, the first dipole region comprising a first thickness Fig 2D, 240 ¶0019-0024, 0031-0034; and forming a second dipole region within the second dielectric layer Fig 2D, 242, the second dipole region comprising and a second thickness Fig 2D, 242 ¶0019-0024, 0031-0034, one of the second dipole dopant and the second thickness being different from the first dipole and the first thickness, respectively¶0019-0024, 0031-0034. Wang discloses all the limitations but silent on the dipole dopant. Whereas Ji discloses a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer Fig 5, 305N over a first semiconductor Fig 5;forming a second dielectric layer Fig 5, 305P over a second semiconductor Fig 5;forming a first dipole region Fig 5, 313N within the first dielectric layer Fig 5, 305N, the first dipole region comprising a first dipole dopant ¶0074-0075; and forming a second dipole region Fig 5, 313P within the second dielectric layer Fig 5, 305P, the second dipole region comprising a second dipole dopant ¶0074-0075, one of the second dipole dopant and the second thickness being different from the first dipole dopant and the first thickness, respectively Fig 5-6. Wang and Ji are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Wang and incorporate the teachings of Ji to improve/adjust device threshold voltage. Wang discloses all the limitations but silent on specific step of forming the dipole region. Whereas Chang discloses forming a first dipole region within the first dielectric layer, the first dipole region comprising a first dipole dopant and a first thickness, wherein the forming the first dipole region comprises removing a first dipole material from over the first dielectric layer Fig 2. Wang and Chang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Wang and incorporate the teachings of Chang as an alternative method step to provide device isolation and improve device processing step.
Regarding claim 2, Ji discloses wherein the first dipole dopant comprises lanthanum¶0074-0075.
Regarding claim 3, Ji discloses wherein the second dipole dopant comprises aluminum ¶0074-0075.
Regarding claim 4, Wang discloses wherein the second thickness is different from the first thickness Fig 2D.
Regarding claim 5, Wang discloses wherein the forming the first dipole region further comprises a first anneal performed at a first temperature and wherein the forming the second dipole region further comprises a second anneal performed at a second temperature different from the first temperature ¶0048-0050.
Regarding claim 6, Wang and Ji discloses forming a gate dielectric layer over the first dielectric layer Wang Fig 2D; Ji Fig 5.
Regarding claim 7, Ji discloses wherein the second dipole region further comprises the first dipole dopant Fig 10E.
Claim 8-11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pao et al (US Publication no. 2021/0391439) in view of Chang et al (US Publication No. 2021/0399104).
Regarding claim 8, Pao discloses a method of manufacturing a semiconductor device, the method comprising: depositing an interfacial layer ¶0027 over a plurality of semiconductor fins Fig 4;sequentially depositing, annealing, and removing a plurality of dipole layers Fig 1, wherein each one of the sequentially depositing, annealing, and removing forms or modifies a dipole region within the interfacial layer Fig 1 and 6-7;forming a gate dielectric layer ¶0028 over the interfacial layer ¶0028 over the plurality of semiconductor fins Fig 15; and forming a plurality of gate electrodes over the gate dielectric layer to form a plurality of transistors Fig 15, each of the plurality of transistors have a different threshold voltage ¶0039. Pao discloses all the limitations but silent on specific step of forming the dipole layers. Whereas Chang discloses wherein each of the removing the plurality of dipole layers fully removes a respective dipole layer after the annealing and before a deposition of a subsequent one of the plurality of dipole layers Fig 2. Pao and Chang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pao because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Wang and incorporate the teachings of Chang as an alternative method step to provide device isolation and improve device processing step.
Regarding claim 9, Pao discloses wherein the plurality of transistors is eight transistors ¶0042-0046.
Regarding claim 10, Pao discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers to a same thickness with a same material ¶0032 and wherein each of the sequentially annealing is performed ¶0056 and 0060. Pao discloses all the limitations but silent on the specific temperature. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify temperature, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Regarding claim 11, Pao discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers to a different thickness and wherein each of the sequentially annealing is performed at a same temperature ¶0056 and 0060.
Regarding claim 13, Pao discloses wherein the depositing the interfacial layer deposits the interfacial layer in physical contact with the plurality of semiconductor fins Fig 4.
Regarding claim 14, Pao discloses, wherein the plurality of dipole layers comprises at least two different dopant layers ¶0016, 0033-0036.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Pao et al (US Publication no. 2021/0391439) and Chang et al (US Publication No. 2021/0399104) and in further view of Wang et al (US Publication No. 2019/0148237).
Regarding claim 12, Pao discloses wherein each of the sequentially annealing is performed at a same temperature ¶0034. Pao discloses all the limitations but silent on the material. Whereas Wang discloses wherein the sequentially depositing the plurality of dipole layers deposits each of the plurality of dipole layers with a different material ¶0019, 0023-0025. Pao and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pao because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Pao and incorporate the teachings of Wang to improve/adjust device threshold voltage.
Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al (US Publication No. 2016/0148934) in view of Wang et al (US Publication No. 2019/0148237) and Chang et al (US Publication No. 2021/0399104).
Regarding claim 21, Ji discloses a method of manufacturing a semiconductor device, the method comprising: forming a first transistor Fig 10H, NMOS comprising a first gate electrode Fig 10H, 35N separated from a first semiconductor by a first interfacial layer Fig 10H, 24N, the first interfacial layer Fig 10H, 24N comprising a first dipole region Fig 10H, 40N, the first transistor having a first threshold voltage ¶0139-0143;forming a second transistor Fig 10H, NMOS comprising a second gate electrode separated from a second semiconductor by a second interfacial layer Fig 10H, 24P, the second interfacial layer comprising a second dipole region Fig 10H, 40P, the second transistor having a second threshold voltage¶0139-0143;forming a third transistor comprising a third gate electrode separated from a third semiconductor by a third interfacial layer, the third interfacial layer comprising a third dipole region, the third transistor having a third threshold voltage Fig 12-15 ¶0139-0143;forming a fourth transistor comprising a fourth gate electrode separated from a fourth semiconductor by a fourth interfacial layer, the fourth interfacial layer comprising a fourth dipole region, the fourth transistor having a fourth threshold voltage Fig 12-15 ¶0139-0143;forming a fifth transistor comprising a fifth gate electrode separated from a fifth semiconductor by a fifth interfacial layer, the fifth interfacial layer comprising a fifth dipole region, the fifth transistor having a fifth threshold voltage Fig 12-15 ¶0139-0143;forming a sixth transistor comprising a sixth gate electrode separated from a sixth semiconductor by a sixth interfacial layer, the sixth interfacial layer comprising a sixth dipole region, the sixth transistor having a sixth threshold voltage Fig 12-15 ¶0139-0143;and forming a seventh transistor comprising a seventh gate electrode separated from a seventh semiconductor by a seventh interfacial layer, the seventh interfacial layer comprising a seventh dipole region Fig 12-15 ¶0139-0143, the seventh transistor having a seventh threshold voltage, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor has a different threshold voltage Fig 12-15 ¶0139-0143. Although Jin discloses a Non planar device Fig 11A, Jin is silent on a Fin Structure. Whereas Wang discloses a method of manufacturing a semiconductor device, the method comprising: forming a first transistor Fig 2D, 240 comprising a first gate electrode separated from a first semiconductor fin by a first interfacial layer Fig 2D, a first dipole region Fig 2D, 212A, the first transistor having a first threshold voltage ¶0007;forming a second transistor Fig 2D, 242 comprising a second gate electrode separated from a second semiconductor fin by a second interfacial layer Fig 2D, a second dipole region Fig 2D, 212B, the second transistor having a second threshold voltage¶0007;forming a third transistor comprising a third gate electrode Fig 2D, 244 separated from a third semiconductor fin by a third interfacial layer Fig 2D, a third dipole region Fig 2D, 214C, the third transistor having a third threshold voltage ¶0007;forming a fourth transistor Fig 2D, 246 comprising a fourth gate electrode separated from a fourth semiconductor fin by a fourth interfacial layer Fig 2D, a fourth dipole region Fig 2D, 212D, the fourth transistor having a fourth threshold voltage ¶0007;forming a fifth transistor comprising a fifth gate electrode separated from a fifth semiconductor by a fifth interfacial layer, the fifth interfacial layer comprising a fifth dipole region, the fifth transistor having a fifth threshold voltage ¶0002-0005;forming a sixth transistor comprising a sixth gate electrode separated from a sixth semiconductor by a sixth interfacial layer, the sixth interfacial layer comprising a sixth dipole region, the sixth transistor having a sixth threshold voltage ¶0002-0005;and forming a seventh transistor comprising a seventh gate electrode separated from a seventh semiconductor by a seventh interfacial layer, the seventh interfacial layer comprising a seventh dipole region ¶0002-0005, the seventh transistor having a seventh threshold voltage, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor has a different threshold voltage ¶0002-0005. Ji and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ji because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Ji and incorporate the teachings of Wang to provide a multi Vt semiconductor device that include specific non planar structures.
Ji discloses all the limitations but silent on specific step of forming the dipole layers. Whereas Chang discloses forming the transistors comprises sequentially depositing, annealing, and removing a plurality of dipole layers Fig 2. Ji and Chang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ji because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Ji and incorporate the teachings of Chang as an alternative method step to provide device isolation and improve device processing step.
Regarding claim 22, Ji discloses wherein the first dipole region comprises a first dipole dopant, and wherein the second dipole region comprises a second dipole dopant different from the first dipole dopant¶0074-0075.
Regarding claim 23, Ji discloses wherein the third dipole region comprises both the first dipole dopant and the second dipole dopant Fig 10E.
Regarding claim 24, Wang in view of Ji discloses wherein the fourth dipole region comprises the first dipole dopant, the second dipole dopant, and a third dipole dopant different from the first dipole dopant and the second dipole dopant ¶0019-0020.
Regarding claim 25, Wang in view of Ji discloses wherein the fifth dipole region comprises the first dipole dopant but not the second dipole dopant and the third dipole dopant¶0019-0020.
Regarding claim 26, Wang in view of Ji discloses wherein the sixth dipole region comprises the second dipole dopant but not the first dipole dopant and the third dipole dopant¶0019-0020.
Response to Arguments
Applicant’s arguments with respect to claims 1-14, 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811