Prosecution Insights
Last updated: August 17, 2026
Application No. 17/897,151

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Final Rejection §103
Filed
Aug 27, 2022
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1137 granted / 1348 resolved
+16.3% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
30 currently pending
Career history
1396
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
64.3%
+24.3% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1348 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US Publication No. 2022/0254891). PNG media_image1.png 514 718 media_image1.png Greyscale Regarding claim 1, More discloses a semiconductor device structure, comprising: a substrate ¶0017 comprising an NMOS region and a PMOS region abutting the NMOS region ¶0018;a first shallow trench isolation (STI) Fig 14, 112 disposed across the PMOS region and the NMOS region Fig 14, PNG media_image2.png 445 198 media_image2.png Greyscale the first STI has a first bottom being slanted from the NMOS region towards the PMOS region Fig 14;a first fin Fig 14, 110c disposed in the PMOS region Fig 14, 102P;a first source/drain epitaxial feature Fig 14, 154 ¶0035 disposed over the first fin Fig 14, 110c;a second fin Fig 14, 108c disposed in the NMOS region Fig 14, 102N;a second source/drain epitaxial feature Fig 14, 152 disposed over the second fin Fig 14, 108c;a first dielectric feature Fig 14, 114c disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature Fig 14, the first dielectric feature having a portion embedded in the first STI Fig 14; and a conductive feature Fig 14, 172 ¶0043 disposed over the first and second source/drain epitaxial features and the first dielectric feature Fig 14. More discloses all the limitations in embodiment 2 but discloses an alternative arrangement in embodiment 1 as illustrated in Fig 13B. Embodiment 1 of More discloses a bottom surface of the first dielectric feature is separated from a top surface by a portion of the first STI Fig 13B. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 2, More discloses a third fin Fig 14, 110b disposed adjacent the first fin Fig 14, 110c;a third source/drain epitaxial feature disposed over the third fin Fig 14, a portion of the third source/drain epitaxial feature being merged with a portion of the first source/drain epitaxial feature Fig 14;a fourth fin Fig 14, 108b disposed adjacent the second fin Fig 14, 108c; and a fourth source/drain epitaxial feature Fig 14, 152 disposed over the fourth fin Fig 14, 108b, a portion of the fourth source/drain epitaxial feature being merged with a portion of the second source/drain epitaxial feature Fig 14. Regarding claim 3, More discloses: a second STI disposed between second fin and the fourth fin, the second STI having a second bottom at an elevation higher than an elevation of the first bottom of the first STI Fig 14. Regarding claim 4, More discloses a third STI disposed between first fin and the third fin, the third STI having a third bottom at an elevation higher than the elevation of the second bottom of the second STI Fig 14. Regarding claim 9, More discloses a silicide layer Fig 14, 170 disposed between the first source/drain epitaxial feature and the conductive feature and between the second source/drain epitaxial feature and the conductive feature Fig 14. Claim 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US Publication No. 2022/0254891) in view of Wu et al (US Publication No. 2018/0151414). Regarding claim 5, More discloses all the limitations but silent on the elevations of the STI. Whereas Wu discloses a fourth STI Fig 8 disposed adjacent the fourth fin Fig 8, the fourth STI having a fourth bottom at an elevation lower than the first bottom of the first STI Fig 8; and a second dielectric feature having a portion embedded in the fourth STI ¶0023-0024 Fig 8.More and Wu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify More because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of More and incorporate the teachings of Wu to provide suitable isolations ¶0023. Regarding claim 6, Wu discloses a fifth STI disposed adjacent the third fin, the fifth STI having a fifth bottom at an elevation between the elevation of the first bottom of the first STI and the elevation of the third bottom of the third STI; and a third dielectric feature having a portion embedded in the fifth STI¶0023-0024 Fig 8. Regarding claim 7, Wu discloses wherein the second and third dielectric features have a height shorter than a height of the first dielectric feature¶0023-0024 Fig 8. Regarding claim 8, Wu discloses wherein the first, second and third dielectric features have a bottom at the same elevation¶0023-0024 Fig 8. Allowable Subject Matter Claims 11-17, 21-23 are allowed over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response f, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest the arrangement/shape of the STIs relative to the well regions , as recited in independent claims 11 and 21. Claims 12-17, 22-23 are also allowed as being directly or indirectly dependent of the allowed independent base claims. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Aug 27, 2022
Application Filed
Oct 27, 2025
Response after Non-Final Action
Dec 18, 2025
Non-Final Rejection (signed) — §103
Feb 05, 2026
Non-Final Rejection mailed — §103
Apr 10, 2026
Applicant Interview (Telephonic)
Apr 10, 2026
Examiner Interview Summary
May 14, 2026
Response Filed
Jul 21, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
95%
With Interview (+10.3%)
1y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1348 resolved cases by this examiner. Grant probability derived from career allowance rate.

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