DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 02/04/2026, with respect to the rejection of claims 1-14 and 21-26 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. The rejection of claims 1-14 and 21-26 has been withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Structure Having Composite Redistribution Structure with Embedded Interconnect Device and IC Package Component.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US-20240063131-A1 – hereinafter Lee) in view of Kang et al. (US-20240006325-A1 – hereinafter Kang).
Regarding claim 1, Lee teaches a semiconductor structure (Fig.1 10; ¶0019), comprising:
a composite redistribution structure (Fig.1 200; ¶0020) comprising a first redistribution structure (Fig.1 200 bottom two layers extending from top of Fig.1 100; ¶0020), a second redistribution structure (Fig.1 200 middle three layers extending from bottom of Fig.1 250; ¶0020) and a third redistribution structure (Fig.1 200 top four layers extending from top of 250; ¶0020), wherein the second redistribution structure (middle three layers of 200) is located between the first redistribution structure (bottom two layers of 200) and the third redistribution structure (top four layers of 200);
a first interconnect device (Fig.1 250; ¶0019) embedded in the second redistribution structure (middle three layers of 200), wherein the first interconnect device (250) comprises a plurality of metal connectors (Fig.1 252; ¶0109) electrically connected to and in contact with vias (Fig.1 233; ¶0045) of the third redistribution structure (top four layers of 200); and
an integrated circuit (IC) package component (Fig.1 300; ¶0019) disposed over the third redistribution structure (top four layers of 200) and electrically connected to the first interconnect device (bottom two layers of 200) via the third redistribution structure (top four layers of 200).
Lee does not teach wherein the first interconnect device contacts the vias at a level of an interface between the second redistribution structure and the third redistribution structure.
Kang teaches a semiconductor structure (Fig.1 1; ¶0017 of Kang) with an embedded IC device (Fig.1 120; ¶0018 of Kang) that connects to vias (Fig.1 115; ¶0020 of Kang) at an interface between two dielectric layers (Fig.1 112; ¶0020 and Fig.1 132; ¶0034 of Kang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the top surface of the embedded chip of Lee (250 of Lee) to be at the interface of the second redistribution structure (middle three layers of 200 of Lee) and the third redistribution structure (top four layers of 200 of Lee) as taught by Kang (Fig.1 of Kang) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Regarding claim 3, the aforementioned combination of Lee in view of Kang from claim 1 teaches the semiconductor structure of claim 1, further comprising:
a second interconnect device (Fig.1 150; ¶0019) disposed on a surface of the first redistribution structure (bottom two layers of 200) relatively far away from the second redistribution structure (middle three layers of 200).
The aforementioned combination does not teach wherein the second interconnect device is coupled to the first redistribution structure using solder connection.
However, the IC package component (300) is coupled using a solder connection (Fig.1 280; ¶0048).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to bond the second interconnect device (150) in the same manner as the IC package component (300) to arrive at the claimed invention. This difference is obvious because it is one of many well-known methods in the art to adhere a chip component to a substrate component.
Regarding claim 4, the aforementioned combination of Lee in view of Kang from claim 3 teaches the semiconductor structure of claim 3, wherein the second interconnect device (150) comprises a main body (150 is the main body), a plurality of conductive connectors (Fig.1 152; ¶0027) and a solder material (280; see claim 3 rejection), the plurality of conductive connectors (152) are electrically connected to the main body (150), and the solder material (280; see claim 3 rejection) is disposed on each of the plurality of conductive connectors (152).
Regarding claim 5, the aforementioned combination of Lee in view of Kang from claim 4 teaches the semiconductor structure of claim 4.
The aforementioned combination does not teach wherein the semiconductor structure is further comprising:
an underfill disposed in a gap between the main body of the second interconnect device and the first redistribution structure.
However, the IC package component (300) is coupled using an underfill (Fig.1 290; ¶0050) surrounding the solder connection (280).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add an underfill layer (290) in the same manner as the IC package component (300) connection to surround the solder connections (280; see claim 3 rejection) and arrive at the claimed invention. A practitioner would be motivated to make this modification for the benefit of improving the reliability and durability of the solder joints from claim 3.
Claim(s) 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang (US-10756054-B1).
Regarding claim 21, Lee teaches a semiconductor structure (Fig.1 10; ¶0019, comprising:
a composite redistribution structure (Fig.1 200; ¶0020) comprising a first redistribution structure (Fig.1 200 bottom two layers extending from top of Fig.1 100; ¶0020), a second redistribution structure (Fig.1 200 middle three layers extending from bottom of Fig.1 250; ¶0020) and a third redistribution structure (Fig.1 200 top four layers extending from top of 250; ¶0020), wherein the second redistribution structure (middle three layers of 200) is located between the first redistribution structure (bottom two layers of 200) and the third redistribution structure (top four layers of 200);
a first interconnect device (Fig.1 250; ¶0019) embedded in the second redistribution structure (middle three layers of 200) and electrically connected to the third redistribution structure (top four layers of 200); and
an integrated circuit (IC) package component (Fig.1 300 and 400; ¶0019) disposed over the third redistribution structure (top four layers of 200) and electrically connected to the first interconnect device (250) via the third redistribution structure (top four layers of 200).
Lee does not teach wherein, in a cross-sectional view, a lateral dimension of the IC package component overlaps a whole span of the first interconnect device.
Huang teaches an embedded die (Fig.1D 141; col.3 lines 35-50 of Huang) that is fully overlapped by an upper die (Fig.1D 143; col.6 lines 24-35 of Huang) that is disposed on top of a dielectric layer (Fig.1D 18; col.5 lines 58-65 of Huang) located between both dies (141 and 143 of Huang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the top package components of Lee (300 and 400 of Lee) to instead be a larger single die like that taught by Huang (143 of Huang) occupying the same footprint to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Regarding claim 22, the aforementioned combination of Lee in view of Huang from claim 21 teaches the semiconductor structure of claim 21, further comprising:
a second interconnect device (Fig.1 150; ¶0019) disposed on a surface of the first redistribution structure (bottom two layers of 200) relatively far away from the second redistribution structure (middle three layers of 200).
The aforementioned combination does not teach wherein the second interconnect device is coupled to the first redistribution structure using solder connection.
However, the IC package component (300) is coupled using a solder connection (Fig.1 280; ¶0048).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to bond the second interconnect device (150) in the same manner as the IC package component (300) to arrive at the claimed invention. This difference is obvious because it is one of many well-known methods in the art to adhere a chip component to a substrate component.
Regarding claim 23, the aforementioned combination of Lee in view of Huang from claim 22 teaches the semiconductor structure of claim 22, wherein the second interconnect device (150) comprises a main body (150 is the main body), a plurality of conductive connectors (Fig.1 152; ¶0027) and a solder material (280; see claim 22 rejection), the plurality of conductive connectors (152) are electrically connected to the main body (150), and the solder material (280; see claim 22 rejection) is disposed on each of the plurality of conductive connectors (152).
Regarding claim 24, the aforementioned combination of Lee in view of Huang from claim 23 teaches the semiconductor structure of claim 23.
The aforementioned combination does not teach wherein the second interconnect structure is further comprising:
an under-fill disposed in a gap between the main body of the second interconnect device and the first redistribution structure.
However, the IC package component (300) is coupled using an underfill (Fig.1 290; ¶0050) surrounding the solder connection (280).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add an underfill layer (290) in the same manner as the IC package component (300) connection to surround the solder connections (280; see claim 3 rejection) and arrive at the claimed invention. A practitioner would be motivated to make this modification for the benefit of improving the reliability and durability of the solder joints from claim 3.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kang, and further in view of Xu et al. (US-20230068875-A1 – hereinafter Xu).
Regarding claim 2, the aforementioned combination of Lee in view of Kang from claim 1 teaches the semiconductor structure of claim 1, wherein the first interconnect device (250) further comprises a main body (250 is a main body), the plurality of metal connectors (252) is disposed on one side of the main body (250).
The aforementioned combination does not explicitly teach a protective layer and wherein the protective layer is disposed on the main body and fills gaps between the plurality of metal connectors.
Xu teaches a chip (Fig.1 10; ¶0033 of Xu) having a main body (Fig.1 11; ¶0033 of Xu), metal connectors (Fig.1 13; ¶0033 of Xu) and a protective layer (Fig.1 12; ¶0033 of Xu) disposed on the main body (11 of Xu) and the metal connectors (13 of Xu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add a protective layer (12 of Xu) disposed on the main body (250 of Lee) and surrounding the metal connectors (252 of Lee) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for improved chip reliability (¶0038 of Xu).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang, and further in view of Xu et al. (US-20230068875-A1 – hereinafter Xu).
Regarding claim 25, the aforementioned combination of Lee in view of Huang from claim 21 teaches the semiconductor structure of claim 21, wherein the first interconnect device (250) further comprises a main body (250 is a main body) and a plurality of metal connectors (Fig.1 252; ¶0109) leveled with a surface of the second redistribution structure (middle three layers of 200), the plurality of metal connectors (252) is disposed on one side of the main body (250).
The aforementioned combination does not teach a protective layer and wherein the protective layer is disposed on the main body and fills gaps between the plurality of metal connectors.
Xu teaches a chip (Fig.1 10; ¶0033 of Xu) having a main body (Fig.1 11; ¶0033 of Xu), metal connectors (Fig.1 13; ¶0033 of Xu) and a protective layer (Fig.1 12; ¶0033 of Xu) disposed on the main body (11 of Xu) and the metal connectors (13 of Xu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add a protective layer (12 of Xu) disposed on the main body (250 of Lee) and surrounding the metal connectors (252 of Lee) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for improved chip reliability (¶0038 of Xu).
Claim(s) 6-8 and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view Kang, and further in view of Su et al. (US-20250015019-A1 – hereinafter Su).
Regarding claim 6, the aforementioned combination of Lee in view of Kang from claim 1 teaches the semiconductor structure of claim 1.
The aforementioned combination does not teach the semiconductor structure further comprising:
a substrate component comprising a core layer, a fourth redistribution structure interposed between the core layer and the first redistribution structure, a fifth redistribution structure underlying the core layer , and through core vias penetrating through the core layer and electrically coupled to the fourth redistribution structure and fifth redistribution structure.
Lee does, however, teach a lower connection point (Fig.1 160; ¶0031) for attaching the semiconductor structure (10) to a larger substrate component, like a board.
Su teaches a substrate (Fig.1A 100; ¶0043 of Su) having a core layer (Fig.1A 120; ¶0043 of Su), a fourth redistribution structure (Fig.1A 160 upper portion; ¶0044 of Su), a fifth redistribution structure (Fig.1A 160 lower portion; ¶0044 of Su and through vias (Fig.1A 175; ¶0044 of Su) that penetrate the core (120 of Su) and electrically couple both the fourth and fifth redistribution structures (160 of Su).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach the semiconductor structure of Lee (10 of Lee) to the substrate of Su (100 of Su) in place of a semiconductor die (Fig.1A 110; ¶0043 of Su) to arrive at the claimed invention. This combination is obvious because ¶0043 of Su states that the dies (110 of Su) can be replaced with other semiconductor devices. The semiconductor package of Lee (10 of Lee) is a suitable replacement with the already existing connection points (160 of Lee).
Regarding claim 7, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 6 teaches the semiconductor structure of claim 6, wherein the first redistribution structure (bottom two layers of 200 of Lee) is coupled to the substrate component (100 of Su) using solder connection (Fig.1 160; ¶0031 of Lee and Fig.1A 130; ¶0043 of Su).
Regarding claim 8, Lee teaches a semiconductor structure, comprising:
an integrated circuit (IC) package component (Fig.1 300; ¶0019);
a composite redistribution structure (Fig.1 200; ¶0020) electrically coupled to the IC package component (300), the composite redistribution structure (200) comprising a first redistribution structure (Fig.1 200 bottom three two extending from bottom of Fig.1 250; ¶0020), a second redistribution structure (Fig.1 200 middle three layers extending from bottom of Fig.1 250; ¶0020) and a third redistribution structure (Fig.1 200 top four layers extending from bottom of Fig.1 250; ¶0020), the third redistribution structure (top four layers of 200) underlying the IC package component (300), and the second redistribution structure (middle three layers of 200) located between the first redistribution structure (bottom two layers of 200) and the third redistribution structure (top four layers of 200); and
a first interconnect device (Fig.1 250; ¶0019) embedded in the second redistribution structure (middle three layers of 200) and electrically connected to the IC package component (300) by the third redistribution structure (top four layers of 200), wherein the composite redistribution structure (200) comprises dielectric layers (depicted throughout Fig.1), and a top surface of the first interconnect device (250) is in contact with one of the dielectric layers (200).
Lee does not teach wherein the first interconnect device contacts dielectric layers at a level where the one of the dielectric layers is in contact with another one of the dielectric layers.
Kang teaches a semiconductor structure (Fig.1 1; ¶0017 of Kang) with an embedded IC device (Fig.1 120; ¶0018 of Kang) that connects to vias (Fig.1 115; ¶0020 of Kang) at an interface between two dielectric layers (Fig.1 112; ¶0020 and Fig.1 132; ¶0034 of Kang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the top surface of the embedded chip of Lee (250 of Lee) to be at the interface of the second redistribution structure (middle three layers of 200 of Lee) and the third redistribution structure (top four layers of 200 of Lee) as taught by Kang (Fig.1 of Kang) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Lee in view of Kang does not teach wherein the semiconductor structure comprises a substrate component;
wherein the IC package component is disposed over the substrate component;
wherein the composite redistribution structure is interposed between and electrically connected to the substrate component; and
wherein the first redistribution structure is overlying the substrate component.
Lee does, however, teach a lower connection point (Fig.1 160; ¶0031) for attaching the semiconductor structure (10) to a larger substrate component, like a board.
Su teaches a substrate (Fig.1A 100; ¶0043 of Su) having a core layer (Fig.1A 120; ¶0043 of Su), a fourth redistribution structure (Fig.1A 160 upper portion; ¶0044 of Su), a fifth redistribution structure (Fig.1A 160 lower portion; ¶0044 of Su and through vias (Fig.1A 175; ¶0044 of Su) that penetrate the core (120 of Su) and electrically couple both the fourth and fifth redistribution structures (160 of Su).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach the semiconductor structure of Lee (10 of Lee) to the substrate of Su (100 of Su) in place of a semiconductor die (Fig.1A 110; ¶0043 of Su) to arrive at the claimed invention. This combination is obvious because ¶0043 of Su states that the dies (110 of Su) can be replaced with other semiconductor devices. The semiconductor package of Lee (10 of Lee) is a suitable replacement with the already existing connection points (160 of Lee).
Regarding claim 10, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 8 teaches the semiconductor structure of claim 8, further comprising:
a second interconnect device (Fig.1 150; ¶0019 of Lee) disposed on a surface of the first redistribution structure (bottom two layers of 200 of Lee) relatively far away from the second redistribution structure (middle three layers of 200 of Lee).
The aforementioned combination does not teach wherein the second interconnect device is coupled to the first redistribution structure using solder connection.
However, the IC package component (300 of Lee) is coupled using a solder connection (Fig.1 280; ¶0048 of Lee).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to bond the second interconnect device (150 of Lee) in the same manner as the IC package component (300 of Lee) to arrive at the claimed invention. This difference is obvious because it is one of many well-known methods in the art to adhere a chip component to a substrate component.
Regarding claim 11, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 10 teaches the semiconductor structure of claim 10, wherein the second interconnect device (150 of Lee) comprises a main body (150 of Lee is a main body), a plurality of conductive connectors (Fig.1 152; ¶0027 of Lee) and a solder material (280 of Lee; see claim 10 rejection), the plurality of conductive connectors (152 of Lee) are electrically connected to the main body (150 of Lee), and the solder material (280 of Lee; see claim 10 rejection) is disposed on each of the plurality of conductive connectors (152 of Lee).
Regarding claim 12, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 11 teaches the semiconductor structure of claim 11.
The aforementioned combination does not teach the semiconductor structure further comprising:
an underfill disposed in a gap between the main body of the second interconnect device and the first redistribution structure.
However, the IC package component (300 of Lee) is coupled using an underfill (Fig.1 290; ¶0050 of Lee) surrounding the solder connection (280 of Lee).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add an underfill layer (290 of Lee) in the same manner as the IC package component (300 of Lee) connection to surround the solder connections (280 of Lee; see claim 3 rejection) and arrive at the claimed invention. A practitioner would be motivated to make this modification for the benefit of improving the reliability and durability of the solder joints from claim 3.
Regarding claim 13, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 12 teaches the semiconductor structure of claim 12, further comprising:
a protective layer (Fig.1 140; ¶0019 of Lee) disposed in a gap between the first redistribution structure (bottom two layers of 200 of Lee) and the substrate component (100 of Su) to cover the second interconnect device (150 of Lee) and the underfill (290 of Lee; see claim 12 rejection).
Claim(s) 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang, and further in view of Wu et al. (US-20200006241-A1 – hereinafter Wu).
Regarding claim 26, the aforementioned combination of Lee in view of Huang from claim 21 teaches the semiconductor structure of claim 21, further comprising:
an encapsulant (Fig.1 350; ¶0019) disposed on the third redistribution structure (top four layers of 200) to encapsulate the IC package component (300).
The aforementioned combination does not teach wherein a top surface of the IC package component is leveled with a surface of the encapsulant.
Wu teaches a semiconductor package (Fig.5; ¶0060 of Wu) having semiconductor devices (Fig.5 301; ¶0060 of Wu) that are encapsulated with an encapsulant (Fig.5 501; ¶0060 of Wu) that is level with the tops of the semiconductor devices (301 of Wu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to keep the top surface of the encapsulant (350 of Lee) level with the IC component (300 of Lee) to arrive at the claimed invention. A practitioner would have been motivated to make this modification to expose the top surfaces of the semiconductor devices for further processing (¶0060 of Wu).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kang, and further in view of Su, and further in view of Xu.
Regarding claim 9, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 8 teaches the semiconductor structure of claim 8, wherein the first interconnect device (250 of Lee) further comprises a main body (250 of Lee is a main body), a plurality of metal connectors (Fig.1 252; ¶0109), the plurality of metal connectors (252 of Lee) disposed on the main body (250 of Lee) are leveled with a surface of the second redistribution structure (middle three layers of 200 of Lee) and electrically connected to the third redistribution structure (top four layers of 200 of Lee).
Lee does not explicitly teach a protective layer and wherein the protective layer is disposed on the main body and fills gaps between the plurality of metal connectors.
Xu teaches a chip (Fig.1 10; ¶0033 of Xu) having a main body (Fig.1 11; ¶0033 of Xu), metal connectors (Fig.1 13; ¶0033 of Xu) and a protective layer (Fig.1 12; ¶0033 of Xu) disposed on the main body (11 of Xu) and the metal connectors (13 of Xu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add a protective layer (12 of Xu) disposed on the main body (250 of Lee) and surrounding the metal connectors (252 of Lee) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for improved chip reliability (¶0038 of Xu).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kang, and further in view of Su, and further in view of Wu.
Regarding claim 14, the aforementioned combination of Lee in view of Kang, and further in view of Su from claim 8 teaches the semiconductor structure of claim 8, further comprising:
an encapsulant (Fig.1 350; ¶0019 of Lee) disposed on the third redistribution structure (top four layers of 200 of Lee) to encapsulate the IC package component (300 of Lee).
The aforementioned combination does not teach wherein a top surface of the IC package component is leveled with a surface of the encapsulant.
Wu teaches a semiconductor package (Fig.5; ¶0060 of Wu) having semiconductor devices (Fig.5 301; ¶0060 of Wu) that are encapsulated with an encapsulant (Fig.5 501; ¶0060 of Wu) that is level with the tops of the semiconductor devices (301 of Wu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to keep the top surface of the encapsulant (350 of Lee) level with the IC component (300 of Lee) to arrive at the claimed invention. A practitioner would have been motivated to make this modification to expose the top surfaces of the semiconductor devices for further processing (¶0060 of Wu).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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