Prosecution Insights
Last updated: April 19, 2026
Application No. 17/898,104

METHODS FOR FORMING SEMICONDUCTOR DEVICES WITH ISOLATION STRUCTURES

Non-Final OA §102§103
Filed
Aug 29, 2022
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
65%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
695 granted / 899 resolved
+9.3% vs TC avg
Minimal -12% lift
Without
With
+-12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
48 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§103
57.6%
+17.6% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 899 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/2/2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 5-9, 11-14, 16, & 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUK et al. (US 20190229011). Regarding claim 1, SUK discloses that a method for forming a semiconductor device, comprising: forming a first layer 201a directly on a substrate 100 without an intermediary structure (Fig. 1); forming a second layer 202a on the first layer 201a, wherein the substrate 100 and the second layer 202a have a first semiconductor material and the first layer has a second semiconductor material, and wherein an etching selectivity is present between the first semiconductor material and the second semiconductor material (para. 0019 & 0022, note: substrate -Si, element 201- SiGe or Ge, element 202- Si or a group III-V compound semiconductor); and performing a first etching process in a trench formation region configured to receive an isolation structure R1 to remove a portion of the second layer 202a until the first layer 201a (Fig 2) is exposed and to stop on the first layer 201a, wherein the first layer is configured as an etch stop layer for the first etching process based on the etching selectivity for defining a trench depth for the isolation structure (Fig. 2). Reclaim 2, SUK discloses that the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium (para. 0019 & 0022). Reclaim 5, SUK discloses that, prior to performing the first etching process, further comprising: forming a layer stack over the second layer, wherein the layer stack includes a plurality of third layers and a plurality of fourth layers alternately stacked on top of one another, and wherein the plurality of third layers each have the first semiconductor material and the plurality of fourth layers each have a third semiconductor material; and performing a second etching process to remove a portion of the layer stack, wherein the removed portion of the layer stack is vertically aligned with the removed portion of the second layer (Fig. 1). Reclaim 6, SUK discloses that, subsequent to performing the first etching process, further comprising: performing a third etching process to remove a portion of the first layer, wherein the removed portion of the first layer is vertically aligned with the removed portion of the second layer (Fig. 2). Reclaim 7, SUK discloses that filling 400 the removed portion of the second layer and the removed portion of the first layer with a dielectric material thereby forming an isolation structure (Fig. 3-4). Reclaim 8, SUK discloses that the isolation structure 500 is configured to electrically isolate remaining portions of the layer stack that are disposed on opposite sides of the removed portion of the layer stack (Fig. 6). Reclaim 9, SUK discloses that the first semiconductor material includes silicon, the second semiconductor material includes first silicon germanium with a first germanium molar ratio, and the third semiconductor material includes second silicon germanium with a second germanium molar ratio (Fig. 3, para. 0022). Regarding claim 11, SUK discloses that a method for forming a semiconductor device, comprising: forming, directly on a substrate 100 having a first semiconductor material 201a, a first layer having a second semiconductor material (para. 0019 & 0022); overlaying the first layer 201a with a second layer202a having the first semiconductor material; forming a layer stack 211-212 over the second layer 202a, wherein the layer stack 201-202 includes a plurality of third layers and a plurality of fourth layers alternately stacked on top of one another, and wherein the plurality of third layers each have the first semiconductor material and the plurality of fourth layers each have a third semiconductor material; etching a portion of the layer stack until the second layer is exposed; and etching, in a trench formation region R1 configured to receive an isolation structure through at least the etched portion of the layer stack, a portion of the second layer 202a until the first layer is exposed (Fig. 2) and to stop on the first layer 201a, wherein first layer is configured as an etch stop layer for defining a trench depth for the isolation structure (Fig. 2). Reclaim 12, SUK discloses that etching, through at least the etched portion of the layer stack 201-202 and the etched portion of the second layer 202a, a portion of the first layer 201a until a top surface of the substrate is exposed (Fig. 4); and filling the etched portion of the second layer and the etched portion of the first layer with a dielectric material 500 thereby forming an isolation structure (Fig. 2-3). Reclaim 13, SUK discloses that etching, through at least the etched portion of the layer stack and the etched portion of the second layer, a portion of the first layer (Fig, 4-5) and a portion of the substrate 100 until an intermediate surface of the substrate is exposed; and filling the etched portion of the second layer, the etched portion of the first layer, and the etched portion of the substrate with a dielectric material 500 thereby forming an isolation structure (Fig. 2-3, para. 0022). Reclaim 14, SUK discloses that the first semiconductor material includes silicon, the second semiconductor material includes first silicon germanium with a first germanium molar ratio, and the third semiconductor material includes second silicon germanium with a second germanium molar ratio (Fig. 2-3, para. 0019 & 0022). Reclaim 16, SUK discloses that the first layer 201a is configured as an etch stop layer during etching the portion of the second layer 202a (Fig. 2-3). Regarding claim 18, SUK discloses that a method for forming a semiconductor device, comprising: forming one or more etch stop layers 201a having a second semiconductor material embedded in a first semiconductor material 202a; defining an active region 222 of a transistor on the first semiconductor material; etching, in an isolation trench region 221r disposed between active device regions 222 and configured to receive a dielectric isolation structure 720, first portions of the first semiconductor material disposed above at least one of the one or more etch stop layers and on opposite sides of the active region (Fig. 23-24 & 29-31), respectively, until the at least one etch stop layer is exposed and to stop on the first layer 2010a, wherein the at least one etch stop layer is configured to halt the etching based on etching selectivity between the first and second semiconductor materials so as to define a uniform trench depth for the isolation structure; and forming an isolation structure by filling at least the etched first portions of the first semiconductor material with a dielectric material (Fig. 29-31). Reclaim 19, SUK discloses that the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium (para. 0019 & 0022). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3-4, 10, 15, 17, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUK et al. (US 20190229011). Reclaims 3 & 20, SUK fails to specify that that a molar ratio of germanium of the second semiconductor material is equal to or greater than ½ . However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain molar ratio of germanium of the second semiconductor material, because it would have been to obtain a certain molar ratio of germanium of the second semiconductor material to achieve to enhance etchability. Reclaims 4 & 17, SUK fails to specify that a ratio of the etching selectivity is equal to or greater than 1/100. However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain ratio of the etching selectivity, because it would have been to obtain a certain ratio of the etching selectivity to achieve to enhance etchability. Reclaims 10 & 15, SUK fails to specify the first germanium molar ratio is substantially greater than the second germanium molar ratio. However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain molar ratio of the first germanium and the second germanium of the etching selectivity, because it would have been to obtain a certain molar ratio of the first germanium and the second germanium of the etching selectivity to achieve to enhance etchability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
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Prosecution Timeline

Aug 29, 2022
Application Filed
Jul 22, 2025
Non-Final Rejection — §102, §103
Sep 30, 2025
Interview Requested
Oct 07, 2025
Examiner Interview Summary
Oct 07, 2025
Applicant Interview (Telephonic)
Oct 09, 2025
Response Filed
Dec 06, 2025
Final Rejection — §102, §103
Jan 26, 2026
Response after Non-Final Action
Feb 02, 2026
Request for Continued Examination
Feb 09, 2026
Response after Non-Final Action
Mar 16, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
65%
With Interview (-12.4%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 899 resolved cases by this examiner. Grant probability derived from career allow rate.

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