DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeung et al. (US 20180261670).
Regarding claim 1, Yeung discloses that a method for forming a semiconductor device, comprising:
forming a first layer 204 directly on a substrate 202 (para. 0051, Si substrate) without an intermediary structure;
forming a second layer 205 on the first layer 204, wherein the substrate 202 and the second layer 205 have a first semiconductor material and the first layer 204 has a second semiconductor material 205, and wherein an etching selectivity is present between the first semiconductor material Si and the second semiconductor material SiGe;
forming a layer stack 207 & 206 over the second layer 205 including at least one layer with a third semiconductor material;
performing a first etching process to remove a portion of the layer stack (Fig. 3C); and
performing a [[first]] second etching process (Fig. 5C) in a trench formation region configured to receive an isolation structure to remove a portion of the second layer until the first layer 204 is exposed and to stop on the first layer 204 (Fig. 5C), wherein the first layer 204 is configured as an etch stop layer for the [[first]] second etching process based on the etching selectivity for defining a trench depth for [[the]] an isolation structure, wherein the second semiconductor material 205 has a first germanium molar ratio (para. 0063) and the third semiconductor material has a second germanium molar ratio, and wherein the first germanium molar ratio is substantially greater than the second germanium molar ratio (para. 0063 & 0064).
Reclaim2, Yeung discloses that the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium (para. 0063 & 0064).
Reclaim 3, Yeung discloses that a molar ratio of germanium of the second semiconductor material is equal to or greater than ½ (para. 0063 & 0064).
Reclaim 4, Yeung discloses that a ratio of the etching selectivity is equal to or greater than 1/100 (para. 0063 & 0064).
Reclaim 5, Yeung discloses that prior to performing the first etching process, further comprising: forming a layer stack over the second layer, wherein the layer stack includes a plurality of third layers and a plurality of fourth layers alternately stacked on top of one another, and wherein the plurality of third layers each have the first semiconductor material and the plurality of fourth layers each have [[a]] the third semiconductor material; and performing a second etching process to remove a portion of the layer stack, wherein the removed portion of the layer stack is vertically aligned with the removed portion of the second layer (Fig. 4B).
Reclaim 6, Yeung discloses that subsequent to performing the [[first]] second etching process, further comprising: performing a third etching process to remove a portion of the first layer, wherein the removed portion of the first layer is vertically aligned with the removed portion of the second layer (Fig. 5C).
Reclaim 7, Yeung discloses that filling the removed portion of the second layer and the removed portion of the first layer with a dielectric material 601 thereby forming an isolation structure (Fig. 6C).
Reclaim 8, Yeung discloses that the isolation structure 601 is configured to electrically isolate remaining portions of the layer stack that are disposed on opposite sides of the removed portion of the layer stack (Fig. 6C).
Reclaim 9, Yeung discloses that the first semiconductor material includes silicon, the second semiconductor material includes first silicon germanium with a first germanium molar ratio, and the third semiconductor material includes second silicon germanium with a second germanium molar ratio (para. 0063 & 0064).
Reclaim 10, Yeung discloses that the first germanium molar ratio is substantially greater that at least twice the second germanium molar ratio (para. 0063 & 0064).
Reclaim 11, Yeung discloses that a method for forming a semiconductor device, comprising:
forming, directly on a substrate having a first semiconductor material 202, a first layer 204 having a second semiconductor material; overlaying the first layer 204 with a second layer 205 having the first semiconductor material;
forming a layer stack 206 & 207 over the second layer, wherein the layer stack includes a plurality of third layers 206 and a plurality of fourth layers 207 alternately stacked on top of one another, and wherein the plurality of third layers 206 each have the first semiconductor material (para. 0064, Si SiGe) and the plurality of fourth layers 207 each have a third semiconductor material (Fig. 4B, para. 0063, SiGe);
etching a portion of the layer stack until the second layer 205 is exposed (Fig. 4C);
and etching, in a trench formation region configured to receive an isolation structure through at least the etched portion of the layer stack (Fig. 5C), a portion of the second layer until the first layer is exposed and to stop on the first layer, wherein first layer 204 is configured as an etch stop layer for defining a trench depth for the isolation structure 601, wherein the second semiconductor material 204 (para. 0063) has a first germanium molar ratio, wherein the third semiconductor 206 material has a second germanium molar ratio, and wherein the first germanium molar ratio is substantially greater than the second germanium molar ratio (para. 0063 & 0064).
Reclaim 12, Yeung discloses that etching, through at least the etched portion of the layer stack and the etched portion of the second layer, a portion of the first layer until a top surface of the substrate is exposed; and filling the etched portion of the second layer and the etched portion of the first layer with a dielectric material thereby forming an isolation structure.
Reclaim 13, Yeung discloses that etching, through at least the etched portion of the layer stack and the etched portion of the second layer, a portion of the first layer and a portion of the substrate until an intermediate surface of the substrate is exposed; and filling the etched portion of the second layer, the etched portion of the first layer, and the etched portion of the substrate with a dielectric material thereby forming an isolation structure (para. 0063 & 0064).
Reclaim 14, Yeung discloses that the first semiconductor material includes silicon, the second semiconductor material includes first silicon germanium with [[a]] the first germanium molar ratio, and the third semiconductor material includes second silicon germanium with [[a]] the second germanium molar ratio (para. 0063 & 0064).
Reclaim 15, Yeung discloses that the first germanium molar ratio is substantially greater than at least twice the second germanium molar ratio (para. 0063 & 0064).
Reclaim 16, Yeung discloses that the first layer is configured as an etch stop layer during etching the portion of the second layer (para. 0063 & 0064).
Reclaim 17, Yeung discloses that an etching selectivity is present between the first semiconductor material and the second semiconductor material, and wherein a ratio of the etching selectivity is equal to or greater than 1/100 (para. 0063 & 0064).
Reclaim 18, Yeung discloses that a method for forming a semiconductor device, comprising:
forming one or more etch stop layers 204 having a second semiconductor material embedded in a first semiconductor material 202 (Fig. 4C);
forming a layer stack over the one or more etch stop layers, wherein the layer stack includes at least one layer with a third semiconductor material;
defining an active region of a transistor on the first semiconductor material;
etching, in an isolation trench region 601 disposed between active device regions and configured to receive a dielectric isolation structure, first portions of the first semiconductor material disposed above at least one of the one or more etch stop layers and on opposite sides of the active region, respectively, until the at least one etch stop layer is exposed and to stop on the first layer 204, wherein the at least one etch stop layer is configured to halt the etching based on etching selectivity between the first and second semiconductor materials so as to define a uniform trench depth for the isolation structure (Fig. 5C); and
forming an isolation structure 601 by filling at least the etched first portions of the first semiconductor material with a dielectric material, wherein the second semiconductor material has a first germanium molar ratio, and the third semiconductor has a second germanium molar ratio, and wherein the first germanium molar ratio is substantially greater than the second germanium molar ratio (para. 0063 & 0064).
Reclaim 19. (Original) The method of claim 18, wherein the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium (para. 0063 & 0064).
Reclaim 20. (Original) The method of claim 19, wherein a molar ratio of germanium of the second semiconductor material is equal to or greater than ½ (para. 0063 & 0064).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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