Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 1, 2023; July 5, 2023; and December 3, 2024 are filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group 1 in the Response filed on August 26, 2025 is acknowledged. As initially presented in the Restriction Requirement of July 2, 2025, Invention Group 1 consisted of Claims 1-7, 17, and 18. However, following Applicant’s amendment filed as part of the Response, Claims 8-16 now depend from Claim 1, thus Group I presents a unified claim set of a singular invention consisting of Claims 1-18.
Therefore, an action on the merits of Claims 1-18 follows in the current Office Action.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--A Standard Cell Comprising A STI Region Having A Top Surface Above A Substrate Which Surrounds NMOS and PMOS Transistors Which Themselves Are Separated By A Distance Defined By Fin Pitch And Fin Width—
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation "the channel layer comprises a top portion covering a top surface of the fin structure" must be shown or the feature canceled from the claims, particularly Claim 10. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 6 and 15-18 are objected to because of the following informalities:
Regarding Claim 6, the limitation “to the second metal line without though the first metal line” should read --to the second metal line without going through the first metal line—
Regarding Claim 15, the limitations “first type transistor” and “second type transistor” should read --first-type transistor-- and --second-type transistor--, respectively.
Regarding Claim 16, the limitations “first type transistor” and “second type transistor” should read --first-type transistor-- and --second-type transistor--, respectively.
Regarding Claim 17, the limitation “to the second metal line without though the first metal line” should read --to the second metal line without going through the first metal line--
Regarding Claim 18, the limitation “The standard cell according to claim 17, herein” should read --The standard cell according to claim 17, wherein--
Appropriate correction is required.
For the purposes of this Office Action, the limitations of Claims 6 and 15-18 as quoted above shall be read by the Examiner in the corrected forms indicated by the dashes (--) above.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 6, 15, and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Regarding Claims 6, 15, and 16, the claim limitation “a minimum feature size (λ)” and its incorporation in other claimed limitations (e.g. “an area size of the standard cell in terms of λ2” (Claim 6), “the fin pitch distance between the two adjacent fin structures in the first-type transistor is between 3~5λ” (Claim 15), and “the gap between the first-type transistor and the second-type transistor is between 8~12λ” (Claim 16)) are not described in the specification in such a way as to enable one skilled in the art to make and/or use the invention without undue experimentation. Details are given below.
The breadth of the claims:
Claims 6, 15, and 16 require certain device characteristics (e.g. an area size, a fin pitch, and a gap) to be based on the value of a minimum feature size (λ). Every device that is manufactured is done so with a minimum feature size, but as claimed there are no bounds provided, thus the claim incorporates scaling both not yet proven (future minimum feature sizes) and those not physically possible.
The nature of the invention:
The disclosure relates to a standard cell incorporating finFet devices manufactured using standard techniques including the use of dummy shield gates (DSGs), selective epitaxy growth (SEG), etc.
The state of the prior art and (D) the level of one of ordinary skill:
Ching et al. (U.S. Pub. 2018/0350969), hereinafter Ching, relates to a finFet device as incorporable in standard cells. As noted in Ching Paragraph [0002], by scaling down semiconductor IC dimensions (e.g. as minimum feature size decreases), increased complexity is introduced to the manufacturing process, and in particular new advances in semiconductor manufacturing processes are required. Moreover, one of ordinary skill in the art would easily recognize that exact scalability cannot be achieved for devices as the minimum feature size decreases. This is because as the minimum feature size decreases with no change to device plans, quantum effects (namely quantum tunneling) would impact device performance if not render them inoperable.
The level of predictability in the art:
The level of predictability as it relates to continued decreasing of a minimum feature size and the presence of quantum effects is high, as the first is a well-known and sought endeavor in the field and the second is a principle of physics. The level of predictability as it relates to scaling of the instant invention (i.e. at what value of λ is the device inoperable or not capable of being formed using disclosed / known techniques) is unknown, both as it relates to manufacturing capabilities and quantum effects.
The amount of direction provided by the inventor and (G) the existence of working examples:
In the instant application’s Specification, the Applicant has provided references to certain structural sizes (such as the Cell_Height and Contact to Poly Pitch (Cpp)) against minimum feature sizes of λ = 16, 10, 7, and 5 nms. (Paragraphs [0009] – [0012]; Fig. 4). Additionally, Applicant has referenced that the invention would apply to 28 nm or lower technologies (Paragraph [0083]), or as λ changed from 22nm to 16nm or from 22nm to 5nm (Paragraph [0086]). The standard cell disclosed by the Applicant (500) in Figs. 5(a) and 5(b) is said to represent a device wherein λ=5nm. However, Applicant provides no support as to how the device would be manufactured once certain fundamental limits are reached nor how quantum effects are prevented at such a scale. No such working examples, following a similar design of the instant application’s invention, are available.
The quantity of experimentation needed to make or use the invention based on the content of the disclosure:
Based on instruction given by the disclosure, experimentation of precise deposition, etching, and lithography, based on numerous technology nodes (notably, including those not known publicly or invented), would need to be tested to determine the bounds of the applicable minimum feature size (λ), such that the device could be manufactured and operated as intended.
The Examiner concludes that undue experimentation would be necessary in order to enable one of ordinary skill in the art to create the device of Claims 6, 15, and 16 wherein a non-limited minimum feature size (λ) is used.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 6, the limitation “wherein as a minimum feature size (λ) of the standard cell gradually decreases for different technology nodes, an area size of the standard cell in terms of λ2 is the same or substantially the same.” is unclear as to how it further limits the claimed device and what are the intended structural consequences. The claim is directed to a “standard cell” which is a static device (i.e. is completed and has definitive physical characteristics), therefore it is unclear how the cell could have decreased sizes during formation. The limitation instead seems to be directed towards a design philosophy to approach manufacturing. Thus, when the limitation is read as part of a device claim, it renders the claim indefinite.
For the purposes of this Office Action, the limitation of Claims 6 as quoted above shall be read by the Examiner as follows:
--an area size of the standard cell is in terms of λ2, where λ is a minimum feature size of the standard cell.--
Regarding Claim 8, the limitation “wherein the channel layer or the conductive region is independent from the semiconductor substrate and is doped without applying an ion implantation.” has unclear syntax as to whether being independent from the substrate and being doped must both be true for either the channel layer or the conductive region, or if they separately can have either limitation (i.e. the channel layer is independent from the substrate while the conductive region is doped). Furthermore, the limitation lacks a proper form as it relates to the structure being claimed as a standard cell (“without applying an ion implantation” has no patentable weight in a device claim) and lacks an antecedent basis in regards to the doping.
For the purposes of this Office Action, the limitation of Claims 8 as quoted above shall be read by the Examiner as follows:
--wherein the channel layer or the conductive region is simultaneously both independent from the semiconductor substrate and comprises a dopant--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Omura (U.S. Pub. 2011/0272776), hereinafter Omura.
Regarding Claim 1, Omura teaches a standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]), comprising:
-a plurality of transistors (NMOS (NT1) and PMOS (PT1); Figs. 3 and 4, Paragraph [0048]) within a semiconductor substrate ((SS); Figs. 3-5, Paragraph [0043]) which includes an original surface (e.g. an exposed surface where the substrate is the thickest, e.g. outer edges in Fig. 2), wherein the plurality of transistors comprises an NMOS transistor (NT1);
- a STI region ((IL1); Figs. 4 and 5, Paragraph [0049]) within the semiconductor substrate (SS), surrounding the NMOS transistor (NT1) and having a top surface (top horizontal surface of (IL1)) higher than the original surface (of (SS));
-a set of contacts (‘silicide layers’ (SL1), (SL2), and (SL3); Figs. 4 and 5, Paragraphs [0046] and [0050]), coupled to the plurality of transistors ((NT1) and (PT1));
-at least one input line (e.g. (EP11); Fig. 3, Paragraphs [0066]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-an output line (e.g. (EP12); Fig. 3, Paragraphs [0069]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-a VDD contacting line ((VDD); Fig. 3, Paragraph [0068]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a VSS contacting line ((GND); Fig. 3, Paragraph [0071]), electrically coupled to the plurality of transistors ((NT1) and (PT1)).
Regarding Claim 2, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the standard cell (SC1) is an inverter cell, a NAND cell, or a NOR cell (e.g. NOR, Paragraph [0182])
Regarding Claim 3, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a metal contacting line ((TP12); Fig. 5, Paragraph [0069]) electrically coupled (via (CL); Paragraph [0070]) to a first contact of the set of contacts (e.g. the left (SL3) of Fig. 5); wherein
-the first contact (left (SL3)) is not fully covered by the metal contacting line (TP12)
Regarding Claim 5, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3, further comprising:
-a highly doped silicon plug ((Ap12) which is p+; Fig. 5, Paragraph [0046]) formed on a portion of the first contact (SL3) which is not covered by the metal contacting line (TP12), wherein
- the highly doped silicon plug (Ap12) contacts (via (SL3) and (CL)) to the metal contacting line (TP12).
Regarding Claim 7, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
- the plurality of transistors ((NT1) and (PT1)) further comprises
-a PMOS transistor (PT1) surrounded by the STI region (IL1),
-the NMOS transistor (NT1) comprises a first conductive region (e.g. the area of (NT1) between source/drain elements (SDR1) and (SDR2)) with a first substantially vertical sidewall (e.g. (SW) on the right side of (NT1); Fig. 4, Paragraph [0050]); and
-the PMOS (PT1) transistor comprises a second conductive region (e.g. the area of (PT1) between source/drain elements (SDR1) and (SDR2)) with a second substantially vertical sidewall (e.g. (SW) on the left side of (PT1); Paragraph [0054]) facing (across the (FE1) region, as seen in Figs. 3 and 5) to the first substantially vertical sidewall of the NMOS transistor (right (SW) of (NT1)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Omura in view of Schultz (U.S. Pub. 2018/0315751), hereinafter Schultz.
Regarding Claim 4, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3 up which it depends, but does not explicitly disclose:
-a width of the metal contacting line (TP12) is the same or substantially the same as that of the first contact (left (SL3)).
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising a metal contacting line (e.g. the right (132); Fig. 13, Paragraph [0031]) and a first contact (e.g. the right (122); Fig. 13, [Paragraph 0028]), wherein:
-a width of the metal contacting line (right (132)) is the same or substantially the same as that of the first contact (right (122)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura such that a width of the metal contacting line is the same or substantially the same as that of the first contact. This would be due to the fact that doing so attains the predictable result of ensuring lower resistance in the metal contacting line (increased volume for carrier flow) whilst additionally simplifying manufacturing by using repeated dimensions.
Regarding Claim 6, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a first conducting line ((GW); Fig. 6, Paragraph [0053]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a second conducting line (the (CL) formed directly vertically above (GW), the rightmost one tagged in Fig. 6; Fig. 6, Paragraph [0058]), electrically coupled to the plurality of transistors ((NT1) and (PT1)), wherein
-the second conducting line (above (CL)) is above the first conducting line (GW); wherein
-at least one of the set of contacts ((SL2); Figs. 4, Paragraph [0053], NOTE while (SL2) is not shown in Fig. 6, Paragraph [0050], it is disclosed to be on the top surface of (GW)) directly connects to the second conducting line (Paragraph [0058]) without going through the first conducting line (GW); and wherein
-an area size of the standard cell (an area of (SC)) is in terms of λ2, where λ is a minimum feature size of the standard cell (A manufactured standard cell must necessarily be made with a minimum feature size (λ), and the area of a standard cell may be arbitrarily represented in terms of λ2, whether multiplied by some constant, or otherwise. Thus, Omura teaches this limitation).
Omura does not explicitly state:
-the first conducting line (GW) is metal.
-the second conducting line (above (CL)) is metal.
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising:
-a first metal line ((124); Fig. 13, Paragraph [0028]) (notably this also functions as a gate as with Omura (GW))
-a second metal line ((130); Fig. 13, Paragraph [0030]) (notably this matches the structure of Omura (above (CL)))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura such that the first conducting line is metal and the second conducting line is metal (i.e. the device of Omura has a first metal line and a second metal line). This would be due to the fact it would have the predictable result of using a conductive material for the lines. Moreover, the specific metal may be selected “based on the design tradeoff between resistance and process dependability” (Schultz, Paragraph [0030]).
Regarding Claim 17, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a first conducting line ((GW); Fig. 6, Paragraph [0053]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a second conducting line (the (CL) formed directly vertically above (GW), the rightmost one tagged in Fig. 6; Fig. 6, Paragraph [0058]), electrically coupled to the plurality of transistors ((NT1) and (PT1)), wherein
-the second conducting line (above (CL)) is above the first conducting line (GW); wherein
-at least one of the set of contacts ((SL2); Figs. 4, Paragraph [0053], NOTE while (SL2) is not shown in Fig. 6, Paragraph [0050], it is disclosed to be on the top surface of (GW)) directly connects to the second conducting line (Paragraph [0058]) without going through the first conducting line (GW).
Omura does not explicitly state:
-the first conducting line (GW) is metal.
-the second conducting line (above (CL)) is metal.
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising:
-a first metal line ((124); Fig. 13, Paragraph [0028]) (notably this also functions as a gate as with Omura (GW))
-a second metal line ((130); Fig. 13, Paragraph [0030]) (notably this matches the structure of Omura (above (CL)))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura such that the first conducting line is metal and the second conducting line is metal (i.e. the device of Omura has a first metal line and a second metal line). This would be due to the fact it would have the predictable result of using a conductive material for the lines. Moreover, the specific metal may be selected “based on the design tradeoff between resistance and process dependability” (Schultz, Paragraph [0030]).
Regarding Claim 18, Omura as modified by Schultz teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 17, wherein:
-the at least one of the set of contacts (Omura, (SL2)) is a gate contact (Omura, Paragraph [0053]).
Claims 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Omura in view of Kim (U.S. Pub. 2014/0312387), hereinafter Kim.
Regarding Claim 8, Omura teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-at least one of the plurality of transistors (NT1) comprises a conductive region (e.g. the area of (NT1) containing a source/drain element ((SDR1) or (SDR2))); wherein
-wherein the conductive region ((SDR1) or (SDR2)) is independent from the semiconductor substrate (SS). (Examiner notes that the definition of “independent” is being taken from the Applicant’s Specification as meaning “not part of the original [silicon substrate]” (Paragraph [00132]) thus anything that differs in characteristics or is understood as independent).
Omura does not explicitly teach:
-at least one of the plurality of transistors comprises a channel layer.
-wherein the channel layer or the conductive region is simultaneously both independent from the semiconductor substrate and comprises a dopant.
(Here the Examiner notes that while Omura teaches a channel (i.e. an area wherein carriers transfer across the transistor), Omura does not show a channel material layer which is structurally distinct)
Kim teaches a transistor with improved reliability ((TR3); Figs. 6-8, Paragraphs [0080] and [0080]), wherein:
-at least one of the plurality of transistors (TR3) comprises a channel layer ((218); Fig. 6, Paragraph [0080]).
-wherein the channel layer (218) or the conductive region (e.g. the area of (TR3) containing (261); Fig. 6, Paragraph [0077]) is simultaneously both independent from the semiconductor substrate ((200); Fig. 6, Paragraph [0078]) and comprises a dopant (sources/drains (261) are formed by ‘injected impurities’ (dopants) into, e.g., Si; Paragraphs [0036] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the device of Omura such that at least one of the plurality of transistors comprises a channel layer, wherein the channel layer or the conductive region is simultaneously both independent from the semiconductor substrate and comprises a dopant. This would be due to the fact that doing so would incorporate reliable transistors (Kim, Paragraph [0090]) with improved carrier mobility (Kim, Paragraph [0005]) into the standard cell layout.
Regarding Claim 10, Omura modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises a top portion covering a top surface of the fin structure (Kim, portion of (218) directly above (F1); Fig. 7) and a side portion covering a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7),
Regarding the limitation “and the top portion and the side portion are not simultaneously formed”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the top and side portions are formed simultaneously or not imposes no structural change to the channel layer. Thus, Omura as modified by Kim teaches all the limitations of Claim 10.
Regarding Claim 11, Omura modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the conductive region (Kim, the area of (TR3) containing (261)) is on a side edge of the semiconductor substrate (Kim, this can be directly seen in Fig. 8, as (261) contacts (F1) on a side edge, wherein (F1) is made of the substrate (200), Specifically, as Kim is incorporated into Omura, this would be understood as being made into the side of (Omura, (SS))).
Regarding the limitation “selectively grown based [on]”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the conductive region is selectively grown, or made differently, does not impact its presence in the device as claimed. Thus, Omura as modified by Kim teaches all the limitations of Claim 11.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Omura and Kim, in view of Doornbos et al. (U.S. Pub. 2020/00998898), hereinafter Doornbos, as supported by Ching et al. (U.S. Pub. 2018/0350969), hereinafter Ching.
Regarding Claim 10, Omura modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises covers a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7).
Omura and Kim do not explicitly teach:
-the channel layer does not cover a top surface of the fin structure.
Doornbos teaches a transistor ((400’); Fig. 14, Paragraph [0045]) that utilizes fins ((FS1); Fig. 14, Paragraph [0022]), wherein:
-the channel layer ((340); Fig. 14, Paragraph [0027]) does not cover a top surface of the fin structure (top of (FS1)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Doornbos into the device of Omura as modified by Kim such that the channel layer does not cover a top surface of the fin structure. This is because it would produce the expected result of allowing greater control in fin processing, controlled (horizontal) carrier flow, and allows for manufacturing flexibility, depending on the desired product. In Doornbos, the lack of a top portion allows further processing of the Fin material directly. See also Ching (218), Figs. 2E-2G.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Omura and Kim, in view of Hamaguchi (U.S. Pub. 2006/0131657), hereinafter Hamaguchi.
Regarding Claim 12, Omura modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 11, further comprising:
-a trench (Kim, (225) Fig. 8, Paragraph [0086]. But incorporated in Omura into the trench where elements (SDR1)/(SDR2) and (SL1) are, as seen in Fig. 4, hereinafter referred to as Omura (trench)) formed under the original surface of the semiconductor substrate (Omura, (SS)); and wherein
-the conductive region (Kim, (261) is disposed in the trench (Omura, (trench))
Neither Omura nor Kim teach:
-an isolation region in the trench
-a bottom surface of the conductive region is isolated from the semiconductor substrate by the isolation region.
Hamaguchi teaches a transistor (within region (43); Fig. 4, Paragraph [0029]) isolated by STI regions ((11); Fig. 4, Paragraph [0029]) featuring trenches (Fig. 4; Paragraph [0030]), comprising:
-an isolation region in the trench ((17), e.g. the left (17); Fig. 4, Paragraph [0030])
-a bottom surface of the conductive region (bottom of source/drain region (27); Fig. 4, Paragraph [0030]) is isolated from the semiconductor substrate ((41) as formed in the substrate (40); Fig. [0029]) by the isolation region (17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hamaguchi into the device of Omura as modified by Kim such that it further comprises an isolation region in the trench and a bottom surface of the conductive region is isolated from the semiconductor substrate by the isolation region. Futhermore, the incorporation would be done such that only one side of the conductive region is contacted to the semiconductor substrate (Hamaguchi, only as a inward-facing sidewall of (27) is contacting the substrate (40), the other side contacts the STI (11), Fig. 4). This would be due to the fact that doing so would reduce junction capacitance and the leak current of the source/drain region (Hamaguchi, Paragraph [0066]).
Regarding Claim 13, Omura modified by Kim and Hamaguchi teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 12, wherein:
-only one side of the conductive region (Modified Omura, (SDR1)/(SDR2)) is contacted to the semiconductor substrate (Omura, (SS)). (As explained above in the incorporation of the Hamaguchi into the device of Omura as modified by Kim. See also Hamaguchi (27) in Fig. 4)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Omura and Kim, in view of Hamaguchi, and in further view of Choi et al. (U.S. Pub. 2016/0233164), hereinafter Choi.
Regarding Claim 14, Omura modified by Kim and Hamaguchi teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 12, wherein:
-a silicide contact layer is present in the trench (Omura, (SL1))
But Omura, Kim, nor Hamaguchi teach:
-a metal region contacting the conductive region, wherein
-the metal region is disposed in the trench
Choi teaches a semiconductor device comprising transistors ((100); Figs. 1B-1C, Paragraph [0036]) including a silicide contact layer ((140); Fig. 1B, Paragraph [0057]) disposed in a trench, further comprising:
-a metal region ((130); Fig. 1B, Paragraph [0059]) contacting the conductive region (‘source/drain regions’ (120); Fig. 1B, Paragraph [0048]), wherein
-the metal region (130) is disposed in the trench (The region defined by the outer bounds of (120)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Choi into the device of Omura as modified by Kim and Hamaguchi such that it further comprises a metal region contacting the conductive region wherein the metal region is disposed in the trench. Futhermore, the incorporation would necessarily result in a bottom surface of the metal region is isolated from the semiconductor substrate by the isolation region, as a consequence of the former incorporation of the teachings of Hamaguchi (Hamaguchi, (17)). This would be due to the fact that doing so would improve (reduce) contact resistance (Choi, Paragraph [0071]).
Conclusion
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/D.M./ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812