Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 14, 2026 has been entered.
Status of Claims
Examiner notes that in the instant application as of the amendment of August 14, 2026:
-Claims 1-12, 14, 15, and 18 are pending.
-Claims 13, 16, and 17 are cancelled.
-Claims 1, 7, 9, 12, 14, 15, and 18 are amended.
Title
Acknowledgement is made of Applicant’s amendment of the title of the invention as to being directed towards the inventive concept as limited by the claim amendments. As stated in the Final Rejection dated May 14, 2026, the objection was at that point withdrawn and this and any future amendments to the title would be based on Applicant’s direction of claim limitations as indicative of the inventive concept.
Claim Rejections under 35 USC § 112(b)
Acknowledgement is made of Applicant’s amendments to Claim 15 as they relate to the 112(b) rejection of the Final Rejection dated May 14, 2026. The 112(b) rejection is withdrawn.
Response to Arguments
Applicant's amendments and arguments filed August 14, 2026, hereinafter Response, have been fully considered but they are not persuasive.
Regarding Applicant’s arguments as they relate to the identification of “a trench formed under the original surface” of the amended claim 1 (Response pg. 12), the Examiner finds that Omura does teach the amended claim in that an identified trench (e.g. consisting of elements (SDR1)/(SDR2) and (ET)) may include a top surface which aligns with an original surface. Furthermore, the method by which a trench is formed (whether via an etching process forming a hole followed by a deposition process, or via multiple implantation steps, or so forth) does not change the structural presence of a trench and cannot be relied upon to disqualify prior art wherein the claims are directed toward a device rather than a specific method of formation.
Regarding Applicant’s statement (Response pg. 13)) that “Of course, Omura does not disclose ‘LDD abutting against an exposed lateral surface of the trench’ as well”, Examiner also disagrees in two initial interpretations. Firstly, “exposed” can be understood in reference solely to other elements within the trench, which is true for element (ET) in Omura. Secondly, “lateral surface of the trench” can be understood in reference to a portion of the totality of the surface, and/or of a portion of the surface defined/above a different element, again true in Omura for the element (ET), wherein the abutting surface defined by (SDR1)/(SDR2) and is exposed (e.g. not under the gate insulating layer (IL4)). Examiner also wishes to note that elements (SDR1)/(SDR2) are identified as the heavily doped semiconductor regions on pg. 20 of the Non-Final, not (SL1)/(SL2) as stated in the response.
Regarding the limitation “abutting against” of Claim 1, Examiner notes that the structural relationship between two elements may be understood such that the first element is positioned “to touch along a border or with a projecting part” (Merriam-Webster; intransitive verb, 1) of a second element. Thus arguments presented using the limitation “abutting against” as under this interpretation are not found to be substantiated.
Regarding further arguments towards Zhu, Okamoto, Schultz, Kim, Doornbos, and Ching, the Examiner finds the arguments are not convincing as due to the reasonings provided above. Furthermore, a recitation of the intended effect/use (Response, pg. 18) of the claimed invention over the prior art must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.
The rejection has been updated to address the newly amended limitations and incorporates a new reference to address the specificity of a metal containing region (though under broad reasonable interpretation, a portion of the silicide contact (SL1) of Omura may be identified as such in this regard if modified by Okamoto as originally presented in the previous Office Actions’ rejection of Claim 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Omura (U.S. Pub. 2011/0272776), hereinafter Omura, in view of Zhu (U.S. Pub. 2019/0139831), hereinafter Zhu, and in view of Hause et al. (U.S. Patent 6,255,704), hereinafter Hause.
Regarding Claim 1, Omura teaches a standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]), comprising:
-a plurality of transistors (NMOS (NT1) and PMOS (PT1); Figs. 3 and 4, Paragraph [0048]) within a semiconductor substrate ((SS); Figs. 3-5, Paragraph [0043]) which includes an original surface (e.g. an exposed surface where the substrate is the thickest, e.g. outer edges in Fig. 2), and a trench (outline of elements (ET) and (SDR1)/(SDR2) within (SS), hereinafter ‘Trench’; Fig. 4) formed under the original surface,
-wherein the plurality of transistors comprises an NMOS transistor (NT1) having a source region, a drain region (comprising (SDR1)/(SDR2) and corresponding (ET), Fig. 4, Paragraph [0050] and [0052]), and a gate structure (comprising (GW), (IL4), (SW), and (SL2); Fig. 4, Paragraph [0050]) between the source region and the drain region;
- a STI region ((IL1); Figs. 4 and 5, Paragraph [0049]) within the semiconductor substrate (SS), surrounding the NMOS transistor (NT1) and having a top surface (top horizontal surface of (IL1));
-a set of contacts (‘silicide layers’ (SL1), (SL2), and (SL3); Figs. 4 and 5, Paragraphs [0046] and [0050]), coupled to the plurality of transistors ((NT1) and (PT1));
-at least one input line (e.g. (EP11); Fig. 3, Paragraphs [0066]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-an output line (e.g. (EP12); Fig. 3, Paragraphs [0069]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-a VDD contacting line ((VDD); Fig. 3, Paragraph [0068]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a VSS contacting line ((GND); Fig. 3, Paragraph [0071]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); wherein
-the source region or the drain region ((SDR1)/(SDR2), corresponding (ET)) is formed in the trench (Trench) and comprises comprises a lightly doped drain (LDD) (Corresponding (ET) to Source or Drain) abutting against an exposed (understood as lack of further elements of the drain or source regions covering it) lateral surface of the trench (e.g. top of (Trench), a heavily doped semiconductor region laterally abutting against a sidewall of the LDD ((SDR1)/ (SDR2) corresponding to Source or Drain)
Omura does not explicitly teach:
-[a STI region] having a top surface higher than a conductive gate layer of the gate structure
Zhu teaches a plurality of transistors (FinFETs on fin structures (F); Fig. 21, Paragraph [0064]) comprising:
-[a STI region] ((T) including (1046) and (1048); Figs. 18 and 19, Paragraph [0086] and [0089]) having a top surface (top of (T)/(1048)) higher than a conductive gate layer of the gate structure ((1040); Fig. 19, Paragraph [0081])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Zhu into the device of Omura such that the STI region has having a top surface higher than a conductive gate layer of the gate structure. This would be due to the fact that doing so would incorporate a STI structure with greater insulating properties (Zhu, Paragraph [0086]).
Omura nor Zhu teaches:
-a metal containing region laterally abutting against a sidewall of the heavily doped semiconductor region
Hause teaches a transistor ((400); Fig. 13, Col. 3, Lines 63-67), comprising:
-a metal containing region ((1380); Fig. 13, Col. 9, Lines 9-27) laterally abutting against a sidewall of the heavily doped semiconductor region ((755); Fig. 13, Col. 6, Lines 36-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hause into the device of Omura and Zhu such that it contains a metal containing region laterally abutting against a sidewall of the heavily doped semiconductor region. This would be due to the fact that doing so would reduce overall resistivity of the transistor and improve operating speed (Hause, Col. 9, Lines 58-67).
For the following claim rejections, all references are directed towards Omura unless otherwise specified. For example (SC1) refers to (Omura, (SC1)), while (Zhu, (1040)) refers to element (1040) of Zhu.
Regarding Claim 2, Omura as modified by Zhu and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the standard cell (SC1) is an inverter cell, a NAND cell, or a NOR cell (e.g. NOR, Paragraph [0182])
Regarding Claim 3, Omura as modified by Zhu and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a metal contacting line ((TP12); Fig. 5, Paragraph [0069]) electrically coupled (via (CL); Paragraph [0070]) to a first contact of the set of contacts (e.g. the left (SL3) of Fig. 5); wherein
-the first contact (left (SL3)) is not fully covered by the metal contacting line (TP12)
Regarding Claim 5, Omura as modified by Zhu and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3, further comprising:
-a highly doped silicon plug ((Ap12) which is p+; Fig. 5, Paragraph [0046]) formed on a portion of the first contact (SL3) which is not covered by the metal contacting line (TP12), wherein
- the highly doped silicon plug (Ap12) contacts (via (SL3) and (CL)) to the metal contacting line (TP12).
Regarding Claim 7, Omura as modified by Zhu and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
- the plurality of transistors ((NT1) and (PT1)) further comprises
-a PMOS transistor (PT1) surrounded by the STI region (IL1),
-the NMOS transistor (NT1) comprises a first conductive region which is the source region or the drain region ((SDR1)/(SDR2), corresponding (ET)) with a first substantially (i.e. the majority of it) vertical sidewall (e.g. sidewall of (SDR1) on the right side; Fig. 4); and
-the PMOS (PT1) transistor comprises a second conductive region (e.g. the area of (PT1) between source/drain elements (SDR1)/(SDR2), corresponding (ET)) with a second substantially vertical sidewall (e.g. (SW) on the left side of (PT1); Paragraph [0054]) facing (across the (FE1) region, as seen in Figs. 3 and 5) to the first substantially vertical sidewall of the NMOS transistor (right sidewall of (SDR1)).
Regarding Claim 15, Omura as modified by Zhu and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the semiconductor substrate (SS) includes a well region ((Wp); Figs. 3-5, Paragraph [0043]); and
-the plurality of transistors ((NT1) and (PT1)) further comprise:
-a first-type transistor (corresponding to the NMOS transistor (NT1)) and a second-type transistor (PMOS (PT1)), wherein the first-type transistor (NT1) is formed within the well region (Wp) and the second-type transistor (PT1) is formed outside the well region ((Wn); Figs. 3 and 5, Paragraph [0043]);
-wherein the first-type transistor includes a first set of fin structures (e.g. (NT1) and (NT2); Fig. 3, Paragraph [0079]) electrically coupled together (via connections to (GND), Figs. 3 and 6, Paragraphs [0071] and [0094]), the second-type transistor includes a second set of fin structures (e.g (PT1) and (PT2); Fig. 3, Paragraph [0079]). electrically coupled together (via connections to (VDD), Figs. 3 and 6, Paragraphs [0068] and [0092]).
Regarding Claim 18, Omura as modified by Zhu and Hause teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the at least one of the set of contacts (Omura, (SL2)) is a gate contact (Omura, Paragraph [0053]).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, and Hause in view of Schultz (U.S. Pub. 2018/0315751), hereinafter Schultz.
Regarding Claim 4, Omura, Zhu, and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3 up which it depends, but does not explicitly disclose:
-a width of the metal contacting line (TP12) is the same or substantially the same as that of the first contact (left (SL3)).
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising a metal contacting line (e.g. the right (132); Fig. 13, Paragraph [0031]) and a first contact (e.g. the right (122); Fig. 13, [Paragraph 0028]), wherein:
-a width of the metal contacting line (right (132)) is the same or substantially the same as that of the first contact (right (122)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura, Zhu, and Hause such that a width of the metal contacting line is the same or substantially the same as that of the first contact. This would be due to the fact that doing so attains the predictable result of ensuring lower resistance in the metal contacting line (increased volume for carrier flow) whilst additionally simplifying manufacturing by using repeated dimensions.
Regarding Claim 6, Omura , Zhu, and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a first conducting line ((GW); Fig. 6, Paragraph [0053]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a second conducting line (the (CL) formed directly vertically above (GW), the rightmost one tagged in Fig. 6; Fig. 6, Paragraph [0058]), electrically coupled to the plurality of transistors ((NT1) and (PT1)), wherein
-the second conducting line (above (CL)) is above the first conducting line (GW); wherein
-at least one of the set of contacts ((SL2); Figs. 4, Paragraph [0053], NOTE while (SL2) is not shown in Fig. 6, Paragraph [0050], it is disclosed to be on the top surface of (GW)) directly connects to the second conducting line (Paragraph [0058]) without going through the first conducting line (GW).
Omura , Zhu, nor Hause explicitly state:
-the first conducting line (GW) is metal.
-the second conducting line (above (CL)) is metal.
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising:
-a first metal line ((124); Fig. 13, Paragraph [0028]) (notably this also functions as a gate as with Omura (GW))
-a second metal line ((130); Fig. 13, Paragraph [0030]) (notably this matches the structure of Omura (above (CL)))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura, Zhu, and Hause such that the first conducting line is metal and the second conducting line is metal (i.e. the device of Omura has a first metal line and a second metal line). This would be due to the fact it would have the predictable result of using a conductive material for the lines. Moreover, the specific metal may be selected “based on the design tradeoff between resistance and process dependability” (Schultz, Paragraph [0030]).
Claims 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, and Hause in view of Kim (U.S. Pub. 2014/0312387), hereinafter Kim.
Regarding Claim 8, Omura, Zhu, and Hause teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-at least one of the plurality of transistors (NT1) comprises a conductive region (e.g. the area of (NT1) containing a source/drain element ((SDR1) or (SDR2))); wherein
-wherein the conductive region ((SDR1) or (SDR2)) is independent from the semiconductor substrate (SS). (Examiner notes that the definition of “independent” is being taken from the Applicant’s Specification as meaning “not part of the original [silicon substrate]” (Paragraph [00132]) thus anything that differs in characteristics or is understood as independent).
Omura, Zhu, nor Hause explicitly teach:
-at least one of the plurality of transistors comprises a channel layer.
-wherein the channel layer is independent from the semiconductor substrate.
(Here the Examiner notes that while Omura teaches a channel (i.e. an area wherein carriers transfer across the transistor), Omura does not show a channel material layer which is structurally distinct)
Kim teaches a transistor with improved reliability ((TR3); Figs. 6-8, Paragraphs [0080] and [0080]), wherein:
-at least one of the plurality of transistors (TR3) comprises a channel layer ((218); Fig. 6, Paragraph [0080]).
-wherein the channel layer (218) is independent from the semiconductor substrate ((200); Fig. 6, Paragraph [0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the device of Omura, Zhu, and Hause such that at least one of the plurality of transistors comprises a channel layer, wherein the channel layer is independent from the semiconductor substrate. This would be due to the fact that doing so would incorporate reliable transistors (Kim, Paragraph [0090]) with improved carrier mobility (Kim, Paragraph [0005]) into the standard cell layout.
Regarding Claim 10, Omura, Zhu, and Hause modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises a top portion covering a top surface of the fin structure (Kim, portion of (218) directly above (F1); Fig. 7) and a side portion covering a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7),
Regarding the limitation “and the top portion and the side portion are not simultaneously formed”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the top and side portions are formed simultaneously or not imposes no structural change to the channel layer. Thus, Omura, Zhu, and Hause as modified by Kim teaches all the limitations of Claim 10.
Regarding Claim 11, Omura, Zhu, and Hause modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the conductive region (Kim, the area of (TR3) containing (261)) is on a side edge of the semiconductor substrate (Kim, this can be directly seen in Fig. 8, as (261) contacts (F1) on a side edge, wherein (F1) is made of the substrate (200), Specifically, as Kim is incorporated into Omura, this would be understood as being made into the side of (Omura, (SS))).
Regarding the limitation “selectively grown based [on]”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the conductive region is selectively grown, or made differently, does not impact its presence in the device as claimed. Thus, Omura, Zhu, and Hause as modified by Kim teaches all the limitations of Claim 11.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, Hause, and Kim, in view of Doornbos et al. (U.S. Pub. 2020/00998898), hereinafter Doornbos, as supported by Ching et al. (U.S. Pub. 2018/0350969), hereinafter Ching.
Regarding Claim 9, Omura, Zhu, and Hause as modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises covers a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7).
Omura, Zhu, Hause, nor Kim explicitly teach:
-the channel layer does not cover a top surface of the fin structure.
Doornbos teaches a transistor ((400’); Fig. 14, Paragraph [0045]) that utilizes fins ((FS1); Fig. 14, Paragraph [0022]), wherein:
-the channel layer ((340); Fig. 14, Paragraph [0027]) does not cover a top surface of the fin structure (top of (FS1)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Doornbos into the device of Omura, Zhu, and Hause as modified by Kim such that the channel layer does not cover a top surface of the fin structure. This is because it would produce the expected result of allowing greater control in fin processing, controlled (horizontal) carrier flow, and allows for manufacturing flexibility, depending on the desired product. In Doornbos, the lack of a top portion allows further processing of the Fin material directly. See also Ching (218), Figs. 2E-2G.
Claim is 12 rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, and Hause, in view of Hamaguchi (U.S. Pub. 2006/0131657), hereinafter Hamaguchi.
Regarding Claim 12, Omura, Zhu, and Hause teach the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, but do not further teach:
-an isolation region in the trench
-a bottom surface of the source region of the drain region is isolated from the semiconductor substrate by the isolation region.
Hamaguchi teaches a transistor (within region (43); Fig. 4, Paragraph [0029]) isolated by STI regions ((11); Fig. 4, Paragraph [0029]) featuring trenches (Fig. 4; Paragraph [0030]), comprising:
-an isolation region in the trench ((17), e.g. the left (17); Fig. 4, Paragraph [0030])
-a bottom surface of the source region or the drain region (bottom of source/drain region (27); Fig. 4, Paragraph [0030]) is isolated from the semiconductor substrate ((41) as formed in the substrate (40); Fig. [0029]) by the isolation region (17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hamaguchi into the device of Omura, Zhu, and Hause such that it further comprises an isolation region in the trench and a bottom surface of the conductive region is isolated from the semiconductor substrate by the isolation region. This would be due to the fact that doing so would reduce junction capacitance and the leak current of the source/drain region (Hamaguchi, Paragraph [0066]).
Regarding Claim 14, Omura, Zhu, and Hause as modified by Hamaguchi teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 12, further comprising:
-a bottom surface of the metal containing region (Hause, (1380) as incorporated into (SDR1)/(SDR2)) is isolated (both physically and electrically) from the semiconductor substrate (SS) by the isolation region (Hamaguchi, (17) as incorporated around (SDR1)/(SDR2)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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