Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-18 are pending.
-Claims 1, 6, 8, 15-18 are amended.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 2, 2026 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings, corresponding to Fig. 10(d), as submitted in response to the objection to the drawings of the Non-Final Office Action dated January 8, 2026, hereinafter the “Non-Final”, were received on April 8, 2026. These drawings are acceptable and the objection to the drawings is hereby withdrawn.
Claim Objections
Acknowledgement is made of Applicant’s amendments as they relate to claim objection over informalities in the Non-Final. The objections over informalities of the Non-Final are hereby withdrawn.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn. Examiner notes, however, that Applicant may update the title with any future amendments based on additional claim limitations.
Response to Arguments
Applicant’s amendments and arguments filed April 8, 2026 have been fully considered and are persuasive, the rejection has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation "the second-type transistor". There is insufficient antecedent basis for this limitation in the claim.
It is the Examiner’s understanding that the previously established “a second transistor” of the claim is meant to be directed towards “a second-type transistor”.
For the sake of examination, Examiner will read the second limitation grouping of Claim 15 as follows:
--the plurality of transistors further comprise a first-type transistor and a second-type transistor, wherein the first-type transistor is formed within the well region and the second-type transistor is formed outside the well region;--
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Omura (U.S. Pub. 2011/0272776), hereinafter Omura, in view of Zhu (U.S. Pub. 2019/0139831), hereinafter Zhu.
Regarding Claim 1, Omura teaches a standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]), comprising:
-a plurality of transistors (NMOS (NT1) and PMOS (PT1); Figs. 3 and 4, Paragraph [0048]) within a semiconductor substrate ((SS); Figs. 3-5, Paragraph [0043]) which includes an original surface (e.g. an exposed surface where the substrate is the thickest, e.g. outer edges in Fig. 2), wherein the plurality of transistors comprises an NMOS transistor (NT1) having a source region, a drain region (comprising (SDR1)/(SDR2) and corresponding (ET), Fig. 4, Paragraph [0050] and [0052]), and a gate structure (comprising (GW), (IL4), (SW), and (SL2); Fig. 4, Paragraph [0050]) between the source region and the drain region;
- a STI region ((IL1); Figs. 4 and 5, Paragraph [0049]) within the semiconductor substrate (SS), surrounding the NMOS transistor (NT1) and having a top surface (top horizontal surface of (IL1));
-a set of contacts (‘silicide layers’ (SL1), (SL2), and (SL3); Figs. 4 and 5, Paragraphs [0046] and [0050]), coupled to the plurality of transistors ((NT1) and (PT1));
-at least one input line (e.g. (EP11); Fig. 3, Paragraphs [0066]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-an output line (e.g. (EP12); Fig. 3, Paragraphs [0069]), electrically coupled to the plurality of transistors ((NT1) and (PT1));
-a VDD contacting line ((VDD); Fig. 3, Paragraph [0068]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a VSS contacting line ((GND); Fig. 3, Paragraph [0071]), electrically coupled to the plurality of transistors ((NT1) and (PT1)).
Omura does not explicitly teach:
-[a STI region] having a top surface higher than a conductive gate layer of the gate structure
Zhu teaches a plurality of transistors (FinFETs on fin structures (F); Fig. 21, Paragraph [0064]) comprising:
-[a STI region] ((T) including (1046) and (1048); Figs. 18 and 19, Paragraph [0086] and [0089]) having a top surface (top of (T)/(1048)) higher than a conductive gate layer of the gate structure ((1040); Fig. 19, Paragraph [0081])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Zhu into the device of Omura such that the STI region has having a top surface higher than a conductive gate layer of the gate structure. This would be due to the fact that doing so would incorporate a STI structure with greater insulating properties (Zhu, Paragraph [0086]).
For the following claim rejections, all references are directed towards Omura unless otherwise specified. For example (SC1) refers to (Omura, (SC1)), while (Zhu, (1040)) refers to element (1040) of Zhu.
Regarding Claim 2, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the standard cell (SC1) is an inverter cell, a NAND cell, or a NOR cell (e.g. NOR, Paragraph [0182])
Regarding Claim 3, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a metal contacting line ((TP12); Fig. 5, Paragraph [0069]) electrically coupled (via (CL); Paragraph [0070]) to a first contact of the set of contacts (e.g. the left (SL3) of Fig. 5); wherein
-the first contact (left (SL3)) is not fully covered by the metal contacting line (TP12)
Regarding Claim 5, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3, further comprising:
-a highly doped silicon plug ((Ap12) which is p+; Fig. 5, Paragraph [0046]) formed on a portion of the first contact (SL3) which is not covered by the metal contacting line (TP12), wherein
- the highly doped silicon plug (Ap12) contacts (via (SL3) and (CL)) to the metal contacting line (TP12).
Regarding Claim 7, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
- the plurality of transistors ((NT1) and (PT1)) further comprises
-a PMOS transistor (PT1) surrounded by the STI region (IL1),
-the NMOS transistor (NT1) comprises a first conductive region (e.g. the area of (NT1) between source/drain elements (SDR1)/(SDR2), corresponding (ET)) with a first substantially vertical sidewall (e.g. (SW) on the right side of (NT1); Fig. 4, Paragraph [0050]); and
-the PMOS (PT1) transistor comprises a second conductive region (e.g. the area of (PT1) between source/drain elements (SDR1)/(SDR2), corresponding (ET)) with a second substantially vertical sidewall (e.g. (SW) on the left side of (PT1); Paragraph [0054]) facing (across the (FE1) region, as seen in Figs. 3 and 5) to the first substantially vertical sidewall of the NMOS transistor (right (SW) of (NT1)).
Regarding Claim 15, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the semiconductor substrate (SS) includes a well region ((Wp); Figs. 3-5, Paragraph [0043]); and
-the plurality of transistors ((NT1) and (PT1)) further comprise:
-a first-type transistor (corresponding to the NMOS transistor (NT1)) and a second-type transistor (PMOS (PT1)), wherein the first-type transistor (NT1) is formed within the well region (Wp) and the second-type transistor (PT1) is formed outside the well region ((Wn); Figs. 3 and 5, Paragraph [0043]);
-wherein the first-type transistor includes a first set of fin structures (e.g. (NT1) and (NT2); Fig. 3, Paragraph [0079]) electrically coupled together (via connections to (GND), Figs. 3 and 6, Paragraphs [0071] and [0094]), the second-type transistor includes a second set of fin structures (e.g (PT1) and (PT2); Fig. 3, Paragraph [0079]). electrically coupled together (via connections to (VDD), Figs. 3 and 6, Paragraphs [0068] and [0092]).
Claims 4, 6, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Omura and Zhu in view of Schultz (U.S. Pub. 2018/0315751), hereinafter Schultz.
Regarding Claim 4, Omura and Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 3 up which it depends, but does not explicitly disclose:
-a width of the metal contacting line (TP12) is the same or substantially the same as that of the first contact (left (SL3)).
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising a metal contacting line (e.g. the right (132); Fig. 13, Paragraph [0031]) and a first contact (e.g. the right (122); Fig. 13, [Paragraph 0028]), wherein:
-a width of the metal contacting line (right (132)) is the same or substantially the same as that of the first contact (right (122)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura and Zhu such that a width of the metal contacting line is the same or substantially the same as that of the first contact. This would be due to the fact that doing so attains the predictable result of ensuring lower resistance in the metal contacting line (increased volume for carrier flow) whilst additionally simplifying manufacturing by using repeated dimensions.
Regarding Claim 6, Omura and Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a first conducting line ((GW); Fig. 6, Paragraph [0053]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a second conducting line (the (CL) formed directly vertically above (GW), the rightmost one tagged in Fig. 6; Fig. 6, Paragraph [0058]), electrically coupled to the plurality of transistors ((NT1) and (PT1)), wherein
-the second conducting line (above (CL)) is above the first conducting line (GW); wherein
-at least one of the set of contacts ((SL2); Figs. 4, Paragraph [0053], NOTE while (SL2) is not shown in Fig. 6, Paragraph [0050], it is disclosed to be on the top surface of (GW)) directly connects to the second conducting line (Paragraph [0058]) without going through the first conducting line (GW).
Omura nor Zhu explicitly state:
-the first conducting line (GW) is metal.
-the second conducting line (above (CL)) is metal.
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising:
-a first metal line ((124); Fig. 13, Paragraph [0028]) (notably this also functions as a gate as with Omura (GW))
-a second metal line ((130); Fig. 13, Paragraph [0030]) (notably this matches the structure of Omura (above (CL)))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura and Zhu such that the first conducting line is metal and the second conducting line is metal (i.e. the device of Omura has a first metal line and a second metal line). This would be due to the fact it would have the predictable result of using a conductive material for the lines. Moreover, the specific metal may be selected “based on the design tradeoff between resistance and process dependability” (Schultz, Paragraph [0030]).
Regarding Claim 17, Omura and Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, further comprising:
-a first conducting line ((GW); Fig. 6, Paragraph [0053]), electrically coupled to the plurality of transistors ((NT1) and (PT1)); and
-a second conducting line (the (CL) formed directly vertically above (GW), the rightmost one tagged in Fig. 6; Fig. 6, Paragraph [0058]), electrically coupled to the plurality of transistors ((NT1) and (PT1)), wherein
-the second conducting line (above (CL)) is above the first conducting line (GW); wherein
-at least one of the set of contacts ((SL2); Figs. 4, Paragraph [0053], NOTE while (SL2) is not shown in Fig. 6, Paragraph [0050], it is disclosed to be on the top surface of (GW)) directly connects to the second conducting line (Paragraph [0058]) without going through the first conducting line (GW).
Omura nor Zhu explicitly state:
-the first conducting line (GW) is metal.
-the second conducting line (above (CL)) is metal.
Schultz teaches a standard cell ((1300); Fig. 13, Paragraph [0046]), comprising:
-a first metal line ((124); Fig. 13, Paragraph [0028]) (notably this also functions as a gate as with Omura (GW))
-a second metal line ((130); Fig. 13, Paragraph [0030]) (notably this matches the structure of Omura (above (CL)))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Schultz into the device of Omura and Zhu such that the first conducting line is metal and the second conducting line is metal (i.e. the device of Omura has a first metal line and a second metal line). This would be due to the fact it would have the predictable result of using a conductive material for the lines. Moreover, the specific metal may be selected “based on the design tradeoff between resistance and process dependability” (Schultz, Paragraph [0030]).
Regarding Claim 18, Omura and Zhu as modified by Schultz teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 17, wherein:
-the at least one of the set of contacts (Omura, (SL2)) is a gate contact (Omura, Paragraph [0053]).
Claims 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Omura and Zhu in view of Kim (U.S. Pub. 2014/0312387), hereinafter Kim.
Regarding Claim 8, Omura and Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-at least one of the plurality of transistors (NT1) comprises a conductive region (e.g. the area of (NT1) containing a source/drain element ((SDR1) or (SDR2))); wherein
-wherein the conductive region ((SDR1) or (SDR2)) is independent from the semiconductor substrate (SS). (Examiner notes that the definition of “independent” is being taken from the Applicant’s Specification as meaning “not part of the original [silicon substrate]” (Paragraph [00132]) thus anything that differs in characteristics or is understood as independent).
Omura nor Zhu explicitly teach:
-at least one of the plurality of transistors comprises a channel layer.
-wherein the channel layer is independent from the semiconductor substrate.
(Here the Examiner notes that while Omura teaches a channel (i.e. an area wherein carriers transfer across the transistor), Omura does not show a channel material layer which is structurally distinct)
Kim teaches a transistor with improved reliability ((TR3); Figs. 6-8, Paragraphs [0080] and [0080]), wherein:
-at least one of the plurality of transistors (TR3) comprises a channel layer ((218); Fig. 6, Paragraph [0080]).
-wherein the channel layer (218) is independent from the semiconductor substrate ((200); Fig. 6, Paragraph [0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the device of Omura and Zhu such that at least one of the plurality of transistors comprises a channel layer, wherein the channel layer is independent from the semiconductor substrate. This would be due to the fact that doing so would incorporate reliable transistors (Kim, Paragraph [0090]) with improved carrier mobility (Kim, Paragraph [0005]) into the standard cell layout.
Regarding Claim 10, Omura and Zhu modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises a top portion covering a top surface of the fin structure (Kim, portion of (218) directly above (F1); Fig. 7) and a side portion covering a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7),
Regarding the limitation “and the top portion and the side portion are not simultaneously formed”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the top and side portions are formed simultaneously or not imposes no structural change to the channel layer. Thus, Omura and Zhu as modified by Kim teaches all the limitations of Claim 10.
Regarding Claim 11, Omura and Zhu modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the conductive region (Kim, the area of (TR3) containing (261)) is on a side edge of the semiconductor substrate (Kim, this can be directly seen in Fig. 8, as (261) contacts (F1) on a side edge, wherein (F1) is made of the substrate (200), Specifically, as Kim is incorporated into Omura, this would be understood as being made into the side of (Omura, (SS))).
Regarding the limitation “selectively grown based [on]”: Patentable weight is given to a claim limitation directed towards a method of manufacturing in a device claim to the extent it directly impacts the resultant structure in a distinct way. In the instant case, whether the conductive region is selectively grown, or made differently, does not impact its presence in the device as claimed. Thus, Omura as modified by Kim teaches all the limitations of Claim 11.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, and Kim, in view of Doornbos et al. (U.S. Pub. 2020/00998898), hereinafter Doornbos, as supported by Ching et al. (U.S. Pub. 2018/0350969), hereinafter Ching.
Regarding Claim 9, Omura modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 8, wherein:
-the at least one transistor (Kim, (TR3)) comprises a fin structure (Kim, (F1); Fig. 6, Paragraph [0078]), the channel layer (Kim, (218)) comprises covers a first sidewall (Kim, portion of (218) to the right of (F1); Fig. 7) and a second sidewall of the fin structure (Kim, portion of (218) to the left of (F1); Fig. 7).
Omura, Zhu, and Kim do not explicitly teach:
-the channel layer does not cover a top surface of the fin structure.
Doornbos teaches a transistor ((400’); Fig. 14, Paragraph [0045]) that utilizes fins ((FS1); Fig. 14, Paragraph [0022]), wherein:
-the channel layer ((340); Fig. 14, Paragraph [0027]) does not cover a top surface of the fin structure (top of (FS1)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Doornbos into the device of Omura and Zhu as modified by Kim such that the channel layer does not cover a top surface of the fin structure. This is because it would produce the expected result of allowing greater control in fin processing, controlled (horizontal) carrier flow, and allows for manufacturing flexibility, depending on the desired product. In Doornbos, the lack of a top portion allows further processing of the Fin material directly. See also Ching (218), Figs. 2E-2G.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Omura, Zhu, and Kim, in view of Hamaguchi (U.S. Pub. 2006/0131657), hereinafter Hamaguchi.
Regarding Claim 12, Omura and Zhu modified by Kim teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 11, further comprising:
-a trench (Kim, (225) Fig. 8, Paragraph [0086]. But incorporated in Omura into the trench where elements (SDR1)/(SDR2) and (SL1) are, as seen in Fig. 4, hereinafter referred to as Omura (trench)) formed under the original surface of the semiconductor substrate (Omura, (SS)); and wherein
-the conductive region (Kim, (261) is disposed in the trench (Omura, (trench))
Omura, Zhu, and Kim do not teach:
-an isolation region in the trench
-a bottom surface of the conductive region is isolated from the semiconductor substrate by the isolation region.
Hamaguchi teaches a transistor (within region (43); Fig. 4, Paragraph [0029]) isolated by STI regions ((11); Fig. 4, Paragraph [0029]) featuring trenches (Fig. 4; Paragraph [0030]), comprising:
-an isolation region in the trench ((17), e.g. the left (17); Fig. 4, Paragraph [0030])
-a bottom surface of the conductive region (bottom of source/drain region (27); Fig. 4, Paragraph [0030]) is isolated from the semiconductor substrate ((41) as formed in the substrate (40); Fig. [0029]) by the isolation region (17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hamaguchi into the device of Omura and Zhu as modified by Kim such that it further comprises an isolation region in the trench and a bottom surface of the conductive region is isolated from the semiconductor substrate by the isolation region. Futhermore, the incorporation would be done such that only one side of the conductive region is contacted to the semiconductor substrate (Hamaguchi, only as a inward-facing sidewall of (27) is contacting the substrate (40), the other side contacts the STI (11), Fig. 4). This would be due to the fact that doing so would reduce junction capacitance and the leak current of the source/drain region (Hamaguchi, Paragraph [0066]).
Regarding Claim 13, Omura and Zhu modified by Kim and Hamaguchi teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 12, wherein:
-only one side of the conductive region (Modified Omura, (SDR1)/(SDR2)) is contacted to the semiconductor substrate (Omura, (SS)). (As explained above in the incorporation of the Hamaguchi into the device of Omura as modified by Kim. See also Hamaguchi (27) in Fig. 4)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Omura and Kim, in view of Hamaguchi, and in further view of Choi et al. (U.S. Pub. 2016/0233164), hereinafter Choi.
Regarding Claim 14, Omura and Zhu modified by Kim and Hamaguchi teaches the standard cell (Omura, e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 12, wherein:
-a silicide contact layer is present in the trench (Omura, (SL1))
But Omura, Kim, Zhu, and Hamaguchi do not teach:
-a metal region contacting the conductive region, wherein
-the metal region is disposed in the trench
Choi teaches a semiconductor device comprising transistors ((100); Figs. 1B-1C, Paragraph [0036]) including a silicide contact layer ((140); Fig. 1B, Paragraph [0057]) disposed in a trench, further comprising:
-a metal region ((130); Fig. 1B, Paragraph [0059]) contacting the conductive region (‘source/drain regions’ (120); Fig. 1B, Paragraph [0048]), wherein
-the metal region (130) is disposed in the trench (The region defined by the outer bounds of (120)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Choi into the device of Omura and Zhu as modified by Kim and Hamaguchi such that it further comprises a metal region contacting the conductive region wherein the metal region is disposed in the trench. Futhermore, the incorporation would necessarily result in a bottom surface of the metal region is isolated from the semiconductor substrate by the isolation region, as a consequence of the former incorporation of the teachings of Hamaguchi (Hamaguchi, (17)). This would be due to the fact that doing so would improve (reduce) contact resistance (Choi, Paragraph [0071]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Omura and Zhu in view of Okamoto (U.S. Pub. 2009/0050965), hereinafter Okamoto.
Regarding Claim 16, Omura as modified by Zhu teaches the standard cell (e.g. (SC1), Figs. 2-6, Paragraph [0041]) according to Claim 1, wherein:
-the source region or the drain region ((SDR1)/(SDR2), corresponding (ET)) comprises a lightly doped drain (LDD) (Corresponding (ET) to Source or Drain), a heavily doped semiconductor region laterally abutting against a sidewall of the LDD ((SDR1)/ (SDR2) corresponding to Source or Drain)
Omura nor Zhu teaches:
-a metal containing region laterally abutting against a sidewall of the heavily doped semiconductor region
Okamoto teaches a finFET ((1); Fig. 1, Paragraph [0020]), comprising:
-a metal containing region ((9b); Fig. 1, Paragraph [0038]) laterally abutting against a sidewall of the heavily doped semiconductor region ((6); Fig. 1, Paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Okamoto into the device of Omura and Zhu such that it contains a metal containing region laterally abutting against a sidewall of the heavily doped semiconductor region. This would be due to the fact that doing so would produce the expected result of incorporating an applicable geometry of a silicide contact layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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