DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
Amendments to the Specification paragraph [0033] in the Applicant’s Arguments of 02/10/2026 overcome the drawing objection made in the Non-Final office action mailed on 08/14/1025 therefore that objection is withdrawn.
Specification
Amendments to the Specification paragraph [0033] in the Applicant’s Arguments of 02/10/2026 overcome the specification objection made in the Non-Final office action mailed on 08/14/1025 therefore that objection is withdrawn.
Claim Objections
Claim 27 is objected to because of the following informalities: Examiner notes that a typo “(Fig. 5)” exists at the end of the claim language. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Haba (US 2022/0122934 A1, hereinafter Haba ‘934) in view of Molla et al. (US 10,741,446 B2, hereinafter Molla ‘446) and in further view of Nasu et al. (US 2007/0262468 A1, hereinafter Nasu ‘468) in view of the following arguments.
With respect to Claim 1 Haba ‘934 discloses a method, comprising:
attaching a first semiconductor die (2, Fig 2, Para [0037]) on a top surface (top of 3) of a carrier wafer (3, Fig 2, Para [0037]),
depositing a glue layer (7, Fig 11, Para [0059]), wherein a sidewall portion (side of 7 touching sidewalls 8) of the glue layer (7) is formed on the sidewall (8, Fig 11, Para [0059]) of the first semiconductor die (2), a bottom portion (bottom of 7, Fig 11, Para [0059]) of the glue layer (7) is formed on the top surface (top of 3, Fig 11) of the carrier wafer (3) (Fig 11 and Para [0059] discloses bottom of 7 formed on carrier wafer 3), the sidewall portion (side of 7 touching sidewalls 8) and the bottom portion (bottom of 7) form a second angle (angle 2), and the second angle (angle 2) is greater than the first angle; and
depositing a dielectric filling material (40, Fig 11, Para [0059]) on the glue layer (7) (Fig 11 and Para [0059] discloses dielectric fill on glue layer) wherein the glue layer (7) is a nitrogen containing layer (Para [0034] discloses 7 as silicon nitride).
But Haba ‘934 fails to explicitly disclose wherein a sidewall of the first semiconductor die is sloped, and a first angle is formed between the sidewall of the first semiconductor die and the top surface of the carrier wafer; and the sidewall portion and the bottom portion form a second angle.
Nevertheless, in a related endeavor (Fig 4 of Molla ‘446), Molla ‘446 teaches wherein a sidewall (478, Fig 4 of Molla ‘446, view 440, Col 6, Line 53) of the first semiconductor die (442, Fig 4 of Molla ‘446, view 440, Col 6, Line 54) is sloped (disclosed in Fig 4 of Molla ‘446, view 440), and a first angle (angle 1 as shown in annotated Fig 3/4 of Molla ‘446, Col 6, Lines 52-54) is formed between the sidewall (478, Fig 4 of Molla ‘446, view 440, Col 6, Line 53) of the first semiconductor die (442, Fig 4 of Molla ‘446, view 440, Col 6, Line 54) and the top surface (top of 432, Fig 4 of Molla ‘446) of the carrier wafer (432, Fig 4 of Molla ‘446 view 440, Col 6, Line 3); and the sidewall portion (side of 442 as shown in annotated Fig 3 of Molla ‘446)) and the bottom portion (top of 432 as shown in annotated Fig 3/4 of Molla ‘446) form a second angle (angle 2 as shown in annotated Fig 4 of Molla ‘446), and the second angle (angle 2) is greater than the first angle (angle 1)(Fig. 4 of Molla ‘446 view 440 discloses angle 2 greater than angle 1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Molla ‘446’s wherein a sidewall of the first semiconductor die is sloped, and a first angle is formed between the sidewall of the first semiconductor die and the top surface of the carrier wafer; and the sidewall portion and the bottom portion form a second angle, Haba ‘934’s device. Molla ‘446 teaches angles that can be formed in die singulation as the first and second angle of the instant application discloses. The ordinary artisan would have been motivated to modify Haba ‘934 in the manner set forth above, at least, because, as Molla ‘446 teaches in Col 6, Lines 9-11, that varying the parameters in singulation of the die provides control over the portion of the outer layer deposited on the die.
As incorporated, the first and second angles of Molla ‘446 would be used on the first and second angles of Haba ‘934.
In a further embodiment of Molla ‘446 (Fig 3, view 350 of Molla ‘446), Molla ‘446 teaches and the second angle is greater than the first angle. (Fig 3, view 350 of Molla ‘446 discloses how a layer deposited over die 342 would form a filet at the connection of the die to the wafer carrier, therefore this filet would fill the gap of the sloped die and increase angle 2 (towards a 90° angle so angle 2 would be greater than angle 1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teaching of Molla ‘446 of the second angle is greater than the first angle into Haba ‘934 as modified by Molla ‘446’s device. Molla ‘446 teaches a layer deposited over die 342 would form a filet at the connection of the die to the wafer carrier. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Molla ‘446 in the manner set forth above, at least, because, the fileted connection between the die and the carrier, as comprises angle 2, would provide additional mechanical strength to the die, thereby increasing device reliability.
As incorporated, the second angles being larger than the first angle of Molla ‘446 would be used in the method of Haba ‘934 as modified by Molla ‘446.
Haba ‘934 as modified by Molla ‘446 fails to explicitly disclose and the dielectric filling material comprises a porous dielectric material.
Nevertheless, in a related endeavor (Fig 1A-3C of Nasu ‘468), Nasu ‘468 teaches and the dielectric filling material (12b, Fig 1B of Nasu ‘468, Para [0026]) comprises a porous dielectric material (Para [0029] of Nasu ‘468 discloses the layer 12 containing a porous dielectric material).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Nasu ‘468’s teaching of and the dielectric filling material comprises a porous dielectric material into Haba ‘934 as modified by Molla ‘446’s method. Haba ‘934 as modified by Molla ‘446 discloses a method and structure for forming an integrated device package for direct bonding, specifically teaching dielectric materials between the devices. Haba ‘934 as modified by Molla ‘446 is open to the material of the dielectric filling material (40 of Haba ‘934) as Para [0059] discloses the “…protective material 40 can comprise any suitable material, including organic or inorganic materials”. Nasu ‘468 teaches a method and structure for forming dielectric structures around semiconductor devices for direct bonding. The ordinary artisan would have been motivated to look at Nasu ‘468 to modify Haba ‘934 as modified by Molla ‘446 for details on the dielectric filling material in the manner set forth above, at least, because, as Nasu ‘468 teaches in Para [0038] the use of the porous low k dielectric lowers resistance which allows the device to be sped up.
As incorporated, the teaching of using a dielectric filling material comprising a porous dielectric (12b) of Nasu ‘468 would be used as the material in the dielectric filling material (40) of Haba ‘934 as modified by Molla ‘446.
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With respect to Claim 8 Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 discloses all limitations of the method of claim 1, and Haba ‘934 discloses further comprising attaching (disclosed in Fig 3A-3C and Para [0038]) a second semiconductor die (additional die 2, Fig 3A and Para [0038] discloses a plurality of die 2) to the carrier wafer (3), wherein a gap (G, Fig 3A, Para [0038]) is formed between the first semiconductor die and the second semiconductor die (Fig 3A discloses a gap G between first and second die 2).
With respect to Claim 9 Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 discloses all limitations of the method of claim 8, and in a further embodiment (Fig 3C of Haba ‘934), Haba ‘934 further discloses wherein the first semiconductor die (2) is a device die (Para [0038] discloses 2 as integrated device die) and the second semiconductor die (2’, Fig 3C, Para [0038]) is a dummy die (Para [0038] discloses 2’ as a dummy die).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teaching of the further embodiment of Haba ‘934’s dummy die along a device die into Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468’s device. The ordinary artisan would have been motivated to further modify Haba ‘934 as modified by Molla ‘446 and further by Nasu ‘468 in the manner set forth above, at least, because, as Haba ‘934 teaches in Para [0038], placing dummy dies between the active die “can beneficially reduce the amount of protective material 7 used to fill the gaps G in subsequent steps and can enable conformal filling of the gaps G”, which can reduce the cost of the protective material per device and provide better protection through the conformal layer.
As incorporated, the dummy die (2’) of the further embodiment of Haba ‘934 would be placed by the device die (2) on the carrier wafer (3) of Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468.
Claims 2-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Molla ‘446 in view of Nasu ‘468 in further view of Uzoh et al. (US 2017/0338214 A1, hereinafter Uzoh ‘214) in view of the following arguments.
With respect to Claim 2 Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 disclose all limitations of the method of claim 1, but Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 fails to explicitly disclose wherein depositing the glue layer comprises:
depositing a thicker layer on a lower portion of the sidewall of the first semiconductor die near the carrier wafer and a thinner layer on an upper portion of the sidewall.
Nevertheless, in a related endeavor (Fig 2A-2F of Uzoh ‘214), Uzoh ‘214 teaches wherein depositing the glue layer (12, Fig 2C of Uzoh ‘214, Para [0033]) comprises: depositing a thicker layer on a lower portion of the sidewall (lower side of 3b as shown in Fig 2C of Uzoh ‘214) of the first semiconductor die (3b, Fig 2C of Uzoh ‘214, Para [0041]) near the carrier wafer (2, Fig 2C of Uzoh ‘214, Para [0041]) and a thinner layer on an upper portion of the sidewall (upper side of 3b as shown in Fig 2C of Uzoh ‘214) (Fig 2C of Uzoh ‘214 discloses that the section of 12 on the lower side of the die 3b and the upper surface of substate 2 is thicker than the upper side of die 3b as the layer 17 covers the upper sides of the die but it does not extend down to the lower portion of 3b and layer 12).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Uzoh ‘214’s depositing a thicker layer on a lower portion of the sidewall of the first semiconductor die near the carrier wafer and a thinner layer on an upper portion of the sidewall into Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 in the manner set forth above, at least, because, the thicker layer of glue at the surface of the carrier would provide additional protection to the connection layer of the die from mechanical damage.
As incorporated, the thicker layer of glue at the bottom of the device die as taught by Uzoh ‘214 would be used in the glue layer (7) of Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468 over the carrier wafer (3) of Haba ‘934 as modified by Molla ‘446 and further modified by Nasu ‘468.
With respect to Claim 3 Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 discloses all limitations of the method of claim 2, and Haba ‘934 further discloses wherein the glue layer (7) comprises one of silicon nitride and silicon carbon nitride (Para [0034] discloses 7 as silicon nitride).
With respect to Claim 5 Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 discloses all limitations of the method of claim 2, and Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 further discloses wherein depositing the dielectric filling material (40 as modified above) comprises:
forming a silicon oxide (Para [0040] of Haba ‘934 discloses 40 as a silicon oxide) using a precursor containing one of tetraethoxysilane (TEOS) and methyldiethoxysilane (mDEOS) (Para [0026] of Nasu ‘468 teaches the silicon oxide filling dielectric, incorporated above, is formed from TEOS).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Molla ‘446 in view of Nasu ‘934 in view of Uzoh ‘214 and in further view of Kiichiro et al. (GB 2027273A, hereinafter Kiichiro ‘273) in view of the following arguments.
With respect to Claim 4 Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 discloses all limitations of the method of claim 3, but Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 fails to explicitly disclose wherein depositing the glue layer is performed at a temperature range between a temperature between about 270°C and 280°C.
Nevertheless, in a related endeavor (Kiichiro ‘273), Kiichiro ‘273 teaches wherein depositing the glue layer (silicon nitride, Page 1, Line 59-60 of Kiichiro ‘273) is performed at a temperature range between a temperature between about 270°C and 280°C (Page 2, Line 10 of Kiichiro ‘273 teaches depositing silicon nitride at 270°C).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kiichiro ‘273’s silicon nitride layer deposition is performed at a temperature range between a temperature between about 270°C and 280°C into Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 in the manner set forth above, at least, because, as Kiichiro ‘273 teaches (Page 1, Line 65 to Page 2, Lines 1-11) having a substrate temp of 270°C provides a silicon nitride layer with a proven density to resist cracking in the silicon nitride layer thereby improving the reliability of the end device.
As incorporated, the silicon nitride deposition temperature taught by Kiichiro ‘273 would be used as the silicon nitride glue layer (7) deposition temperature would be used in the method of Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Molla ‘446 in view of Nasu ‘468 in view of Uzoh ‘214, in further view of Gulett et al. (US 4,330,569, hereinafter Gulett ‘569) in view of the following arguments.
With respect to Claim 6 Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 discloses all limitations of the method of claim 5,
But Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 fails to explicitly disclose further comprising: treating the glue layer with a flow of oxygen prior to depositing dielectric filling material.
Nevertheless, in a related endeavor (Fig 1-4 of Gulett ‘569), Gulett ‘569 discloses treating the glue layer (silicon nitride film, Fig 1 of Gulett ‘569, Col with a flow of oxygen prior (Col 4, Lines 8-11 disclose oxygen flow over silicon nitride layer) to depositing dielectric filling material. (15, Fig 4, Col 5, Lines 33-34 of Gulett ‘569).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gulett ‘569’s flow of oxygen prior to depositing dielectric filling material into Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214 in the manner set forth above, at least, because, as Gulett ‘569 teaches in Col 3, Lines 26-35, the oxygen treatment of a silicon nitride layer closely controls the topography of the layer and the method provides a time and costs saving over equivalent processes.
As incorporated, the oxygen flow taught by Gulett ‘569 would be used over the glue layer (7) prior to the deposition of dielectric filling material (40) of Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 and further modified by Uzoh ‘214.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Molla ‘446 in view of Nasu ‘468 in view of Uzoh ‘214 in view of Gulett ‘569 in further view of Hsu et al. (US 2021/0407802 A1, hereinafter Hsu ‘802), in view of the following arguments.
With respect to Claim 7 Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 as modified by Uzoh ‘214 and further modified by Gulett ‘569 discloses all limitations of the method of claim 6,
But Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 as modified by Uzoh ‘214 and further modified by Gulett ‘569 fails to explicitly disclose further comprising annealing the dielectric filling material at a temperature between about 270°C and 280°C.
Nevertheless, in a related endeavor (Para [0007] of Hsu ‘802), Hsu ‘802 teaches annealing the first dielectric filling material (silicon oxynitride, silicon carbine or carbon film, Para [0005] of Hsu ‘802) at a temperature between about 270°C and 280°C. (Para [0007] of Hsu ‘802 discloses an anneal process at a temperature of about 200°C to 600°C, therefore an embodiment where the temp range of between about 270°C and 280°C exists)(MPEP §2131.03, Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (citing In re Petering, 301 F.2d 676, 682, 133 USPQ 275, 280 (CCPA 1962)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hsu ‘802’s annealing the dielectric filling material at a temperature between about 270°C and 280°C into Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 as modified by Uzoh ‘214 and further modified by Gulett ‘569’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 as modified by Uzoh ‘214 and further modified by Gulett ‘569 in the manner set forth above, at least, because, as Hsu ‘802 teaches (Para [0007]) that this process controls the stress of the dielectric film layer and then specifically, as mentioned in the Abstract, further teaches that the process enables a reduced stress layer which would increase device reliability.
As incorporated, the annealing method of Hsu ‘802 would be used in the method of Haba ‘934 as modified by Molla ‘446 as modified by Nasu ‘468 as modified by Uzoh ‘214 and further modified by Gulett ‘569 to form the dielectric fill material (40 as modified above).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Yu et al. (US 2008/0142990 A1, hereinafter Yu ‘990) in view of Nasu ‘468, in view of the following arguments.
With respect to Claim 10 Haba ‘934 discloses a method, comprising:
attaching a first device die (left most 2, Fig 3, Para [0038]) and a second device die (second from left most die 2, Para [0038]) on a carrier wafer (3, Fig 3, Para [0038]), wherein a first gap (G, Fig 3, Para [0038]) is formed between the first device die (left most 2) and the second device die (second from left most die 2)(Fig 3A discloses arrangement);
depositing a first glue layer (7, Fig 11, Para [0059]) on exposed surfaces (10, Fig 11, Para [0059]) of the first device die (left most 2), the second device die (second from left most die 2), and the carrier wafer (3)(Fig 11 discloses 7 over top of first and second die and carrier wafer); wherein the first glue layer (7) comprises a nitrogen containing dielectric material (Para [0034] discloses 7 as silicon nitride);
depositing a first dielectric filling material (40, Fig 11, Para [0059]) on the first glue layer (7), wherein the first dielectric filling material (40) fills the first gap (G) between the first device die (left most 2) and second device die (second from left most die 2);
But Haba ‘934 fails to explicitly disclose forming a bonding dielectric layer over the first device die, the second device die, and the first dielectric filling material;
bonding a third device die and a dummy die on a top surface of the bonding dielectric layer, wherein a second gap is formed between the third device die and the dummy die;
depositing a second glue layer on sidewalls of the third device die and the dummy die and the top surface of the bonding dielectric layer; and
depositing a second dielectric filling material on the second glue layer, wherein the second dielectric filling material fills the second gap between the third device die and the dummy die.
Nevertheless, in a related endeavor (Fig 9-12 of Yu ‘990), Yu ‘990 discloses forming a bonding dielectric layer (58, Fig 10 of Yu ‘990, Para [0030]) over the first device die (36, Fig 6 of Yu ‘990, Para [0024]), the second device die (38, Fig 6 of Yu ‘990, Para [0024]), and the first dielectric filling material (56, Fig 8 of Yu ‘990, Para [0027]); bonding a third device die (68, Fig 12 of Yu ‘990, Para [0032]) and a die (70, Fig 12 of Yu ‘990, Para [0032]) on a top surface of the bonding dielectric layer (58)(Fig 12 of Yu ‘990 discloses 68 and 70 disposed on top of layer 58), wherein a second gap (gap of 71, Fig 12 of Yu ‘990, Para [0032]) is formed between (disclosed in Fig 12 of Yu ‘990) the third device die (68) and the die (70); depositing a second glue layer (69, Fig 12 of Yu ‘990, Para [0032]) on sidewalls (sides of die 68 and 70) of the third device die (68) and the die (70) and the top surface (top of 58) of the bonding dielectric layer (58); and depositing a second dielectric filling material (71, Fig 12 of Yu ‘990, Para [0032]) on the second glue layer (69), wherein the second dielectric filling material fills (71) the second gap (gap of 71) between the third device die (68) and the die (70).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yu ‘990’s forming a bonding dielectric layer over the first device die, the second device die, and the first dielectric filling material; bonding a third device die and a die on a top surface of the bonding dielectric layer, wherein a second gap is formed between the third device die and the die; depositing a second glue layer on sidewalls of the third device die and the die and the top surface of the bonding dielectric layer; and depositing a second dielectric filling material on the second glue layer, wherein the second dielectric filling material fills the second gap between the third device die and the die into Haba ‘934’s method. The ordinary artisan would have been motivated to modify Haba ‘934 in the manner set forth above, at least, because incorporating the additional layer of devices with the same dielectric protections of the first layer provides additional functionality for the end device while still maintaining the footprint of the first layer thereby saving valuable real estate in the end device.
As incorporated, a method of creating second device layer as taught by Yu ‘990 would incorporated over the first device layer in the method disclosed by Haba ‘934.
Haba ‘934 as modified by Yu ‘990 fails to explicitly disclose a dummy die.
But in a further embodiment (Fig 3C of Haba ‘934), Haba ‘934 further discloses a dummy die (Para [0038] discloses 2’ as a dummy die).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Haba ‘934’s further teaching of using a dummy die into Haba ‘934 as modified by Yu ‘990’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Yu ‘990 in the manner set forth above, at least, because, as Haba ‘934 teaches in Para [0038], placing dummy dies between the active die “can beneficially reduce the amount of protective material 7 used to fill the gaps G in subsequent steps and can enable conformal filling of the gaps G”, which can reduce the cost of the protective material per device and provide better protection through the conformal layer.
As incorporated, the dummy die (2’) of the further embodiment of Haba ‘934 would be placed by the device die (2) on the carrier wafer (3) of Haba ‘934 as modified by Yu ‘990.
Haba ‘934 as modified by Yu ‘990 fails to explicitly disclose wherein the first dielectric filling material is a low-k dielectric material.
Nevertheless, in a related endeavor (Fig 1A-3C of Nasu ‘468), Nasu ‘468 teaches and the dielectric filling material (12b, Fig 1B of Nasu ‘468, Para [0026]) is a low-k dielectric material (Para [0029] of Nasu ‘468 discloses the layer 12 is a low-k dielectric material).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Nasu ‘468’s teaching of wherein the first dielectric filling material is a low-k dielectric material into Haba ‘934 as modified by Molla ‘446’s method. Haba ‘934 as modified by Molla ‘446 discloses a method and structure for forming an integrated device package for direct bonding, specifically teaching dielectric materials between the devices. Haba ‘934 as modified by Molla ‘446 is open to the material of the dielectric filling material (40 of Haba ‘934) as Para [0059] discloses the “…protective material 40 can comprise any suitable material, including organic or inorganic materials”. Nasu ‘468 teaches a method and structure for forming dielectric structures around semiconductor devices for direct bonding. The ordinary artisan would have been motivated to look at Nasu ‘468 to modify Haba ‘934 as modified by Molla ‘446 for details on the dielectric filling material in the manner set forth above, at least, because, as Nasu ‘468 teaches in Para [0038] the use of the porous low k dielectric lowers resistance which allows the device to be sped up.
As incorporated, the teaching of using a dielectric filling material is a low-k dielectric material (12b) of Nasu ‘468 would be used as the material in the dielectric filling material (40) of Haba ‘934 as modified by Molla ‘446.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Yu ‘990 in view of Nasu ‘468 in further view of Venkatasubramanian et al. (US 2020/0027726 A1, hereinafter Venkatasubramanian ‘726) in view of the following arguments.
With respect to Claim 11 Haba ‘934 as modified by Yu ‘990 and further modified by Nasu ‘468 discloses all limitations of the method of claim 10, but Haba ‘934 as modified by Yu ‘990 and further modified by Nasu ‘468 fails to explicitly disclose wherein depositing the first dielectric filling material comprises: flowing a precursor gas containing NH3, SiH2Cl2 and C3H6 at a temperature below about 270°C.
Nevertheless, in a related endeavor (Para [0024 and 0025] of Venkatasubramanian ‘726), Venkatasubramanian ‘726 teaches depositing the first dielectric filling material comprises: flowing a precursor gas containing NH3, SiH2Cl2 and C3H6 at a temperature below about 270°C. (Para [0024 and 0025] of Venkatasubramanian ‘726 disclose forming a dielectric film (Para [0057] discloses dielectric film as silicon oxide. Para [0024 and 0025] disclose use of “one or more” precursor selected from…” and that list includes NH3, SiH2Cl2 and C3H6. Further Para [0025] discloses a deposition temperature of -50°C to 150°C which is below 270°C).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Venkatasubramanian ‘726’s teaching depositing the first dielectric filling material comprises flowing a precursor gas containing NH3, SiH2Cl2 and C3H6 at a temperature below about 270°C.into Haba ‘934 as modified by Yu ‘990 and further modified by Nasu ‘468’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Yu ‘990 and further modified by Nasu ‘468 in the manner set forth above, at least, because, as Venkatasubramanian ‘726 teaches in Para [0023] the method provides a dielectric film that are amorphous in nature and have a high density having a higher etch selectivity and low stress.
As incorporated, the precursor composition and deposition process taught by Venkatasubramanian ‘726 would be used to form the dielectric filling material (40) of Haba ‘934 as modified by Yu ‘990 and further modified by Nasu ‘468.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Yu ‘990 in view of Nasu ‘468 in view of Venkatasubramanian ‘726 in further view of LaVoie et al. (US 9,611,544 B2, hereinafter LaVoie ‘544) in view of the following arguments.
With respect to Claim 12 Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 and further modified by Venkatasubramanian ‘726 discloses all limitations of the method of claim 11, and Haba ‘934 further discloses wherein depositing the first dielectric filling material comprises:
depositing a first layer (Para [0052] discloses depositing layer 40 on layer 7) of the first dielectric filling material (40) on the first glue layer (7);
But Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 and further modified by Venkatasubramanian ‘726 fails to explicitly disclose exposing the first layer to an atmospheric environment; and depositing a second layer of the first dielectric filling material on the first layer.
Nevertheless, in a related endeavor (Fig 8 of LaVoie ‘544), LaVoie ‘544 teaches exposing the first layer to an atmospheric environment; and depositing a second layer of the first dielectric filling material on the first layer. (Col 24, Line 21-23 of LaVoie ‘544 disclose exposing first layer to atmospheric conditions between deposition).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate LaVoie ‘544’s s exposing the first layer to an atmospheric environment; and depositing a second layer of the first dielectric filling material on the first layer into Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 and further modified by Venkatasubramanian ‘726’s method. LaVoie ‘544 teaches a method of doped silicon oxide deposition to achieve the well-known advantage of filling gaps with a dielectric in a device structure. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 and further modified by Venkatasubramanian ‘726 in the manner set forth above, at least, because, as LaVoie ‘544 teaches in Col 24, Lines 35-37, this process enables a thicker film to be deposited at a higher deposition rate which will improve production rates.
As incorporated, the exposure of the first layer to an atmospheric environment and depositing the second layer of the first dielectric material as taught by LaVoie ‘544 would be incorporated into the method of Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 and further modified by Venkatasubramanian ‘726 to deposit first dielectric filling material (40).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Yu ‘990 in view of Nasu ‘468 in view of Venkatasubramanian ‘726 in view of LaVoie ‘544 in further view of Gulett ‘569 in view of the following arguments.
With respect to Claim 13 Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 discloses all limitations of the method of claim 12, but Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 fails to explicitly disclose treating the first glue layer with a flow of oxygen prior to depositing the first dielectric filling material.
Nevertheless, in a related endeavor (Fig 1-4 of Gulett ‘569), Gulett ‘569 discloses treating the glue layer (silicon nitride film, Fig 1 of Gulett ‘569, Col with a flow of oxygen prior (Col 4, Lines 8-11 disclose oxygen flow over silicon nitride layer) to depositing dielectric filling material. (15, Fig 4, Col 5, Lines 33-34 of Gulett ‘569).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gulett ‘569’s flow of oxygen prior to depositing dielectric filling material into Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 in the manner set forth above, at least, because, as Gulett ‘569 teaches in Col 3, Lines 26-35, the oxygen treatment of a silicon nitride layer closely controls the topography of the layer and the method provides a time and costs saving over equivalent processes.
As incorporated, the oxygen flow taught by Gulett ‘569 would be used over the glue layer (7) prior to the deposition of dielectric filling material (40) of Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 in view of Gulett ‘569 and in further view of Hsu ‘802 in view of the following arguments.
With respect to Claim 14 Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 and further modified by Gulett ‘569 disclose all limitations of the method of claim 13,
But Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 and further modified by LaVoie ‘544 and further modified by Gulett ‘569 fails to explicitly disclose further comprising: annealing the first dielectric filling material at a temperature between about 270°C and 280°C.
Nevertheless, in a related endeavor (Para [0007] of Hsu ‘802), Hsu ‘802 teaches annealing the first dielectric filling material (silicon oxynitride, silicon carbine or carbon film, Para [0005] of Hsu ‘802) at a temperature between about 270°C and 280°C. (Para [0007] of Hsu ‘802 discloses an anneal process at a temperature of about 200°C to 600°C, therefore an embodiment exists with a temp range of between about 270°C and 280°C)(MPEP §2131.03, Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (citing In re Petering, 301 F.2d 676, 682, 133 USPQ 275, 280 (CCPA 1962)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hsu ‘802’s annealing the dielectric filling material at a temperature between about 270°C and 280°C into Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 as modified by LaVoie ‘544 and further modified by Gulett ‘569’s method. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 as modified by LaVoie ‘544 and further modified by Gulett ‘569 in the manner set forth above, at least, because, as Hsu ‘802 teaches (Para [0007]) that this process controls the stress of the dielectric film layer and then specifically, as mentioned in the Abstract, further teaches that the process enables a reduced stress layer which would increase device reliability.
As incorporated, the annealing method of Hsu ‘802 would be used in the method of Haba ‘934 as modified by Yu ‘990 as modified by Nasu ‘468 as modified by Venkatasubramanian ‘726 as modified by LaVoie ‘544 and further modified by Gulett ‘569 to form the dielectric fill material (40).
Claims 21 and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Chiu et al. (US 9,922,895 B2, hereinafter Chiu ‘995) and in further view of Nasu ‘468 in view of the following arguments.
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With respect to Claim 21 Haba ‘934 discloses a method, comprising:
forming a semiconductor package (10, Fig 1A-1C) comprising:
a first device die (2, Fig 1B, Para [0031]) having a first sidewall (8, Fig 1B, Para [0031]) and a dielectric top surface (5, Fig 1B, Para [0031] discloses 5 (nonconductive area) as dielectric);
a dielectric filling material (40, Fig 11, Para [0059]) disposed along the first sidewall (8); and
a glue layer (7, Fig 11, Para [0059]) disposed between the first device die (2) and the dielectric filling material (40) (arrangement disclosed in Fig 11), wherein a first side (side of 7 touching sidewalls 8, reference annotated Fig 11) of the glue layer (7) is in contact with the first sidewall (8) of the first device die (2)(annotated Fig 11 discloses 7 contacting sidewall 8 of first device die), a second side (second side as shown in annotated Fig 11, Para [0059]) of the glue layer (7) is in contact with the dielectric filling material (40), the second side (second side as shown in annotated Fig 11) of the glue layer (7) and the dielectric top surface (5) of the first device die (2),
wherein the glue layer (7) comprises silicon nitride or silicon carbide nitride (Para [0034] discloses 7 as silicon nitride);
But Haba ‘934 fails to explicitly disclose wherein the first sidewall and the dielectric top surface form a first angle and the second side of the glue layer and the dielectric top surface of the first device form a second angle, and the first angle is greater than the second angle.
Nevertheless, in a related endeavor (Fig 11 of Chiu ‘895), Chiu ‘895 teaches wherein the first sidewall (36’, Fig 11 of Chiu ‘895, Col 6, Line 21) and the dielectric top surface (28, Fig 11 of Chiu ‘895, Col 6, Lines 28-30) form a first angle (angle 1 as shown on annotated Fig 11 of Chiu ‘895) and the second side (side of 60 along device 32 as shown in Fig 11 of Chiu ‘895) of the glue layer (60, Fig 11 of Chiu ‘895, Col 6, Lines 8-9) and the dielectric top (28) surface of the first device (32, Fig 11 of Chiu ‘895, Col 5, Line 63) form a second angle (angle 2 as shown on annotated Fig 11 of Chiu ‘895), and the first angle is greater than the second angle (annotated Fig 11 of Chiu ‘895 discloses angle 1 is greater than angle 2).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chiu ‘895’s wherein a sidewall of the first semiconductor die is sloped, and a first angle is formed between the sidewall of the first semiconductor die and the top surface of the carrier wafer; and the sidewall portion and the bottom portion form a second angle, and the second angle is greater than the first angle into Haba ‘934’s method. Chiu ‘895 teaches angles that can be formed in die singulation and a method to encapsulate them. The ordinary artisan would have been motivated to modify Haba ‘934 in the manner set forth above, at least, because, as Chiu ‘895 teaches (Col 6, Lines 21-37) encapsulating the angles formed in singulation can help to maintain the die shape during the manufacturing process.
As incorporated, the first and second angles of Chiu ‘995 would be used on the first and second angles of the device die (2) Haba ‘934.
But Haba ‘934 as modified by Chiu ‘995 fails to explicitly disclose and the dielectric filling material comprises a low-k dielectric material formed from one of TEOS and mDEOS.
Nevertheless, in a related endeavor (Fig 1A-3C of Nasu ‘468), Nasu ‘468 teaches and the dielectric filling material (12b, Fig 1B of Nasu ‘468, Para [0026]) comprises a low-k dielectric material formed from one of TEOS and mDEOS (Para [0026] of Nasu ‘468 discloses 12b formed from TEOS and Para [0029] of Nasu ‘468 discloses the layer 12 is a low-k dielectric material).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Nasu ‘468’s teaching of and the dielectric filling material comprises a low-k dielectric material formed from one of TEOS and mDEOS into Haba ‘934 as modified by Chiu ‘995’s method. Haba ‘934 as modified by Chiu ‘995 discloses a method and structure for forming an integrated device package for direct bonding, specifically teaching dielectric materials between the devices. Haba ‘934 as modified by Chiu ‘995 is open to the material of the dielectric filling material (40 of Haba ‘934) as Para [0059] discloses the “…protective material 40 can comprise any suitable material, including organic or inorganic materials”. Nasu ‘468 teaches a method and structure for forming dielectric structures around semiconductor devices for direct bonding. The ordinary artisan would have been motivated to look at Nasu ‘468 to modify as modified by Chiu ‘995 for details on the dielectric filling material in the manner set forth above, at least, because, as Nasu ‘468 teaches in Para [0038] the use of the porous low k dielectric lowers resistance which allows the device to be sped up.
As incorporated, the teaching of a dielectric filling material comprises a low-k dielectric material formed from one of TEOS and mDEOS (12b) of Nasu ‘468 would be used as the material in the dielectric filling material (40) of Haba ‘934 as modified by Chiu ‘995.
With respect to Claim 24 Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses all limitations of the method of claim 21, and Haba ‘934 discloses further comprising:
disposing a second die (second from left most die 2, Para [0038]) side-by-side with the first device die (2)(Fig 11 discloses a plurality of die 2), wherein the second die (second from left most die 2) has a second sidewall (sidewall of second die as shown in annotated Fig 11) facing the first sidewall (8) of the first device die (2), and the dielectric filling material (40) is disposed between the first sidewall (8) and second sidewall (sidewall of second die as shown in annotated Fig 11) (reference annotated Fig 11 for arrangement).
With respect to Claim 25 Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses all limitations of the method of claim 24, and Haba ‘934 further discloses wherein the second die (second from left most die 2) is a device die the second die (2) is a device die (Para [0038] discloses 2 as integrated device die).
With respect to Claim 26 Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses all limitations of the method of claim 24, and in a further embodiment (Fig 3C of Haba ‘934), Haba ‘934 further discloses wherein the second die (2’, Fig 3C, Para [0038]) is a dummy die (Para [0038] discloses 2’ as a dummy die).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teaching of the further embodiment of Haba ‘934’s dummy die along a device die into Haba ‘934 as modified by XXX’s device. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 in the manner set forth above, at least, because, as Haba ‘934 teaches in Para [0038], placing dummy dies between the active die “can beneficially reduce the amount of protective material 7 used to fill the gaps G in subsequent steps and can enable conformal filling of the gaps G”, which can reduce the cost of the protective material per device and provide better protection through the conformal layer.
As incorporated, the dummy die (2’) of the further embodiment of Haba ‘934 would be placed by the device die (2) on the carrier wafer (3) of Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468.
With respect to Claim 27 Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses all limitations of the method of claim 21, and Chiu ‘995 further teaches wherein the first device die (32 of Chiu ‘995) has a substrate portion (10, Fig 9 of Chiu ‘995, Col 2, Lines 46-48) and an interconnect structure portion (14, Fig 9 of Chiu ‘995, Col 2, Lines 47-50), the first sidewall (36’) is formed along the substrate portion (10) and the interconnect structure portion (14) (36’ formed along 10 and 14 is disclosed in Fig 17A of Chiu ‘995), the first sidewall (36’) is sloped on (Fig 16 and 17A of Chiu ‘995 disclose 36’ is sloped on interconnect 14) the interconnect structure portion (14), the glue layer 960, Fig 16 of Chiu ‘995, Col 6, Lines 3-5) has a substantially uniform thickness (60 having a uniform thickness on the substrate portion 10 of die 32 is disclosed in Fig 16 of Chiu ‘995) on the substrate portion (10) and an increasing thickness on (60 having an increasing thickness on the interconnect structure portion 14 of die 32 is disclosed in Fig 16 of Chiu ‘995) the interconnect structure portion (14). (Fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teaching of Chiu ‘995 of wherein the first device die has a substrate portion and an interconnect structure portion, the first sidewall is formed along the substrate portion and the interconnect structure portion, the first sidewall is sloped on the interconnect structure portion, the glue layer has a substantially uniform thickness on the substrate portion and an increasing thickness on the interconnect structure portion into Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468’s device. Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses a semiconductor structure with dielectric layers on the semiconductor dies. Chiu ‘995 further teaches that dies have sloped sides when separated from the substrate on which they were formed. The ordinary artisan would have recognized that the well-known die separation process would cause sloped sides on individual die that would be used in a package. The further teachings of Chiu ‘995 of how to encapsulate these die would have been motivating to the person of ordinary skill in the art then, as Chiu ‘995 teaches the process of how to encapsulate those slope die in order to uniformly spread the encapsulating material. (Col 6, Lines 8-20 of Chiu ‘995).
As incorporated, the teachings of Chiu ‘995 of the glue layer (60 of Chiu ‘995) is uniform on the substrate (10 of Chiu ‘995) and increases on the sloped interconnect structure (14 of Chiu ‘995) would be used as the thickness of the glue layer (7 of Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468) as it is used over the portions of the first device die (2 of Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Haba ‘934 in view of Chiu ‘995 in view of Nasu ‘468 and in further view of Madou (WO 91/11827 A1, hereinafter Madou ‘827) in view of the following arguments.
With respect to Claim 23 Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 discloses all limitations of the method of claim 21, but Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 fails to explicitly discloses further wherein the glue layer has a thickness in a range between about 750 angstroms and about 2000 angstroms.
Nevertheless, in a related endeavor (Fig 1 of Madou ‘827),, Madou ‘827 teaches wherein the glue layer (22, Fig 1 of Madou ‘827) has a thickness in a range between about 750 angstroms and about 2000 angstroms (Page 6, Line 4-7 disclose layer 22 as 500 angstroms).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Madou ‘827’s teaching of the glue layer having a thickness in a range between about 750 angstroms and about 2000 angstroms into Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468’s method. Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 teaches dielectric layers but is silent as to their thickness. Madou ‘827 teaches dielectric films and teaches thicknesses of the layers. The ordinary artisan would have been motivated to modify Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468 in the manner set forth above, at least, because, as Madou ‘827 teaches (Page 2, Lines 31-35 and Page 3, Lines 1-9) the taught thicknesses provide protection against high humidity or liquid damage to the device.
As incorporated, the dielectric thickness taught by Madou ‘827 would be in the glue layer (7) of Haba ‘934 as modified by Chiu ‘995 and further modified by Nasu ‘468.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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